201230269 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半i 是有關於-種具職點之:装導=:及基板’且特別 【先前技術】201230269 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semi-i is related to: a type of service: a package =: and a substrate' and a special [prior art]
用於電子穿3技步，使得封裝結構愈加廣泛地使 = ’如此能在維持既有之功能與效用下，得 格縮：化二；π:所需之配置空間，從而有效滿足曰趨規 、、、的市野需求，並提升使用上的便利性。 請同時參照第1Α圖至第汨圖，第1Α圖係 裝結構的剖視圖，第1Β圖係為第一種封裝：構之基 板的仰視圖。封裝結構1〇〇包含一基板11〇、一晶片12〇、 數個銲線130、一封膠140以及數個銲球15〇。Used for electronically wearing 3 steps, making the package structure more and more extensively = 'so can maintain the existing functions and effects, and it can be reduced: two; π: the required configuration space, thus effectively satisfying the trend The demand for the city, and the convenience of use. Please refer to the first to third figures at the same time. The first drawing is a cross-sectional view of the mounting structure. The first drawing is the bottom view of the first package: the base plate of the structure. The package structure 1A includes a substrate 11A, a wafer 12, a plurality of bonding wires 130, an adhesive 140, and a plurality of solder balls 15A.
基板110位於一電路板160上，並包含相對之一第一 面111與一第二面112、數個接墊113、數個連接點114以 及數個導電路徑115。接墊113位於第一面1Π上。連接點 114位於第二面112上’並以相等的間距w排列於基板110 之周邊。導電路控115位於基板110中，並電性連接接塾 113與連接點114。晶片120位於基板110之第一面m上， 並包含數個第一銲墊121與數個第二銲墊122。銲線130 電性連接晶片120之第一銲墊121與基板11〇之接墊113。 封膠140覆蓋基板11〇、晶片120與銲線130。銲球150位 於基板110之連接點114上，用以電性連接電路板ι60。 在封裝結構100中，由於只有第一銲塾121電性連接 至連接點114，而第二銲墊122則未電性連接至連接點 114。因此，在測試晶片12〇時’僅能對第一銲墊12ι進行 量測，卻無法對第二銲墊122作功能測試、量測或驗證。 201230269 請同時參照第2A圖至第2B圖，第2A圖係為習知第 二種封裝結構的剖視圖，第2B圖係為第二種封裝結構之基 板的仰視圖。第二種封裝結構100與上述之第二=ς 構100大致相同，故相似之處不再詳細贅述。 但是’在第二種封震結構100巾，所有的第-銲墊121 與第二銲墊122均透過銲線13G連接至連接點ιΐ4，並經 由銲球150連接至電路板16〇。然而，若未考慮曰 之第二銲墊122是否皆需要電性連接至電路板， 自對應設置銲球150的設計方式，將增加銲球15〇 ，量與成本，並佔用電路板16G不少的可用空間，從而影 響電路板160上的電路布局（Lay〇ut)。 此外，所有連接點114皆為同樣大小，並以相等的間 距W排列於基板11〇上，不易依實際設計需求 調整其間距W、數量、大小或排列方式。 彈r 【發明内容】 本發明之目的，係提供一種具測試點 板。封裝結構包含一基板以及至少一晶片。以 一測试區與至少一連接區，測試點位於測試區， 於連接區，以提升設計與測試上便利性。同時，_ 際需求適切地配置測試點於陣列型式之位置上，^ ，The substrate 110 is disposed on a circuit board 160 and includes a first surface 111 and a second surface 112, a plurality of pads 113, a plurality of connection points 114, and a plurality of conductive paths 115. The pad 113 is located on the first surface 1Π. The connection points 114 are located on the second surface 112' and are arranged at equal intervals w around the periphery of the substrate 110. The circuit control 115 is located in the substrate 110 and electrically connects the interface 113 to the connection point 114. The wafer 120 is located on the first side m of the substrate 110 and includes a plurality of first pads 121 and a plurality of second pads 122. The bonding wire 130 is electrically connected to the first pad 121 of the wafer 120 and the pad 113 of the substrate 11 . The sealant 140 covers the substrate 11 , the wafer 120 and the bonding wires 130 . The solder balls 150 are located on the connection points 114 of the substrate 110 for electrically connecting the circuit board ι60. In the package structure 100, since only the first pad 121 is electrically connected to the connection point 114, the second pad 122 is not electrically connected to the connection point 114. Therefore, the first pad 12i can only be measured while the wafer 12 is being tested, but the second pad 122 cannot be functionally tested, measured or verified. 201230269 Please refer to FIG. 2A to FIG. 2B simultaneously. FIG. 2A is a cross-sectional view of a second package structure, and FIG. 2B is a bottom view of the substrate of the second package structure. The second package structure 100 is substantially the same as the second structure 100 described above, so the similarities are not described in detail. However, in the second sealing structure 100, all of the first pad 121 and the second pad 122 are connected to the connection point ι 4 through the bonding wire 13G, and are connected to the circuit board 16 via the solder ball 150. However, if it is not considered whether the second pad 122 needs to be electrically connected to the circuit board, the design method of the corresponding solder ball 150 will increase the solder ball 15 〇, the amount and the cost, and occupy the circuit board 16G. The available space affects the circuit layout on the board 160 (Lay〇ut). In addition, all of the connection points 114 are of the same size and are arranged on the substrate 11 at equal intervals W. It is not easy to adjust the spacing W, the number, the size or the arrangement according to the actual design requirements. Bulletin R SUMMARY OF THE INVENTION An object of the present invention is to provide a test point board. The package structure includes a substrate and at least one wafer. With a test area and at least one connection area, the test points are located in the test area and in the connection area to improve design and test convenience. At the same time, the _ demand needs to properly configure the test point in the position of the array type, ^,
片的功能測試，亦不會限制電路板之電路佈局。 、BB 1包樣:：提出一種八具測試點之封裳結構， ^ ° δ基板以及一晶片。基板包含一第一面、一笛一而 數個第-測試點以及數個第—連接點。第二面 ^ 面’並具有-第-測試區與一第一連接@ '式 有數個第-位置，此些第-位置彼此間隔排列且;尸： 列型式。第一測試點位於第一測試區之第一」成= 201230269 連接點位於第-連接區。晶片位於第_面上，並包 第-銲塾與數個第二銲墊’第—銲塾電性 點，第二銲墊電性連接第一連接點。 女乐判忒 在一實施例中，此些第一測試點位於部分 -位置上，並排成-規則型式或—不規則型式，此 位置以-第-間距彼此間隔排列，此些第一連接點以 二間距彼此間隔排列，並形成至少_列或—圈 之外側、周圍或中間，第二間距等於或不等於第一間距。 本發明之另一態樣，.係提出一種具測試點之基板，其 包含-第-面、-第二面、數個第一接墊、數個第二接墊： 數個第一測試點以及數個第一連接點。第一接墊 二 墊位於第一面上。第二面相對於第一面，並具有二第= 試區與-第-連接區，第—測試區具有數個第—位置，此 些第一位置彼此間隔排列且形成一陣列型式。第一 位於第一測試區之第一位置上，並電性連接第一接墊。 一連接點位於第一連接區，並電性連接第二接墊。 在一實施例中，此些第一測試點位於部分或全部 一位置上，並排成一規則型式或一不規則型式，此些 位置以一第一間距彼此間隔排列，此些第一連接點&一 二間距彼此間隔排列，並形成至少一列或一圈於第一位 之外側、周圍或中間’第二間距可等於或不等於第一間距。 在一實施例中，基板包含數個第二測試點，第二面具 有一第二測試區，第二測試區具有數個第二位置。此些g 二位置以一第三間距彼此間隔排列且形成另一陣列型^， 第二間距不等於第一間距，第二測試點位於第二位置上。 在一實施例中，基板更包含數個第二連接點，第二面 ^具有-第二連接區，第二連接區與第—連接區分別位於 第-測試區之中央及翻’第二連接點位於第二連接區， 201230269 第連接點與第二連接點上設有數個銲球。 含一第一而、二^ 日片 第二晶片。基板包 〇 ^ 第一面、數個第一測試點以及數個第一連 =接f目對於第一面，並具有-第-測試區：-ί 彼此間隔排列且形成一陣列】 二第位置 -晶片位於ϊ—1第—連接點位於第—連接區。第 點。第二曰片你㈣’並電性連接第一測試點與第一連接 測試點與^曰一連接晶片或第一面上，並電性連接第一 -位中’此些第一測試點位於部分或全部的第 =第1成—_型式或一不規則型式’此 ίϊίΓ二，此間隔排列，此些第-連接點：-第-=形=-列或-圈於第-位t 本發明或不等於第-間距。 包含-第-面出：測=之=，其 導電路徑、數個第二導電路：1第:接U個第-一 ί接點。第-接墊與二接== 連接第二:導生 接區。第一測試區具有數個 成:陣列型式。第-測試“ 在-實施例ί第二導電路徑。 -位置上，並排成-規或=第的—第 201230269 位置以一第一間距彼此間隔排列，此些第一連接點以一第 , 二間距彼此間隔排列，並形成至少-列或-圈於第—位置 ‘ 之外側、周圍或中間，第二間距等於或不等於第一間距。 在-實施例中，基板包含數個第二測試點，第二面具 有-第二測試區，第二測試區具有數個第二位置。此些第 二位置以一第三間距彼此間隔排列且形成另一陣列型 第三間距不等於第一間距，第二測試點位於第二位置上。 在一實施例中，基板更包含數個第二連接點，第二面 iU二ί接區。第二連接區與第一連接區分別位於 # =-測试區之中央及周圍，第二連接點位於第二連接區， 第一連接點與第二連接點上設有數個銲球。 【實施方式】 ^了使本發明之敘述更加詳盡與完備，可參照所附之 :以下所述各種實施例’圖式中㈣之號碼代表相同 im。另一方面’眾所週知的元件與步驟並未描 述於實施例中，以避免造成本發明不必要的限制。 請參照第3A圖至第3B圖，第3A圖係繪示本發 例中具測試點之封裝結構的剖視圖，第3B圖係繪示 J施例t具測試點之基板的仰視圖。封裝結構2〇 έ 一基板210以及一第一晶片261。 0 …基板210包含一第一面2U、一第二面212、數 測試點233與數個第一連接點235。篦_ & m 4 第 一面211 *目士 逆按點235第一面212相對於第 第一、有一第一測試區221與一第一連接區223。 f 區221具有數個第一位置231，此些第一位 以一第一間距W1彼此間隔排列且形成一陣列型式。 部的Ϊ些位於第一測試區221中部分或全 <置231上，並排成一規則型式或一不規則型 201230269 式。例如’在第3B圖中，此些第一測試點233位於部分的 第一位置231上’並排成不規則架式。同時，通常只有第 一測試點233會顯現於基板21〇上，而第一位置231則不 會顯現於基板21〇上，故以虛線之圓圈表示第一位置23卜 此些第一連接點235位於第一連接區223 ,並以一第 二間距W2彼此間隔排列’且此些第一連接點235形成至 少一列或至少一圈於此些第一位置231之外側、周圍或中 間。第二間距W2可等於或不等於第一間距wi，以增加設 計上的彈性。而且，第一測試點233與第一連接點235之 配置方式及數量，亦可依照實際設計需求而變更或增減。 第一晶片261位於第一面211上，並包含數個第一銲 墊263與數個第二銲墊264。第一銲墊263電性連接至第 一測試點233，第二銲墊264電性連接至第一連接點235。 基板210可包含數個第一接墊241以及數個第二接墊 242。第一接塾241位於第一面211上，並電性連接第一銲 塾加與第一測試點233。第二接墊24== 上’並電性連接第二銲墊264與第一連接點235。 基板210可包含數個第一導電路徑251以及數個第二 導電路徑252。第一導電路徑2M位於基板210中，並電 性連接第一接塾241與第一測試點233。第二導電路徑252 位於基板210中’並電性連接第二接塾242血第一遠接點 ，第-導電路徑251與第二導電路徑252^為導 貫穿孔、導電材料、金屬材料、導電層、金屬層、導電線、 電路線或其任意組合。 封裝結構200可包含數個第一銲線271與數個第二銲 線272。第一銲線271用以電性連接第一銲墊263與第一 接塾241，第一知線272用以電性連接第二鲜塾264與第 二接墊242。但是，第一銲腺271與第二銲線272亦可以 201230269 銲球或其他導電元件取代之。 封裝結構200可包含一封膠280，封膠280覆蓋基板 210、第一晶片261、第一銲線271與第二銲線272。另外， 封裝結構200可包含數個銲球281 ’此些銲球281位於基 板210之第一連接點235上。 由上述可知，藉由將基板210之第二面212區分為第 一測試區221與第一連接區223，並將第一測試點233與 第一連接點235分別設置在第一測試區221及第一連接區 223上，有利於分辨及設計。而且，將數個第一位置231 形成一陣列型式，並將第一測試點233對應設置於第一位 馨 置231上，在第一晶片261進行測試時，各第一測試點233 可精確地與測試治具之各探針（圖未示）相互定位，以提升 實際操作上的準確性與便利性’有效進行第一晶片261之 開路/閉路測試、功能驗證、電性量測或不良品分析等作業。 在第3A圖中，封裝結構200之第一連接點235可透 過銲球281電性連接至電路板290。但第一測試點233上 不設置銲球281，以減少佔用電路板290的可用空間，亦 不會影響電路板290上的電路布局，還能降低銲球281的 設置數量與成本。 ® 請參照第4A圖至第4B圖，第4A圖係繪示本發明第 二實施例中具測試點之封裝結構的剖視圖，第4B圖係繪系 第二實施例中具測試點之基板的仰視圖。封裝結構200包 含一基板210、一第一晶片261以及一第二晶片262。 基板210包含一第一面211、一第二面212、數個第〆 測試點233與數個第一連接點235。第二面212相對於第 一面211，並具有一第一測試區221與一第一連接區223。 第一測試區221具有數個第一位置231，此些第—位置231 以一第一間距W1彼此間隔排列且形成一陣列型式。 201230269 此些第一測試點233位於第一測試區221中部分或全 部的第一位置231上，並排成一規則型式或一不規則型 式。例如，在第4B圖中’此些第一測試點233位於部分的 第一位置231上’並排成不規則型式。同時，通常只有第 一測試點233會顯現於基板210上，而第一位置23/則不 會顯現於基板210上’故以虛線之圓圈表示第一位置231。 此些第一連接點235位於第一連接區223，並以一第 二間距W2彼此間隔排列，且此些第一連接點235形成至 少一列或至少一圈於此些第一位置231之外側、周圍或中 間。第二間距W2可等於或不等於第一間距wi，以增加設 計上的彈性。而且，第一測試點233與第一連接點235之 配置方式及數量’亦可依照實際設計需求而變更或增減。 第一晶片261位於第一面211上，並包含數個第一鮮 墊263與數個第二銲墊264，第一銲墊263電性連接至第 一測試點233，第二銲墊264電性連接至第一連接點235。 第一晶片262位於第一晶片261上’並包含數個第三輝塾 265與數個第四銲塾266 ’第三銲塾· 265電性連接第一測試 點233 ’第四銲墊266電性連接第一連接點235。 基板210可包含數個第一接塾241、數個第二接塾 242、數個第三接墊243以及數個第四接墊244。第一接墊 241至第四接墊244均位於第一面211上，第一接塾241 電性連接第一銲墊263與第一測試點233，第二接墊242 電性連接第一銲墊264與第一連接點235，第三接墊243 電性連接第三銲墊265與第一測試點233，第四接墊244 電性連接第四銲墊266與第一連接點235。 基板210可包含數個第一導電路徑251、數個第二導 電路徑252、數個第三導電路徑253以及數個第四導電路 徑254。第一導電路徑251至第四導電路徑254均位於基 201230269 一，第一導電路徑251電性連接第一接墊241與第 二^^33，第二導電路徑252電性連接第二接墊242 接點235，第三導電路徑253電性連接第三接墊 則試點233’第四導電路徑254電性連接第四接 故從第一連接點235。第一導電路徑251至第四導電 雷^ Α^為導通孔、貫穿孔、導電材料、金屬材料、導 電層、金屬層、導電線、電路線或其任意組合。 笛一 ^，結構200可包含一黏合層282，黏合層282位於The functional test of the chip does not limit the circuit layout of the board. BB 1 package:: A set of eight test points, a ^ ° δ substrate and a wafer. The substrate comprises a first face, a flute and a plurality of first test points and a plurality of first connection points. The second face ^ face' has a -th-test zone and a first connection @'-form having a plurality of first-positions, the first-positions being spaced apart from one another; and the corpse: column type. The first test point is located at the first of the first test zone. = 201230269 The connection point is located in the first connection zone. The wafer is located on the _th surface and includes a first solder bump and a plurality of second solder pads, a solder bump electrical point, and the second solder pad is electrically connected to the first connection point. In an embodiment, the first test points are located in a portion-position and arranged in a regular pattern or an irregular pattern, the positions being spaced apart from each other by a -first spacing, the first connections The dots are spaced apart from each other by two pitches and form at least the outer side, the periphery or the middle of the column or circle, and the second pitch is equal to or not equal to the first pitch. According to another aspect of the present invention, a substrate having a test point includes a -first face, a second face, a plurality of first pads, and a plurality of second pads: a plurality of first test points And a number of first connection points. The first pad two pads are located on the first side. The second side is opposite to the first side and has a second test zone and a -th connection zone. The first test zone has a plurality of first positions which are spaced apart from each other and form an array pattern. The first is located at the first position of the first test zone and electrically connected to the first pad. A connection point is located in the first connection area and is electrically connected to the second connection pad. In an embodiment, the first test points are located at a part or all of the positions, and are arranged in a regular pattern or an irregular pattern. The positions are arranged at a first interval, and the first connection points are arranged. < One or two pitches are spaced apart from each other and form at least one column or one turn on the outer side, around or in the middle of the first bit. The second pitch may or may not be equal to the first pitch. In one embodiment, the substrate includes a plurality of second test points, the second mask has a second test zone, and the second test zone has a plurality of second locations. The g two positions are spaced apart from each other by a third pitch and form another array type, the second pitch is not equal to the first pitch, and the second test point is located at the second position. In an embodiment, the substrate further includes a plurality of second connection points, the second surface has a second connection area, and the second connection area and the first connection area are respectively located at the center of the first test area and the second connection The point is located in the second connection area, and there are several solder balls on the connection point and the second connection point of 201230269. A first wafer, a second wafer, and a second wafer are included. The first package, the plurality of first test points, and the plurality of first connection points are connected to the first side, and have a -th test area: -ί are spaced apart from each other and form an array. - The wafer is located at the first connection point of the first connection point. The first point. The second cymbal you (4) 'and electrically connected to the first test point and the first connection test point and ^ 曰 one connected to the wafer or the first side, and electrically connected in the first - bit 'the first test point is located Part or all of the first = the first -_ type or an irregular type 'this ϊ Γ Γ , , , 此 此 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The invention is not equal to the first spacing. Including - the first face: test = =, its conductive path, a number of second conductive circuits: 1 first: connect U first - a ί contact. The first pad and the second connector == the second connection: the conduction zone. The first test zone has several arrays: array type. The first-test "in the second embodiment of the second conductive path - position, side by side - or the first - the 201230269 position is spaced apart from each other by a first spacing, the first connection point is a The two pitches are spaced apart from each other and form at least a column or a ring outside, around or in the middle of the first position, the second pitch being equal to or not equal to the first pitch. In an embodiment, the substrate comprises a plurality of second tests a second test area having a second test area, the second test area having a plurality of second positions. The second positions are spaced apart from each other by a third pitch and form another array type. The third pitch is not equal to the first pitch. The second test point is located at the second position. In an embodiment, the substrate further includes a plurality of second connection points, and the second surface is connected to the first connection area. #=- The second connection point is located at the center of the test area, and the second connection point is located at the second connection area. The first connection point and the second connection point are provided with a plurality of solder balls. [Embodiment] The description of the present invention is more detailed and complete. Can be referred to the attached: various implementations described below The numbers in the figure (4) represent the same im. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the present invention. Please refer to Figures 3A to 3B, 3A. The figure shows a cross-sectional view of the package structure with the test points in the present embodiment, and FIG. 3B shows a bottom view of the substrate of the test point of the embodiment 1. The package structure 2 〇έ a substrate 210 and a first wafer 261 0. The substrate 210 includes a first surface 2U, a second surface 212, a plurality of test points 233 and a plurality of first connection points 235. 篦_ & m 4 first surface 211 *Mesh reverse point 235 first The surface 212 is opposite to the first one, and has a first test area 221 and a first connection area 223. The f area 221 has a plurality of first positions 231, and the first positions are spaced apart from each other by a first pitch W1 and form a The array type is located in the first test area 221 in part or all of the 231, and arranged in a regular pattern or an irregular type 201230269. For example, in the 3B figure, the first test Point 233 is located on the first position 231 of the portion and is arranged side by side in an irregular frame. Only the first test point 233 will appear on the substrate 21〇, and the first position 231 will not appear on the substrate 21〇, so the first position 23 is indicated by a dotted circle, and the first connection points 235 are located first. The connection regions 223 are spaced apart from each other by a second pitch W2 and the first connection points 235 form at least one column or at least one turn of the outer sides, the periphery or the middle of the first positions 231. The second pitch W2 may be equal to Or not equal to the first spacing wi, to increase the flexibility of the design. Moreover, the arrangement and quantity of the first test point 233 and the first connection point 235 may also be changed or increased according to actual design requirements. The first wafer 261 is located on the first surface 211 and includes a plurality of first pads 263 and a plurality of second pads 264. The first pad 263 is electrically connected to the first test point 233, and the second pad 264 is electrically connected to the first connection point 235. The substrate 210 may include a plurality of first pads 241 and a plurality of second pads 242. The first interface 241 is located on the first surface 211 and electrically connected to the first soldering pad and the first test point 233. The second pad 24 == upper and electrically connects the second pad 264 with the first connection point 235. The substrate 210 can include a plurality of first conductive paths 251 and a plurality of second conductive paths 252. The first conductive path 2M is located in the substrate 210 and electrically connected to the first interface 241 and the first test point 233. The second conductive path 252 is located in the substrate 210 and electrically connected to the first contact point of the second interface 242. The first conductive path 251 and the second conductive path 252 are conductive through holes, conductive materials, metal materials, and conductive materials. A layer, a metal layer, a conductive line, a circuit line, or any combination thereof. The package structure 200 can include a plurality of first bonding wires 271 and a plurality of second bonding wires 272. The first bonding wire 271 is electrically connected to the first bonding pad 263 and the first bonding pad 241. The first bonding wire 272 is electrically connected to the second fresh squeezing 264 and the second bonding pad 242. However, the first solder gland 271 and the second bonding wire 272 can also be replaced by 201230269 solder balls or other conductive components. The package structure 200 may include a glue 280 covering the substrate 210, the first wafer 261, the first bonding wire 271 and the second bonding wire 272. In addition, the package structure 200 can include a plurality of solder balls 281' such solder balls 281 are located on the first connection point 235 of the substrate 210. As can be seen from the above, the second surface 212 of the substrate 210 is divided into the first test area 221 and the first connection area 223, and the first test point 233 and the first connection point 235 are respectively disposed in the first test area 221 and The first connection area 223 is advantageous for resolution and design. Moreover, the plurality of first positions 231 are formed into an array pattern, and the first test points 233 are correspondingly disposed on the first position 231. When the first wafer 261 is tested, each of the first test points 233 can be accurately Positioning each probe of the test fixture (not shown) to improve the accuracy and convenience of the actual operation 'effectively performing open/closed test, function verification, electrical measurement or defective product of the first wafer 261 Analysis and other operations. In FIG. 3A, the first connection point 235 of the package structure 200 can be electrically connected to the circuit board 290 through the solder balls 281. However, the solder ball 281 is not disposed on the first test point 233 to reduce the available space of the circuit board 290, nor to affect the circuit layout on the circuit board 290, and to reduce the number and cost of the solder balls 281. ® FIG. 4A to FIG. 4B, FIG. 4A is a cross-sectional view showing a package structure having a test point in a second embodiment of the present invention, and FIG. 4B is a view showing a substrate having a test point in the second embodiment. Bottom view. The package structure 200 includes a substrate 210, a first wafer 261, and a second wafer 262. The substrate 210 includes a first surface 211, a second surface 212, a plurality of second test points 233, and a plurality of first connection points 235. The second surface 212 is opposite to the first surface 211 and has a first test area 221 and a first connection area 223. The first test area 221 has a plurality of first positions 231, and the first positions 231 are spaced apart from each other by a first pitch W1 and form an array pattern. 201230269 The first test points 233 are located in a part or all of the first position 231 of the first test area 221 and are arranged in a regular pattern or an irregular pattern. For example, in Fig. 4B, 'the first test points 233 are located on the first position 231 of the portion' and arranged in an irregular pattern. At the same time, usually only the first test point 233 will appear on the substrate 210, and the first position 23/ will not appear on the substrate 210. Thus, the first position 231 is indicated by a dashed circle. The first connection points 235 are located at the first connection area 223 and are spaced apart from each other by a second spacing W2, and the first connection points 235 form at least one column or at least one circle outside the first positions 231. Around or in the middle. The second pitch W2 may or may not be equal to the first pitch wi to increase design flexibility. Moreover, the arrangement and number of the first test point 233 and the first connection point 235 may also be changed or increased or decreased according to actual design requirements. The first wafer 261 is located on the first surface 211 and includes a plurality of first fresh pads 263 and a plurality of second pads 264. The first pads 263 are electrically connected to the first test point 233, and the second pads 264 are electrically connected. The connection is made to the first connection point 235. The first wafer 262 is located on the first wafer 261' and includes a plurality of third illuminates 265 and a plurality of fourth solder pads 266. The third solder pads 265 are electrically connected to the first test point 233 'the fourth solder pads 266 The first connection point 235 is connected. The substrate 210 may include a plurality of first interfaces 241, a plurality of second interfaces 242, a plurality of third pads 243, and a plurality of fourth pads 244. The first pads 241 to the fourth pads 244 are both located on the first surface 211. The first pads 241 are electrically connected to the first pads 263 and the first test points 233, and the second pads 242 are electrically connected to the first pads. The pad 264 is electrically connected to the first pad 235 and the third pad 243 to the third pad 265 and the first test point 233. The fourth pad 244 is electrically connected to the fourth pad 266 and the first connection point 235. The substrate 210 can include a plurality of first conductive paths 251, a plurality of second conductive paths 252, a plurality of third conductive paths 253, and a plurality of fourth conductive paths 254. The first conductive path 251 to the fourth conductive path 254 are both located at the base 201230269. The first conductive path 251 is electrically connected to the first pad 241 and the second electrode 251, and the second conductive path 252 is electrically connected to the second pad 242. The third conductive path 253 is electrically connected to the third pad, and the fourth conductive path 254 of the pilot 233' is electrically connected to the fourth connection from the first connection point 235. The first conductive path 251 to the fourth conductive conductive electrode are via holes, through holes, conductive materials, metal materials, conductive layers, metal layers, conductive lines, circuit lines, or any combination thereof. The structure 200 may include an adhesive layer 282, and the adhesive layer 282 is located.
I笛阳日261與第二晶片262之間，用以黏合第一晶片261 興弟一晶片262。 抹97^裝^結構2〇0可包含數個第一銲球275、數個第二銲 捸數個第一銲線271以及數個第二銲線272。第一銲 276電性電一輝塾263與第一接墊241 ’第二鋅球 雷接第一銲墊264與第二接墊242，第一銲線271 第三銲墊265與第三接墊243，第二銲線272電 四銲墊266與第四接墊244。但是，第一銲球275 線—銲球276可以銲線或其他導電元件取代之，第一銲 、、、271與第二銲線272亦可以銲球或其他導電元件取代之。 —曰封震結構200可包含一封膠280，其覆蓋基板210、第 261、第二晶片262、第一銲球275、第二銲球276、 勺二鲜線271與第二銲線272。另外，封裝結構200亦可 匕含數個銲球28卜其位於基板210之第一連接點235上。 由上述可知，藉由將基板210之第二面212區分為第 一測試區221與第一連接區223，並將第一測試點233與 第一連接點235分別設置在第一測試區221與第一連接區 223 ’有利於分辨及設計。而且，將數個第一位置231形成 —陣列型式，並將第一測試點233對應設置於第一位置231 上，在第一晶片261與第二晶片262進行測試時，各第一 201230269 測試點233可精確地與測試治具之各探針（圖未示）相互定 位，以提升實際操作上的準確性與便利性，有效地進行開 路/閉路測試、功能驗證、電性量測或不良品分析等作業。 在第4A圖中，封裝結構200之第一連接點235 <透 過銲球281電性連接至電路板290。但第一測試點233上 不設置銲球281，以減少佔用電路板290的可用空間，济 不會影響電路板290上的電路布局，還能降低銲球281的 設置數量與成本。 請參照第5A圖至第5B圖，第5A圖係繪示本發明第 φ 三實施例中具測試點之封裝結構的剖視圖，第5B圖係繪示 第三實施例中具測試點之基板的仰視圖。 第三實施例之封裝結構200及基板210與上述第二實 施例大致相同，故相似之處不再詳細贅述。但是，在第三 實施例中，第一晶片261與第二晶片262均位於基板210 之第一面211上，此些第一測試點233排成一規則型式。 同時，在第5A圖中，封裝結構200具有數個第一銲 線27卜數個第二銲線272、數個第三銲線273及數個第四 銲線274。第一銲線271電性連接第一晶片261之第一銲 φ 墊263與基板21〇之第一接墊241。第二銲線272電性連 接第一晶片261之第二銲墊264與基板210之第二接墊 242。第三銲線273電性連接第二晶片262之第三銲墊265 與基板210之第三接墊243。第四銲線274電性連接第二 晶片262之第四銲墊266與基板210之第四接墊244。而 且’第一銲線271與第三銲線273亦可電性連接同一第三 接塾243，以透過同—第一測試點233測試第一晶片261 與第二晶片262相連接之訊號。 請參照第6A圖至圖6G圖，係繪示本發明各實施例中 具測試點之基板各種變化態樣的仰視圖。除上述第一實施 201230269 第三實施例之封裝結構·與基板 * 基板21G的測試區、連接區、測試點、連接胃、=ί •距、陣列型式、排列方式等，尚有許多二= 化與實施態樣，且均適用於上述各會樣的組合變 與基板210中，僅簡早列舉數種變化態樣，如下所述· 在第6A圖之變化態樣中，基板21〇包含 2fi122;f_T古第一Γ試點233以及數個第一連接點235。第二 面>212具有-第-測試區221與一第一連接區奶 測試區221具有數個第一位置23卜此些第一位置23ι以 第一間距W1彼此間隔排列且形成-陣列型式。第一遠 ，區223位於第一測試區221之外側或周目。此些第一測 試點233位於第一測試區221中全部的第一位置&!上， 並排成一規則型式。此些第一連接點235位於第一連接區 223 ’並形成二列或二圈於第一位置231之外側或周圍。而 ί ί些第一連接點235係以-第二間距W2彼此間隔排 列，第一間距W2可等於或不等於第一間距W1。 在第6B圖之變化態樣中，基板21〇包含一第二面 212數個第一測3式點233以及數個第一連接點235。第二 面212具有一第一測試區221與一第一連接區223，第一 測試區221具有數個第一位置231，此些第一位置以一第 一間距W1彼此間隔排列且形成一陣列型式。第一連接區 223位於第一測試區221之外側或周圍。此些第一測試點 233位於第一測試區221中部分的第一位置^'31上，、並排 成二規則型式。此些第一連接點235位於第一連接區223， 並形成一列或一圈於第一位置231之外側或周圍。而且， 此些第一連接點235係以一第二間距W2彼此間隔排列， 第二間距W2可等於或不等於第一間距wi。 在第6C圖之變化態樣中，基板210大致與第6B圖相 S3 13 201230269 同’故相似之處不再詳細贅述。主要差異在於，第6C圖之 第一位置231彼此交錯及間隔排列，且此些第一測試點233 排成一不規則型式。 在第6D圖之變化態樣中，基板21〇包含一第二面 212、數個第一測試點233以及數個第一連接點235。第二 面212具有一第一測試區221、一第二測試區222與一第 一連接區223。第一測試區221與第二測試區222各自具 有數個第一位置231 ’此些第一位置231以一第一間距 彼此間隔排列且形成一陣列型式。第一連接區223位於第 一測試區221與第二測試區222之中央及周圍。此些第一 測試點233位於第一測試區221中部分的第一位置231 上，並排成一不規則型式。此些第一連接點235位於第一 連接區223，並形成一列或一圈於第一位置231之中央及 周圍。而且，此些第一連接點235係以一第二間距W2、彼 此間隔排列，第二間距W2可等於或不等於第一間距wi。 在第6E圖之變化態樣中，基板21〇包含一第二面 212、數個第一測試點233、數個第二測試點234以及數個 第連接點235。第一面212具有一第一測試區221、一第 一測试區222與一第一連接區223。第一測試區221具有 數個第一位置231，此些第一位置231以一第一間距ψ1 彼此間隔排列且形成一陣列型式。第二測試區222位於第 一測試區221之中央，並具有數個第二位置232。此些第 二位置232以一第三間距W3彼此間隔排列且形成另二陣 列型式’第三間距W3大於第一間距wi。 第一連接區223位於第一測試區221與第二測試區222 ^卜側或周圍。此些第-測試點233位於第—測試區221 邛刀的第位置231上，並排成一規則型式。此些第二 測試點234位於第二測觀222中部分的第二位置二加了 201230269 並排成一不規則型式。此些第一連接點235位於第一 區223’並形成一列或-圈於第一位置231之外側或周圍。 而且’此些第-連接點235係以-第二間距W2彼此間 排列’第二間距W2可等於或不等於第一間距们 間距W3。 示一The first wafer 261 is bonded to the second wafer 262 between the second wafer 261 and the second wafer 262. The squeegee structure 2 〇 0 may include a plurality of first solder balls 275, a plurality of second solder joints, a plurality of first bonding wires 271, and a plurality of second bonding wires 272. The first soldering wire 276 and the first pad 241 'the second zinc ball are connected to the first pad 264 and the second pad 242, the first bonding wire 271, the third pad 265 and the third pad 243, the second bonding wire 272 is electrically connected to the fourth pad 266 and the fourth pad 244. However, the first solder ball 275-battery ball 276 may be replaced by a bonding wire or other conductive component, and the first solder, 271, and 271 may also be replaced by solder balls or other conductive components. The hemostatic structure 200 can include a glue 280 that covers the substrate 210, the 261th, the second wafer 262, the first solder ball 275, the second solder ball 276, the scoop two fresh line 271, and the second bonding wire 272. In addition, the package structure 200 can also include a plurality of solder balls 28 on the first connection point 235 of the substrate 210. As can be seen from the above, the second surface 212 of the substrate 210 is divided into the first test area 221 and the first connection area 223, and the first test point 233 and the first connection point 235 are respectively disposed in the first test area 221 and The first connection zone 223' facilitates resolution and design. Moreover, the plurality of first positions 231 are formed into an array pattern, and the first test points 233 are correspondingly disposed on the first position 231. When the first wafer 261 and the second wafer 262 are tested, the first 201230269 test points are respectively 233 can accurately position each probe of the test fixture (not shown) to improve the accuracy and convenience of actual operation, effectively perform open/closed test, function verification, electrical measurement or defective product. Analysis and other operations. In FIG. 4A, the first connection point 235 < of the package structure 200 is electrically connected to the circuit board 290 through the solder ball 281. However, the solder ball 281 is not disposed on the first test point 233 to reduce the available space of the circuit board 290, and the circuit layout on the circuit board 290 is not affected, and the number and cost of the solder balls 281 can be reduced. 5A to 5B, FIG. 5A is a cross-sectional view showing a package structure having a test point in the third embodiment of the present invention, and FIG. 5B is a view showing a substrate having a test point in the third embodiment. Bottom view. The package structure 200 and the substrate 210 of the third embodiment are substantially the same as those of the second embodiment described above, and thus the similarities are not described in detail. However, in the third embodiment, the first wafer 261 and the second wafer 262 are both located on the first surface 211 of the substrate 210, and the first test points 233 are arranged in a regular pattern. Meanwhile, in Fig. 5A, the package structure 200 has a plurality of first bonding wires 27, a plurality of second bonding wires 272, a plurality of third bonding wires 273, and a plurality of fourth bonding wires 274. The first bonding wire 271 is electrically connected to the first pad 263 of the first wafer 261 and the first pad 241 of the substrate 21. The second bonding wire 272 is electrically connected to the second pad 264 of the first wafer 261 and the second pad 242 of the substrate 210. The third bonding wire 273 is electrically connected to the third pad 265 of the second wafer 262 and the third pad 243 of the substrate 210. The fourth bonding wire 274 is electrically connected to the fourth pad 266 of the second wafer 262 and the fourth pad 244 of the substrate 210. Moreover, the first bonding wire 271 and the third bonding wire 273 may be electrically connected to the same third interface 243 to test the signal connecting the first wafer 261 and the second wafer 262 through the same first test point 233. Referring to Figures 6A through 6G, there are shown bottom views of various variations of the substrate having test points in various embodiments of the present invention. In addition to the above-described first embodiment 201230269, the package structure of the third embodiment and the test area, the connection area, the test point, the connection stomach, the distance, the array type, the arrangement mode, etc. of the substrate* substrate 21G, there are many With respect to the embodiment, and both of them are applied to the combination of the above-mentioned samples and the substrate 210, only a few variations are listed as described below, as described below. In the variation of FIG. 6A, the substrate 21 includes 2fi122. ;f_T ancient first pilot 233 and several first connection points 235. The second side > 212 has a - test area 221 and a first connection area milk test area 221 has a plurality of first positions 23, such first positions 23 i are spaced apart from each other by a first pitch W1 and form an array pattern . The first far zone 223 is located on the outer side or the periphery of the first test zone 221. The first test pilots 233 are located in all of the first positions &! in the first test zone 221 and are arranged in a regular pattern. The first connection points 235 are located in the first connection region 223' and form two or two turns on the outer side or the periphery of the first position 231. And the first connection points 235 are arranged at a distance from each other by a second pitch W2, and the first pitch W2 may be equal to or not equal to the first pitch W1. In the variation of FIG. 6B, the substrate 21A includes a second surface 212 and a plurality of first measurement points 233 and a plurality of first connection points 235. The second surface 212 has a first test area 221 and a first connection area 223. The first test area 221 has a plurality of first positions 231. The first positions are spaced apart from each other by a first pitch W1 and form an array. Type. The first connection region 223 is located on or around the outside of the first test zone 221. The first test points 233 are located at the first position ^'31 of the portion of the first test area 221, and are arranged in a two-rule pattern. The first connection points 235 are located in the first connection area 223 and form a column or a circle on the outer side or the periphery of the first position 231. Moreover, the first connection points 235 are spaced apart from each other by a second pitch W2, and the second pitch W2 may be equal to or not equal to the first pitch wi. In the variation of Fig. 6C, the substrate 210 is substantially the same as that of Fig. 6B, S3 13 201230269, and will not be described in detail. The main difference is that the first positions 231 of Fig. 6C are staggered and spaced apart from each other, and the first test points 233 are arranged in an irregular pattern. In a variation of Figure 6D, substrate 21A includes a second face 212, a plurality of first test points 233, and a plurality of first connection points 235. The second surface 212 has a first test area 221, a second test area 222 and a first connection area 223. The first test area 221 and the second test area 222 each have a plurality of first positions 231'. The first positions 231 are spaced apart from each other by a first pitch and form an array pattern. The first connection area 223 is located at the center and around the first test area 221 and the second test area 222. The first test points 233 are located on the first position 231 of the portion of the first test zone 221 and are arranged in an irregular pattern. The first connection points 235 are located in the first connection area 223 and form a column or a circle in the center and around the first position 231. Moreover, the first connection points 235 are arranged at a second pitch W2, spaced apart from each other, and the second pitch W2 may be equal to or not equal to the first pitch wi. In a variation of Figure 6E, substrate 21A includes a second face 212, a plurality of first test points 233, a plurality of second test points 234, and a plurality of first connection points 235. The first surface 212 has a first test area 221, a first test area 222 and a first connection area 223. The first test area 221 has a plurality of first positions 231, and the first positions 231 are spaced apart from each other by a first pitch ψ1 and form an array pattern. The second test zone 222 is located in the center of the first test zone 221 and has a plurality of second locations 232. The second positions 232 are spaced apart from each other by a third pitch W3 and form another array pattern. The third pitch W3 is larger than the first pitch wi. The first connection area 223 is located on or around the first test area 221 and the second test area 222. The first test points 233 are located at the first position 231 of the first test zone 221 and are arranged in a regular pattern. The second test points 234 are located in the second position of the second portion of the second survey 222, and are added to the 201230269 side by side into an irregular pattern. The first attachment points 235 are located in the first region 223' and form a column or circle around the outer side of the first location 231. Further, the "the first connection points 235 are arranged with the second pitch W2". The second pitch W2 may be equal to or not equal to the first pitch pitch W3. Show one
-在第6F圖之變化態樣中，基板21〇大致與第6£圖相 同，故相似之處不再詳細贅述。主要差異在於，第邡圖之 第位置231彼此父錯及間隔排列，此些第一測試點233 排成★不規則型式，第二測試區222位於第一測試區221 之角落，第三間距W3小於第一間距W1。 在第6G圖之變化態樣中，基板21〇包含一第二面 = 2^、數個第一測試點233、數個第一連接點235以及數個 一連接點236。第二面212具有一第一測試區221、一第 二連接區223與一第二連接區224。第一測試區221具有 個第=位置231，此些第一位置231以一第一間距W1 彼此間隔排列且形成一陣列型式。 π π第一連接區223與第二連接區224分別位於第-測試 ，21之周圍及中央。此些第—測試點⑶位於第一測試 的第一位置231上，並排成一不規則型式。 - “曾連接點235位於第—連接區223，並形成一列或 办认-厂位置231之外側或周圍。此些第二連接點236 i +一連接區224，並形成另一陣列型式於第一位置231 而且’此些第一連接點235或第二連接點236係 一間距W2彼此間隔排列，第二間距W2可等於或 不等於第一間距W1。 ，然本發明已以實;^方式揭露如上，然其並非用以限 明’任何熟習此技藝者’在不脫離本發明之精神和 fc圍内’當可作各種之更動與潤飾，因此本發明之保護範 201230269 圍當視後附之申請專利範圍所界定者為準 【圖式簡單說明] 能更下特徵、優點與實施例 ί= 種封裝結構的剖視圖。 第2A圖在1 種封裝結構之基板的仰視圖。 ==習知第二種封裝結構的剖視圖。 第3A圖===封裝結構之基板的仰視圖。 結構的剖視圖林發明第—實施例中具測試點之封裳 的仰ίΓ。圖鱗林發明第―實施射具測試點之基板 結構錢示本發㈣二實施射具㈣點之封震 的仰^林發明第二實施射具測試點之基板 結構輪本發明第三實施例中具測試點之封裝 第6A圖至第6G圖係繪示本發明各實施例中具測 點之基板各種變化態樣的仰視圖。 ° 111 :第一面 112 :第二面 主要元件符號說明】 1〇〇 :封裝結構 110 :基板 [S3 16 201230269- In the variation of Fig. 6F, the substrate 21 is substantially the same as the sixth embodiment, so the similarities will not be described in detail. The main difference is that the first position 231 of the first map is arranged in a wrong and spaced relationship with each other. The first test points 233 are arranged in an irregular pattern, the second test area 222 is located at the corner of the first test area 221, and the third interval W3 is Less than the first pitch W1. In a variation of the 6G diagram, the substrate 21A includes a second face = 2^, a plurality of first test points 233, a plurality of first connection points 235, and a plurality of connection points 236. The second surface 212 has a first test area 221, a second connection area 223 and a second connection area 224. The first test area 221 has a == position 231, and the first positions 231 are spaced apart from each other by a first pitch W1 and form an array pattern. The π π first connection region 223 and the second connection region 224 are located around and at the center of the first test 21, respectively. The first test points (3) are located at the first position 231 of the first test and are arranged in an irregular pattern. - "The connection point 235 is located at the first connection area 223 and forms a column or the identification-plant location 231 outside or around. These second connection points 236 i + a connection area 224 and form another array type a position 231 and 'the first connection point 235 or the second connection point 236 are spaced apart from each other by a spacing W2, and the second spacing W2 may be equal to or not equal to the first spacing W1. However, the present invention has been implemented in the manner of The above disclosure is not intended to limit the 'any skilled person' who can make various changes and refinements without departing from the spirit and scope of the present invention. Therefore, the protection model 201230269 of the present invention is attached. The scope of the patent application is defined as a simple description of the drawings. A more detailed description of the features, advantages, and embodiments of the package structure. Fig. 2A is a bottom view of the substrate of one package structure. A cross-sectional view of the second package structure. Fig. 3A === bottom view of the substrate of the package structure. The cross-sectional view of the structure of the invention is in the embodiment - the test piece with the test point of the seal. Substrate structure money with test points示本发(四)二 Implementing the sealing of the shot (4) point of the Yang Lulin invention The second embodiment of the substrate test wheel of the test point of the third embodiment of the present invention with the test point package 6A to 6G A bottom view showing various variations of a substrate having a measuring point in each embodiment of the present invention. ° 111: first surface 112: second surface main component symbol description] 1〇〇: package structure 110: substrate [S3 16 201230269
113 接墊 242 ： 第二接墊 114 連接點 243 ： 第三接墊 115 導電路徑 244 ： 第四接墊 120 晶片 251 ： 第一導電路徑 121 第一銲墊 252 ： 第二導電路徑 122 第二銲墊 253 ： 第三導電路徑 130 銲線 254 ： 第四導電路徑 140 封膠 261 ： 第一晶片 150 鲜球 262 ： 第二晶片 160 電路板 263 ： 第一銲墊 W ： 間距 264 ： 第二銲墊 200 封裝結構 265 ： 第三銲墊 210 基板 266 ： 第四銲墊 211 第一面 271 ： 第一銲線 212 第二面 272 ： 第二銲線 221 第一測試區 273 ： 第三銲線 222 第二測試區 274 ： 第四銲線 223 第一連接區 275 ： 第一銲球 224 第二連接區 276 : 第二鮮球 231 第一位置 280 ： 封膠 232 第二位置 281 ： 焊球 233 第一測試點 282 ： 黏合層 234 第二測試點 290 ： 電路板 235 第一連接點 W1 ： 第一間距 236 第二連接點 W2 ： 第二間距 241 第一接墊 W3 ： 第三間距 [s] 17113 pad 242: second pad 114 connection point 243: third pad 115 conductive path 244: fourth pad 120 wafer 251: first conductive path 121 first pad 252: second conductive path 122 second solder Pad 253: third conductive path 130 bonding wire 254: fourth conductive path 140 encapsulant 261: first wafer 150 fresh ball 262: second wafer 160 circuit board 263: first pad W: pitch 264: second pad 200 package structure 265 : third pad 210 substrate 266 : fourth pad 211 first surface 271 : first bonding wire 212 second surface 272 : second bonding wire 221 first test zone 273 : third bonding wire 222 Second test area 274: fourth bonding wire 223 first connection zone 275: first solder ball 224 second connection zone 276: second fresh ball 231 first position 280: sealant 232 second position 281: solder ball 233 first Test point 282: adhesive layer 234 second test point 290: circuit board 235 first connection point W1: first pitch 236 second connection point W2: second pitch 241 first pad W3: third pitch [s] 17