201220410 六、發明說明： [相關申請案之交互參照] 本申請主張於2010年7月9曰提出之韓國專利申請 案號10-2010-0066534,案名“半導體封裝基板及製造其 之方法（Semiconductor Package Substrate and Method for Manufacturing the Same)，，之優先權，該案之整個内 容在此一併提出以供參考。 【發明所屬之技術領域】 本發明係關於半導體封裝基板及製造其之方法。 【先前技術】 於需要快速反應於客戶需求並且減少開發週期之情況’ 縮短了產品週期，由於趨勢朝向使用半導體薄厚度基板， 因此帶狀基板和單元基板之翹曲已顯然成為需要解決之核 心技術問題，帶狀基板和單元基板各具有實際的尺寸交付 客戶公司。 於封裝半導體晶片於基板上時基板之翹曲導致晶片 受到損害，因此，半導體封裝事業要求必須審批關於新基 板之翹曲。 現行用來減少基板翹曲之方法可以分類成三種情況。 第一種方法藉由於基板中形成通過狹縫以解決基板 之勉曲作詩基板，第二财法藉由於基板巾插人硬度增 強詹增加對基板之㈣之抵抗以改善基板之勉曲 ，以及第 三種方法藉由調整主要引起基板之勉曲之阻焊層和銅層之 虛擬區域以減少基板之翹曲。 95260 ⑧ 4 201220410 ^而’這些方法雖然可以改善帶狀基板之翹曲，但是 不能解決產生於單元尺寸基板之翹曲。 接著，將參照第1和2圖示意地說明依照先前技術之 半導體封裝基板之結構。 參照第1圖’半導體封裝基板10具有用於電路之金 屬層’例如’第一銅層12a和第一表面處理層13a，該第 一表面處理層13a構成形成在核心絕緣層η之一個表面上 (例如’組件表面）之隆起墊；以及用於電路之金屬層，例 如’第二銅層12b和第二表面處理層13b，該第二表面處 理層13b構成形成在核心絕緣層11之另一個表面上（例 如’焊接表面）之焊接墊。 第一銅層12a和第二銅層12b，以及形成在核心絕緣 層11之一個表面上之第一表面處理層13a和第二表面處理 層13b習用上係對稱，並且實質上具有相同的厚度。 此處’由於在構成基板之幾層間之不同的熱膨脹係數 (CTE)，和涉及於封裝生產過程中溫度的改變，如第2圖中 所示，於單元大小的最終產品中產生翹曲，而使得組件表 面（於圖式中上表面）為凹入翹曲的，或者反之，組件表面 為凸出翹•曲的。 因此’急迫需要一種解決作為最終產品之帶狀大小的 基板之翹曲和產生於單元大小的基板中翹曲之方法。 【發明内容】 經過努力研發本發明提供一種能夠符合趨向薄厚度產 品’同時具有最實質影響基板之紐曲之半導體封裝基板， 5 95260 201220410 及製造其之方法。 於=ί過努力研發本發明提供一種能夠相應地應用 於-個射出模（shQtmQld)，同時具有最 板 曲之半導騎裝基板，及製造其之方法。a基板之也 A板又過”研發本發明提供一種能夠改善面板 基板#練、和早域板讀肖之 及製造其之方法。 了装基板 依照本發明之較佳實施例，其係 基板，包含：基底基板，具有形成在^個=導體封裝 表面和形成在其另—個表面上之焊接表組件 有形成在其中之電路圖Μ該組件表面之牛表面具 來安裝半導體之隆㈣，而該焊接表Μ =包含用 電路圖案且該焊接表面之電路圖案包成在其中之 合之焊接^形成在該組件表面之隆妓上4部組件結 理層；以及形成在該焊接表面之焊接墊上之=第〜表面處 層。此處，該第一表面處理層與該 二表面處理 同的厚度。 一面處理層具有不 基底基板可具有用於内層電路之 第-表面處理層與第二錢錄層間之=多層基板。 ΙΟμιη。 又差可以是3至 第-表面處理層可包含第一錢錄層 第二表面處理層可包含第二錄錄層和第 _金層而 鍵鎳層具有與第一鍛錄層不同的厚声 層’ §亥第一 第-鑛鎳層與第二錢錦層間之厚度差 又σ以是3至1〇 95260 6 201220410 A m ° 第鑛鎳層可具有3至12口之厚度，而第二鑛鎳層 可具有6至15以m之厚度。 第鍛錦層可以具有6至之厚度，而第二鍍錄 層可具有3至丨2//m之厚度。 半導體封裝基板可以進一步包含分別形成在基底基 板之二個表面以轉層’靠烊層具有用來分別暴露隆起 墊和焊接墊之開口部分。 依照本發明之另一個較佳實施例，提供一種製造半導 體封裝基板之方法，該方法包含：設置基底基板，其具有 幵1在其個表面上之組件表面和形成在其另—個表面上 之焊接表面’該組件表面具有形成在其中之電路圖案且該 組件表面之電路圖案包含用來安裝半導體之隆起墊，而該 焊接表面具有形成在其中之電關案且該焊接表面之電路 圖案包含絲與外部組件結合之焊接墊；以及在該 面之隆起塾上和在該焊接表面之焊接墊上分別形成第一表 面處理層和第二表面處理層。此處，該第—表面處理層與 該弟二表面處理層具有不同的厚度。 基底基板可以是具有用於内層電路之金屬層之多層 基板。 當設置之基底基板以朝向組件表面為凸出勉曲時，第 -表面處理層之厚度可形成大於第二表面處理層之厚度。 當設置之基底基板以朝向組件表面為凹入赵曲時，第 -表面處理層之厚度可形成小於第二表面處理層之厚度。 95260 7 201220410 第一表面處理層與第二鍍鎳層間之厚度差可以是3至 ， 10 以 m。201220410 VI. Description of the invention: [Related References of Related Applications] This application claims the Korean Patent Application No. 10-2010-0066534 filed on Jul. 9, 2010, entitled "Semiconductor Package Substrate and Method of Manufacturing the Same (Semiconductor) The entire contents of the present application are hereby incorporated by reference. The present invention relates to a semiconductor package substrate and a method of fabricating the same. Prior Art] The need to quickly respond to customer needs and reduce the development cycle' shortened the product cycle. As the trend toward the use of semiconductor thin-thickness substrates, the warpage of the strip substrate and the unit substrate has clearly become a core technical problem to be solved. The strip substrate and the unit substrate are each delivered to the customer's company in actual size. When the semiconductor wafer is packaged on the substrate, the warpage of the substrate causes the wafer to be damaged. Therefore, the semiconductor packaging business requires approval of the warpage of the new substrate. The method to reduce substrate warpage can be classified into three In the first method, since the substrate is formed through the slit to solve the distortion of the substrate, the second method increases the resistance of the substrate by increasing the hardness of the substrate to improve the distortion of the substrate. And the third method reduces the warpage of the substrate by adjusting the dummy regions of the solder resist layer and the copper layer which mainly cause the distortion of the substrate. 95260 8 4 201220410 ^ While these methods can improve the warpage of the strip substrate, However, the warpage caused by the cell size substrate cannot be solved. Next, the structure of the semiconductor package substrate according to the prior art will be schematically explained with reference to Figs. 1 and 2. Referring to Fig. 1 'the semiconductor package substrate 10 has a metal layer for the circuit. 'for example, a first copper layer 12a and a first surface treatment layer 13a, the first surface treatment layer 13a constituting a ridge pad formed on one surface of the core insulating layer η (for example, a 'component surface); and a metal for the circuit a layer such as a 'second copper layer 12b and a second surface treatment layer 13b, which is formed on the other surface of the core insulating layer 11 ( For example, a solder pad of a 'welding surface.' The first copper layer 12a and the second copper layer 12b, and the first surface treatment layer 13a and the second surface treatment layer 13b formed on one surface of the core insulating layer 11 are conventionally symmetric. And substantially the same thickness. Here 'because of the different coefficients of thermal expansion (CTE) between the layers constituting the substrate, and the temperature changes involved in the package production process, as shown in Fig. 2, in the cell size Warpage occurs in the final product, so that the surface of the component (upper surface in the drawing) is concavely warped, or vice versa, the surface of the component is convex and curved. Therefore, 'there is a need for a solution to the final product. The warp of the strip-sized substrate and the method of warping in the substrate of the unit size. SUMMARY OF THE INVENTION The present invention has been made in an effort to develop a semiconductor package substrate that can conform to a product that tends to be thin and has the most substantial influence on the substrate, 5 95260 201220410, and a method of manufacturing the same. The present invention provides a semi-guided riding substrate which can be applied to an ejection die (shQtmQld) at the same time, and has the most curved plate, and a method of manufacturing the same. The invention also provides a method for improving the panel substrate #, and the early domain plate, and the method for manufacturing the same. The substrate is in accordance with a preferred embodiment of the present invention, and the substrate is The method comprises: a base substrate having a soldering surface formed on the surface of the conductor package and formed on the other surface thereof, wherein the surface of the surface of the component is mounted to mount the semiconductor (4), and Soldering surface Μ = includes a circuit pattern and the circuit pattern of the soldering surface is packaged into a solder joint formed on the ridge of the component surface; and a soldering pad formed on the soldering surface of the soldering surface The first surface treatment layer has the same thickness as the two surface treatments. The one side treatment layer has a non-base substrate and may have a first surface treatment layer for the inner layer circuit and the second surface layer. = multilayer substrate. 又μιη. The difference may be 3 to the first surface treatment layer may comprise a first recording layer. The second surface treatment layer may comprise a second recording layer and a _ gold layer and the bonding nickel layer has The thickness of the difference between the thickness of the first forging layer and the thickness of the second layer of gold and the second layer of gold is 3 to 1〇95260 6 201220410 A m ° The layer of the first ore layer may have 3 To a thickness of 12, and the second mineral nickel layer may have a thickness of 6 to 15 m. The first forging layer may have a thickness of 6 to 6, and the second plating layer may have a thickness of 3 to 丨2//m. The semiconductor package substrate may further include opening portions respectively formed on the two surfaces of the base substrate to form a turn-over layer having openings for respectively exposing the bumps and the solder pads. According to another preferred embodiment of the present invention, a A method of manufacturing a semiconductor package substrate, the method comprising: providing a base substrate having a surface of a component of a crucible 1 on a surface thereof and a soldering surface formed on another surface thereof, the surface of the component having a circuit pattern formed therein And the circuit pattern on the surface of the component includes a bump for mounting a semiconductor, and the solder surface has an electrical gate formed therein and the circuit pattern of the solder surface includes a solder pad bonded to the external component; A first surface treatment layer and a second surface treatment layer are respectively formed on the ridges of the surface and on the solder pads of the soldering surface. Here, the first surface treatment layer and the second surface treatment layer have different thicknesses. The substrate may be a multilayer substrate having a metal layer for the inner layer circuit. When the base substrate is disposed to be convexly curved toward the surface of the component, the thickness of the first surface treatment layer may be formed to be greater than the thickness of the second surface treatment layer. When the base substrate is disposed to be concave toward the surface of the component, the thickness of the first surface treatment layer may be formed to be smaller than the thickness of the second surface treatment layer. 95260 7 201220410 Thickness difference between the first surface treatment layer and the second nickel plating layer It can be 3 to 10 in m.
W 形成該第一表面處理層和該第二表面處理層可以包含： · 分別於基底基板之組件表面之隆起墊與焊接表面之焊接墊 上形成第一鍍鎳層和第二鍍鎳層，以及分別於該一鍍鎳層 和該第二鍍鎳層上形成第一鍍金層與第二鑛金層。此處， 該第一鍍鎳層與第二鍍鎳層可形成具有不同的厚度。 第一鍍鎳層與第二鍍鎳層間之厚度差可以是3至10 y m 〇 當基底基板以朝向組件表面為凸出翹曲時，第一錄錦 層之厚度可形成大於第二鍍鎳層之厚度。 第一鍍鎳層可以具有6至15#m之厚度，而第二鍍鎳 層可具有3至12/zm之厚度。 當基底基板以朝向組件表面為凹入翹曲時，第一鍍鎳 層之厚度可形成小於第二鍍鎳層之厚度。 第一鍍鎳層可以具有3至I2wm之厚度，而第二鍍鎳 層可具有6至15//m之厚度。 本方法可以進一步包含於設置該基底基板後形成具 有開口部分之阻焊層於該基底基板之二個表面，該開口用 來分別暴露隆起墊和焊接墊。 【實施方式】 由下列參照伴隨圖式之實施例之詳細說明，本發明之 各種目的、優點、和特徵將變得报清楚^於本說明書中， 遍及圖式帽加於組件之元件符號，應該注 意到即使組件 8 95260 ⑧ 201220410 Μ示於*同的圖式中’但是相同的組件符號表示相同的組 m ’應該知道於圖式中各崎之大小僅僅顯示說明 • 用’而並不整個地反應組件之實際大小。 再者，當判定相關於本發明之已知技藝之詳細說明可 能掩蓋了本發明之目的時，則將省略其詳細說明。於詳細 說明中’ 5司囊「第-」、「第二」、等等係用來區別一個組件 與另一個組件，而該等組件並不受上述詞彙之限制。 —如使用於本發明巾的，詞彙「組件表面」意指半導體 元件般安裝於其上之表面’而詞彙「焊接表面」意指焊 球一般安裝於其上用來與外部組件結合之表面。 如使用於本發明中的，表示“當朝向組件表面為凸出 麵曲時t指基板根據其核心層相對凸出和麵曲於組件表 面和焊接表面之垂直於組件表面方向之情況。相似於此情 況，如使用於本發明中的，表示「當以朝向組件表面為凹 入魏曲時」意指基板根據其核心層相對凸出和_曲於組件 表面和焊接表面之垂直於焊接表面方向之情況。 半導體封裝基板之翹曲導自於構成基板之數層之不 同的熱膨脹係數’和涉及於封裝生產過程中溫度的改變。 因此，於本發明中，以不同的方式調整組件表面之厚 度和焊接表面之厚度，以產生其應力於相反於彼此相關於 產生翹曲之應力方向的方向，結果，能夠抵銷彼此相反之 熱應力，由此改善基板之翹曲。 下文中，將參照所附圖式詳細說明本發明之較佳實施 例0Forming the first surface treatment layer and the second surface treatment layer may comprise: forming a first nickel plating layer and a second nickel plating layer on the bonding pads of the bump pads and the soldering surface of the component surface of the base substrate, respectively Forming a first gold plating layer and a second gold layer on the nickel plating layer and the second nickel plating layer. Here, the first nickel plating layer and the second nickel plating layer may be formed to have different thicknesses. The difference in thickness between the first nickel plating layer and the second nickel plating layer may be 3 to 10 ym. When the base substrate is convexly warped toward the surface of the component, the thickness of the first recording layer may be formed larger than the second nickel plating layer. The thickness. The first nickel plating layer may have a thickness of 6 to 15 #m, and the second nickel plating layer may have a thickness of 3 to 12/zm. When the base substrate is concavely warped toward the surface of the component, the thickness of the first nickel plating layer may be formed to be smaller than the thickness of the second nickel plating layer. The first nickel plating layer may have a thickness of 3 to 12 mm, and the second nickel plating layer may have a thickness of 6 to 15 // m. The method may further include forming a solder resist layer having an opening portion on the two surfaces of the base substrate after the base substrate is disposed, the openings for respectively exposing the bump pad and the solder pad. The various objects, advantages, and features of the present invention will become apparent from the following description of the embodiments of the accompanying drawings. Note that even if component 8 95260 8 201220410 is shown in the same drawing 'but the same component symbol indicates the same group m ' should know that the size of each saki in the drawing only shows the description • use 'and not the whole The actual size of the reaction assembly. Further, when it is determined that the detailed description of the known art of the present invention may obscure the object of the present invention, the detailed description thereof will be omitted. In the detailed description, the "5" capsules "--", "second", etc. are used to distinguish one component from another, and such components are not limited by the above terms. As used in the towel of the present invention, the term "component surface" means a surface on which a semiconductor component is mounted, and the term "welding surface" means a surface on which a solder ball is generally mounted for bonding with an external component. As used in the present invention, it is meant that "when the surface of the component is convexly curved, t refers to the fact that the substrate is relatively convex and curved according to its core layer perpendicular to the surface of the component and the surface of the soldering surface. This case, as used in the present invention, means "when the surface is concave toward the surface of the component" means that the substrate is relatively convex according to its core layer and is perpendicular to the surface of the component and the surface of the soldering surface perpendicular to the surface of the soldering surface. The situation. The warpage of the semiconductor package substrate is derived from the different coefficients of thermal expansion of the layers constituting the substrate and the temperature changes involved in the package production process. Therefore, in the present invention, the thickness of the surface of the component and the thickness of the soldering surface are adjusted in different ways to generate a direction in which the stress is opposite to the stress direction in which warpage is generated, and as a result, the heat opposite to each other can be offset. Stress, thereby improving the warpage of the substrate. Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
95260 201220410 半導體封裝基板 ， 第3和4圖為例示依照本發明之較佳實施例之半導體 - 封裝基板之示意剖面圖；第5和6圖為例示依照本發明之 - 第-個較佳實施例之半導體封裝基板之示意剖面圖。 依照本發明之較佳實施例之半導體封裝基板包含：基 底基板，具有形成在其一個表面上之組件表面和形成在其 另個表面上之焊接表面，該組件表面具有形成在其中之 電路®案且該組件表面之電路圖案包含用來安裝半導體之 隆起墊’而3亥焊接表面具有形成在其中之電路圖案且該焊 接表面之電路圖案包含用來與外部組件結合之焊接替丨形 成在該組件表面之隆起塾上之第一表面處理層；以及形成 在該焊接表面之焊接塾上之第二表面處理層 。此處，該第 -表面處理層㈣第二表面纽層具有不同的厚度。 基底基板可以是具有用於内層電路之金屬層之多層 基板。 第一表面處理層與第二魏層間之厚度差可以是3至 10 以 m。 較理想之情況是，第一表面處理層包含第一錄錄層和 第-鍵金層而第二表面處理層包含第二鍍鎳層和第二錄金 層’該第-纖層具有與第二賴層不同的厚度。 此外，半導體封農基板可進一步包含分別形成在基底 基板之二個表面之阻焊層，該阻焊層具有用來分別暴露隆 起墊和焊接墊之開口部分。 下文中’將參照第3和4圖說明依照本發明之較佳實 10 95260 201220410 施例之半導體封裝基板。 參照第3圖’半導體封裝基板100包含：基底基板， 具有於絕緣層1〇1之一個表面上之組件表面，在該組件表 面中开>成有電路圖案，電路圖案包含用來安裝半導體之隆 起墊102a，且基底基板具有於絕緣層1〇1之另一個表面上 之知接表面在5亥知接表面中形成有電路圖案，電路圖案 包含用來與外部組件結合之焊接墊102b;第一表面處理層 103a和l〇4a，形成在該組件表面之隆起墊上；以及 第二表面處理層1031)和1〇4b，形成在該焊接表面之焊接 墊102b上。此處，該第一表面處理層1〇知和乜層較該 第二表面處理層l〇3b和l〇4b為厚。 一較理想之情況是，第一表面處理層103a和i〇4a與第 :表面處理層娜和難間之差係3至而使得 可以抵鱗和補償基底基板之趣曲。 雖然為了方便朗起見於第3圖中僅放大顯示95260 201220410 Semiconductor package substrate, FIGS. 3 and 4 are schematic cross-sectional views illustrating a semiconductor-package substrate in accordance with a preferred embodiment of the present invention; FIGS. 5 and 6 are diagrams illustrating a first preferred embodiment in accordance with the present invention A schematic cross-sectional view of a semiconductor package substrate. A semiconductor package substrate according to a preferred embodiment of the present invention includes: a base substrate having a surface formed on one surface thereof and a soldering surface formed on the other surface thereof, the surface of the module having a circuit formed therein And the circuit pattern on the surface of the component includes a bump pad for mounting the semiconductor and the 3H solder surface has a circuit pattern formed therein and the circuit pattern of the solder surface includes a solder substitute for bonding with the external component. a first surface treatment layer on the surface of the raised surface; and a second surface treatment layer formed on the soldering surface of the soldering surface. Here, the first surface treatment layer (four) second surface layer has different thicknesses. The base substrate may be a multilayer substrate having a metal layer for the inner layer circuit. The difference in thickness between the first surface treatment layer and the second Wei layer may be 3 to 10 m. Preferably, the first surface treatment layer comprises a first recording layer and a first-bond gold layer and the second surface treatment layer comprises a second nickel-plated layer and a second gold-plated layer The two layers have different thicknesses. Further, the semiconductor sealing substrate may further comprise a solder resist layer respectively formed on both surfaces of the base substrate, the solder resist layer having opening portions for respectively exposing the bump pad and the solder pad. Hereinafter, a semiconductor package substrate according to a preferred embodiment of the present invention will be described with reference to FIGS. 3 and 4. Referring to FIG. 3, the semiconductor package substrate 100 includes a base substrate having a surface of a component on one surface of the insulating layer 1-1, which is formed in a circuit pattern, and the circuit pattern includes a semiconductor for mounting the semiconductor. a bump pad 102a, and the base substrate has a circuit pattern formed on the other surface of the insulating layer 1-1, and the circuit pattern includes a solder pad 102b for bonding with an external component; A surface treatment layer 103a and 104a are formed on the embossing pad on the surface of the component; and a second surface treatment layer 1031) and 1 〇 4b are formed on the bonding pad 102b of the bonding surface. Here, the first surface treatment layer 1 is thicker than the second surface treatment layers 10a and 3b. Preferably, the difference between the first surface treatment layers 103a and i〇4a and the surface treatment layer Na and the difficulty layer 3 is such that the scale and the compensation of the base substrate can be compensated. Although it is seen in the third figure for the sake of convenience, it is only enlarged.
屬層之多層基板。 、 的树脂絕緣材料可以使用為絕 基板可以是具有用於内層電路之金 緣層。樹脂絕緣材 95260 11 201220410 料可以包含熱©化樹脂’此種環氧樹脂，例如fr 4、雙馬 來酰亞胺三（BT)、味之素建立膜（ABF)、等等，其已知為習 知的樹脂基板材料；熱_脂，譬如聚酰亞胺，或者於上 述樹脂中注人了譬如玻璃纖維或無機填料之加強構件之樹 脂’例如，可以使用預浸’並亦可使用熱固化樹脂和/或光 固化樹脂、等等，但是不限於此等情況。 使用為用於電路板之場中電路之導電金屬之任何金 屬可以應用於電路®案而不受聞，—般而言，可以使用 銅。 可以藉由此技術已知之任何方法形成表面處理而不 受限制’舉例而言’藉由電錄金、浸鑛金、有機可焊性防 腐（0SP)或浸鍍錫、浸鍍銀、無電鎳和浸鍍金（ENIG)、直接 浸鍍金（DIG電鍍）、熱風焊料整平（HASL)等等。 依照本較佳實施例，第一表面處理層1〇3a和1〇4a包 含第一鍍鎳層103a和第一鍍金層i〇4a，而第二表面處理 層103b和104b包含第二鍍鎳層103b和第二鍍金層1〇4卜 此處，第一鍍鎳層103a較第二鍍鎳層103b為厚。 較理想之情況是’第一鍍鎳層l〇3a與第二鍍鎳層i〇3b 間之厚度差係3至10/ζιη，而使得可以抵銷和補償基底基 板之勉曲。 較理.想之情況是，第一鍍鎳層l〇3a具有厚度6至15 ’而第二鍍鎳層i〇3b具有厚度3至12/zm，由此使得 基底基板之輕曲將被抵銷和補償。 而且，半導體封裝基板可以進一步包含分別形成在基 12 95260 ⑧ 201220410 底基板之二個表面之阻焊層（未顯示）。阻焊層具有分別暴 露隆起墊102a和焊接墊l〇2b之開口部分。此處，如上迷 之表面處理層形成在由開口部分暴露之連接端子上，也就 是說，隆起墊102a和焊接墊i〇2b。 阻焊層作為保護最外層電路之保護層。阻焊層由電絕 緣材料形成，並且具有用來暴露最外層之連接端子之開口 为。阻知層可以由如此技術中已知的例如阻焊油墨、阻 4膜、雄·封劑等專組成，並且依照使用目的可以由譬如熱 固化樹脂或光敏樹脂之絕緣材料製成，但是特別不限於此。 依照上述說明，組件表面之第一表面處理層丨03a、 104a可以形成具有較焊接表面之第二表面處理層⑽匕和 l〇4b為大之厚度，_此，可㈣產生自基底基板論 至組件表©之凸出翹曲，由此防止最終半導體封裝基板 100之翹曲。 下文中，將參照第5和6圖說明依照本發明之第二個 較佳實施例之半導體封裝基板’但是將省略與第-個較佳 實施例者重疊之部分。 參照第5圖，半導體封裝基板包含：基底基板， 具有於絕緣層201之—個表面上之組件表面，在該組件表 面中形成有電路圖案，電路圖案包含絲安裝半導體之隆 起，202a’且基底基板具有於絕緣層皿之另”個表面上 2接表面’在該焊接表面中形成有電路圖案，電路圖案 =3用來與外部組件結合之焊接墊襲；形結該組表 面之㈣墊咖上之第―表面處理層獅和施；以及 95260 13 201220410 形成在該焊接表面之焊接墊202b上之第二表面處理層 203b和204b。此處，該第一表面處理層203a和204a層較 該第二表面處理層203b和204b具有較小之厚度。 較理想之情況是’第一表面處理層203a和204a與第 二表面處理層203b和204b間之差係3至10# m，而使得 可以抵銷和補償基底基板之勉曲。 雖然為了方便說明起見於第5圖中僅放大顯示了基底 基板之電路圖案中連接端子部分，但是熟悉此項技術者可 以完全了解到除了形成在組件表面上之隆起墊2〇2a作為 連接端子之其他電路圖案和除了形成在焊接表面上之焊接 塾202b作為連接知子之其他電路圖案外，尚可提供其他的 電路圖案。 而且’於本圖中僅僅顯示了作為基板之核心之絕緣層 201’但是當需要時基底基板可為具有用於内層電路之金屬 層之多層基板。 可以藉由此技術已知之任何方法形成表面處理而不 受限制，舉例而言，藉由電鑛金、浸鍍金、有機可焊性防 腐（osp)或浸鍍錫、浸鍍銀、無電鎳和浸鍍金（ENIG)、直接 浸鑛金（DIG電鍍）、熱風焊料整平（jjaSL)等等。 依照本較佳實施例，第一表面處理層2〇33和2〇4a包 含第一鍍鎳層203a和第一鑛金層.204a，而第二表面處理 層203b和204b包含第二鍍鎳層203b和第二鍍金層204b。 此處，第一鍍鎳層203a較第二鍍鎳層203b為厚。 較理想之情況是，第一鍍鎳層2〇3a與第二鍍鎳層203b 95260 ⑧ 201220410 間之厚度差係3至10 # m，而使得可以抵銷和補償基底基 板之麵曲。 較理想之情況是，第一鑛鎳層203a具有厚度3至12 //m’而第一鐘錄層203b具有厚度6.至15/^ηι，由此使得 基底基板之翹曲將被抵銷和補償。 而且，半導體封裝基板可以進一步包含分別形成在基 底基板之二個表面之阻焊層（未顯示阻焊層具有分別暴 露隆起墊202a和焊接摯202b之開口部分。此處，如上述 之表面處理層形成在由開口部分暴露之連接端子上，也就 是說，隆起墊202a和焊接墊202b。 依照上述說明，組件表面之第一表面處理層2〇3a、 2〇4a形成具有較焊接表面之第二表面處理層203b和204b 為小之厚度，而因此，可以抵銷產生自基底基板1〇〇a至組 件表面之凹入翹曲，由此防止最終半導體封裝基板200之 紐曲。 製造半導體封裝基板之方法 第7和8圖為例示依照本發明之第三個較佳實施例之 製造半導體封裝基板之方法之示意剖 面圖；而第9和10 圖為例示依照本發明之第四個較佳實施例之製造半導體封 裝基板之方法之示意剖面圖。 依照本發明之較佳實施例一種製造半導體封裝基板 之方法包含：設置基底基板，該基底基板具有形成在其一 個表面上之組件表面和形成在其另一個表面上之焊接表 面’該Μ件表面具有電路圖案形成在其中之電路圖案且該 15 95260 201220410 組件表面之電路圖案包含用來安裝半導體之隆起墊，而該 烊接表面具有形成在其中之電路圖案且該焊接表面之電^ 圖案包含用來與外部組件結合之焊接塾；以及在該組件表 面之隆起塾上和在該焊接表面之焊接墊上分別形成第一表 面處理層和第二表面處理層。該第—表面處理層與該第二 表面處理層具有不同的厚度。 較理想之情況是，該第一表面處理層和該第二表面處 理層之厚度差係3至l〇em。 較理想之情況是，形成該第一表面處理層和該第二表 面處理層包含：分別形成第一鍍鎳層和第二鍍鎳層於基底 基板之組件表面之隆起墊與焊接表面之焊接墊上，以及分 別形成第一鍍金層與第二鍍金層於該一鍍鎳層和該第二鍍 錄層上。 該第一鍍鎳層與第二鍍鎳層形成具有不同的厚度。 此外，依照本發明之一個較佳實施例之方法可進一步 包含於設置基底基板後於該基底基板之二個表面上分別形 成阻焊層，該阻焊層具有用來分別暴露該隆起塾和該焊接 墊之開口部分。 下文中，將參照第7和8圖說明依照本發明之第三個 較佳實施例之製造半導體封裝基板之方法。然而，將省略 與上述半導體封裝基板重疊之部分。 首先’參照第7圖’基底基板30〇a具有於絕緣層301 之一個表面上之組件表面’在該組件表面中形成有電路圖 案，電路圖案包含用來安裝半導體之隆起墊302a，且基底 16 95260 ⑧ 201220410 基板具有於絕緣層301之另一個表面上之焊接表面，在該 焊接表面中形成有電路圖案，電路圖案包含用來與外部組 件結合之焊接墊302b。 此處，於本較佳實施例中，參照第7圖之下部，一種 情況因為組件表面之基板翹曲量相較於焊接表面之基板翹 曲量相當地小，因此基底基板3〇〇a凸出地朝組件表面翹 曲。 然後，參照第8圖，為了抵銷會產生翹曲之應力，形 成在組件表面之隆起墊3〇2a上之第一表面處理層3〇3a、 304a被形成具有較形成在焊接表面之焊接墊3〇託上之第 二表面處理層303b、304b為大之厚度。結果，如第8圖之 下部所示，於相反方向產生可以抵銷產生於基底基板3〇〇a 中翹曲之翹曲，而因此防止最終半導體封裝基板3〇〇之翹 曲。 依照本較佳實施例，形成之第一表面處理層303a、 304a和第一表面處理層303b、304b包含：分別形成第一 鍍鎳層303a和第二鍍鎳層3〇3b於基底基板300a之組件表 面之隆起墊302a和焊接表面之焊接墊302b上；以及分別 形成第一鍍金層304a和第二鍍金層304b於第一鍍鎳層 303a和第二鍍鎳層303b上。該第一鍍鎳層303a形成具有 較該第二鍍鎳層303b較大之厚度。 此處’可於基底基板3〇〇a之組件表面之隆起塾302a 和焊接表面之焊接墊302b上分別形成第一鍍鎳層303a和 第二鍍鎳層303b，而使得對於此技術已知的一般抗鍍圖案 17 95260 201220410 形成於二表面，然後同時形成二個鍍鎳層303&和鍍鎳層 303b’或者當需要時使得二個錢錄層3〇3a和303b以一個 表面被整個遮罩和電鍍層形成在其他表面，然後再度，其 他表面被整個遮罩和電鑛層形成在一個表面之方式交替地 形成。 相似於此情況’可於第一鑛鎳層303a和第二鑛鎳層 303b上分別形成第一鍵金層304a和第二鑛金層304b，而 使得二個鍍鎳層3〇3a和303b同時形成或交替形成。 較理想之情況是，第一鍍鎳層3〇3a與第二鍍鎳層303b 間之厚度差係3至10# m，而使得可以抵銷和補償基底基 板300a之輕曲。 較理想之情況是，第一鍍鎳層303a具有6至15/zm 之厚度範圍，而第二鍍鎳層303b具有3至12em厚度範 圍’由此使得基底基板300a之翹曲能夠被抵銷和補償。 於製備基底基板300a後，雖然圖式中未顯示，但是 可以進一步執行形成阻焊層，該等阻焊層具有用來分別暴 露隆起墊和焊接墊3〇2b分別於基底基板300a之二個表面 之開口部分。 此處，如上述之表面處理層可以形成在透過開口部分 暴露之隆起墊302a和焊接墊302b上。 此處，可以藉由此技術已知之方法形成開口部分，譬 如一般的雷射直接切除（LDA)方法、光學微影術方法等等， 而不受特殊限制。 如上述參照第8圖說明，當基底基板3〇〇a朝向組件 18 95260 ⑧ 201220410 表面凸出翹曲時，形成組件表面之第一表面處理層3〇3a 和304a具有較組件表面之第二表面處理層如北和3〇4b 為大之厚度。結果’可以抵銷產生凸出朝向組件表面之麵 曲，由此防止最終半導體封裝基板3〇〇之翹曲。 下文中，將參照第9和1〇圖說明依照本發明之第四 個較佳實施例之製造半導體封裝基板之方法。然而，將省 略與上述半導體封裝基板重曼之部分。 首先，參照第9圖，基底基板4()0a具有於絕緣層4〇1 之-個表®上之崎表®，在該組件絲㈣财電路圖 案，電路圖案包含用來安裝半導體之隆起墊4〇2a，且基底 基板具有於絕緣層401之另一個表面上之焊接表面，在該 焊接表面中形成有電路㈣，電路圖案包含絲與外部挺 件結合之焊接墊4〇2b。 ’ 此處，於本較佳實施例中，參照第9圖之下部，一種 情況因為組件表面之基板收縮量相較於焊接表面之基板收 縮量相當地小，因此基底基板4〇〇八凹入地朝組件表面翹 曲。 然後，參照第10圖，為了抵銷會產生翹曲之應力， 形成在組件表面之隆起塾402a上之第-表面處理層4〇3a、 4〇4a被形成具有較形成在焊接表面之焊接墊402b上之第 二表面處理層娜、獅為小之厚度。結果，於相反方向 產生可以抵銷產生於基底基板撕中趣曲之勉曲，而因此 防止最終半導體封裝基板400之翹曲。 依照本較佳實施例，形成之第一表面處理層403a、 95260 19 201220410 404a和第二表面處理層403b、404b包含：分別形成第一 鍍鎳層403a和第二鍍鎳層403b於基底基板400a之組件表 面之隆起墊402a和焊接表面之焊接墊4〇2b上；以及分別 形成第一鍍金層404a和第二鍍金層4〇4b於第一鍍鎳層 403a和第二鍍鎳層403b上。該第一鍍鎳層4〇如形成具有 較該第二鍍鎳層403b較小之厚度。 此處，可於基底基板400a之組件表面之隆起墊4〇2a 和焊接表面之焊接墊402b上分別形成第一鍍鎳層403a和 第二鍍鎳層403b’而使得對於此技術已知的一般抗鍍圖案 形成於二表面，然後同時形成二個鍍鎳層4〇3&和鍍鎳層 403b，或者使得二個鍍鎳層403a和403b以一個表面被整 個遮罩和電鐘層形成在其他表面，然後再度，其他表面被 整個遮罩和電鏟層形成在一個表面之方式交替地形成。 相似於此情況，可於第一鍍鎳層403a和第二鍍鎳層 403b上分別形成第一鑛金層404a和第二鍍金層404b，而 使得二個鍍鎳層303a和303b同時形成或交替形成。 較理想之情況是，第一鑛鎳層403a與第二鍍鎳層403b 間之厚度差係3至10/zm，而使得可以抵銷和補償基底基 板之翹曲。 較理想之情況是，第一鍍鎳層403a具有3至12/zm 之厚度範圍’而第二鍍鎳層403b具有6至15# m厚度範 圍，由此使得基底基板300a之勉曲能夠被抵銷和補償。 於製備基底基板400a後，雖然圖式中未顯示，但是 可以進一步執行形成阻焊層，該等阻焊層具有用來分別暴 20 95260 ⑧ 201220410 露隆起塾402a和焊接墊402b分別於基底基板400a之二個 表面之開口部分。 此處，如上述之表面處理層可以形成在透過開口部分 暴露之隆起墊402a和焊接墊402b上。 此處’可以藉由此技術已知之方法形成開口部分，譬 如一般的雷射直接切除（LDA)方法、光學微影術方法等等， 而不受特殊限制。 如上述參照第圖說明，當基底基板400a朝向組件 表面凹入翹曲時’形成組件表面之第一表面處理層403a 和404a具有較組件表面之第二表面處理層4〇3b和4〇4b 為小之厚度。結果，可以抵銷產生凹入朝向組件表面之翹 曲’由此防止最終半導體封裝基板4〇〇之翹曲。 如上述說明’本發明藉由寬擴地改變組件表面和焊接 表面之表面處理層之厚度並且將他們構成不對稱方式，而 可以相應地應用於趨向薄厚度產品和一個射出模，同時具 有最大影響於基板之翹曲。 此外’依照本發明，可以從根本上改善面板基板之翹 曲、帶狀基板之翹曲、和單元基板之翹曲。 再者’依照本發明，可以在形成表面處理層之前藉由 以不對稱之方式構成表面處理層之厚度，而明顯減少基板 之翹曲量，使得可以抵銷產生於基底基板之翹曲。 又再者’本發明不需要額外的製程用來顯著地減少基 板之趣曲’即使該基板變薄’並且因此可以應用於各種產 品而無關面板、帶狀基板、和單元基板之大小。 21 95260 201220410 依照本發明，可以藉由改變表面處理層之厚度，而根 本上改善面板基板之魅曲。 涉及封裝製程之基板之溫度減少藉由於構成基板之數 層間之熱膨脹係數差而導致基板翹曲。於本發明中，凸出 翹曲表面之表面處理層之厚度形成大於凹入翹曲表面之表 面處理層之厚度，以不對稱方式調整其厚度。結果，產生 於基底基板之基板收縮量被產生於表面處理層之基板收縮 量抵銷，由此明顯減少基板之輕曲量。 此外，本發明不需要額外的製程用來顯著地減少基板 之翹曲，即使該基板變薄，並且因此可以應用於各種產品 而無關面板基板、帶狀基板、和單元基板之大小。 雖然已經揭了示本發明之較佳實施例用於說明目的， 該等實施例用來特定說明本發明而因此依照本發明之半導 體封裝基板和製造其之方法並錢於此，值是減此項技 術者將了解到，各種修改、添加、和替代是可能的，而不 會偏離揭示於所附申請專利範圍中之本發明之範 圍。 因此’應該了解到該等修改、添加、和替代亦將落於 本發明之範圍内。 【圖式簡單說明】 第1和2圖為例示依照先前技術之半導體封装基板之 示意剖面圖； 第3和4圖為例示依照本發明之較佳實施例之半導體 封裴基板之示意剖面圖； 95260 ⑧ 22 201220410 第5和6圖為例示依照本發明之第二個較佳實施例之 半導體封裝基板之示意剖面圖； 第7和8圖為例示依照本發明之第三個較佳實施例之 製造半導體封裝基板之方法之示意剖面圖； 第9和10圖為例示依照本發明之第四個較佳實施例 之製造半導體封裝基板之方法之示意剖面圖。 【主要元件符號說明】 10、100、200、300、400 半導體封裝基板 11 核心絕緣層 12a 第一銅層 12b 第二銅層 13a、103a、104a、203a、204a、303a、304a、403a、404a 第一表面處理層 13b、103b、104b、203b、204b、303b、304b、403b、404b 第二表面處理層 100a、300a、400a 基底基板 101、201、301、401 絕緣層 102a、202a、302a、402a 隆起墊 102b、202b、302b、402b 焊接墊 v,.. .· ·· 23 95260A multilayer substrate of a genus layer. The resin insulating material may be used as a substrate or may have a gold layer for an inner layer circuit. Resin insulating material 95260 11 201220410 The material may contain a thermal resin such as an epoxy resin such as fr 4 , bismaleimide tris(BT), ajinomoto-forming film (ABF), etc., which are known. It is a conventional resin substrate material; a thermal grease such as polyimide, or a resin in which a reinforcing member such as a glass fiber or an inorganic filler is added to the above resin, for example, prepreg can be used and heat can also be used. Curing resin and/or photocurable resin, and the like, but are not limited thereto. Any metal that is used as a conductive metal for the circuit in the field of the board can be applied to the circuit® without being smelled. In general, copper can be used. The surface treatment can be formed by any method known in the art without limitation 'for example' by electrocalyptus gold, gold immersion gold, organic solderability corrosion protection (0SP) or immersion tin plating, immersion silver plating, electroless nickel And immersion gold plating (ENIG), direct immersion gold plating (DIG plating), hot air solder leveling (HASL) and so on. According to the preferred embodiment, the first surface treatment layers 1〇3a and 1〇4a comprise a first nickel plating layer 103a and a first gold plating layer i〇4a, and the second surface treatment layers 103b and 104b comprise a second nickel plating layer. 103b and the second gold plating layer 1b, here, the first nickel plating layer 103a is thicker than the second nickel plating layer 103b. Preferably, the difference in thickness between the first nickel plating layer 10a and the second nickel plating layer i3b is 3 to 10/inch, so that the distortion of the base substrate can be offset and compensated. It is reasonable to think that the first nickel plating layer 10a has a thickness of 6 to 15' and the second nickel plating layer i3b has a thickness of 3 to 12/zm, thereby causing the base substrate to be lightly buckled. Sales and compensation. Moreover, the semiconductor package substrate may further comprise solder resist layers (not shown) formed on the two surfaces of the base substrate of the base 12 95260 8 201220410, respectively. The solder resist layer has openings for exposing the bump pads 102a and the solder pads l2b, respectively. Here, the surface treatment layer as described above is formed on the connection terminal exposed by the opening portion, that is, the bump pad 102a and the solder pad i〇2b. The solder mask acts as a protective layer for the outermost circuit. The solder resist layer is formed of an electrically insulating material and has openings for exposing the outermost connection terminals. The blocking layer may be composed of, for example, a solder resist ink, a resist film, a male sealant, etc., which are known in the art, and may be made of an insulating material such as a thermosetting resin or a photosensitive resin according to the purpose of use, but in particular, Limited to this. According to the above description, the first surface treatment layer 丨03a, 104a of the surface of the component may be formed to have a thickness greater than that of the second surface treatment layer (10) 〇 and 〇4b of the solder surface, which may be generated from the substrate substrate to The warpage of the component sheet © is warped, thereby preventing warpage of the final semiconductor package substrate 100. Hereinafter, a semiconductor package substrate ' in accordance with a second preferred embodiment of the present invention will be described with reference to Figs. 5 and 6, but portions overlapping with the first preferred embodiment will be omitted. Referring to FIG. 5, a semiconductor package substrate includes: a base substrate having a surface of a component on a surface of the insulating layer 201, a circuit pattern formed in the surface of the component, the circuit pattern including a ridge of the wire-mounted semiconductor, 202a' and a substrate The substrate has a second surface on the other surface of the insulating layer. A circuit pattern is formed in the soldering surface, and the circuit pattern=3 is used for bonding with the external component; and the surface of the group is formed. The first surface treatment layer lion and the application; and 95260 13 201220410 form the second surface treatment layers 203b and 204b on the soldering pad 202b of the soldering surface. Here, the first surface treatment layer 203a and 204a layer The second surface treatment layers 203b and 204b have a small thickness. It is desirable that the difference between the first surface treatment layers 203a and 204a and the second surface treatment layers 203b and 204b is 3 to 10#m, so that Offset and compensate for the distortion of the base substrate. Although only the connection terminal portion in the circuit pattern of the base substrate is shown enlarged in FIG. 5 for convenience of explanation, those skilled in the art Other circuit patterns can be provided in addition to other circuit patterns in addition to the bump pads 2 2a formed on the surface of the module as the connection terminals and other solder patterns 202b formed on the solder surface as the connection circuit. Moreover, 'only the insulating layer 201' which is the core of the substrate is shown in the figure, but the base substrate may be a multilayer substrate having a metal layer for the inner layer circuit when necessary. Surface treatment may be formed by any method known in the art. Without limitation, for example, by electrowinning gold, dip gold plating, organic solderability anticorrosion (osp) or immersion tin plating, immersion silver plating, electroless nickel and immersion gold plating (ENIG), direct leaching gold (DIG) Electroplating), hot air solder leveling (jjaSL), etc. According to the preferred embodiment, the first surface treatment layers 2〇33 and 2〇4a comprise a first nickel plating layer 203a and a first gold layer. 204a, and The two surface treatment layers 203b and 204b include a second nickel plating layer 203b and a second gold plating layer 204b. Here, the first nickel plating layer 203a is thicker than the second nickel plating layer 203b. Preferably, the first nickel plating layer is Layer 2〇3a The difference in thickness between the second nickel plating layer 203b 95260 8 201220410 is 3 to 10 #m, so that the curvature of the base substrate can be offset and compensated. Preferably, the first mineral nickel layer 203a has a thickness of 3 to 12 //m' and the first clock recording layer 203b has a thickness of 6. to 15/m, whereby the warpage of the base substrate is offset and compensated. Further, the semiconductor package substrate may further comprise a base substrate, respectively. a solder resist layer of two surfaces (the solder resist layer is not shown to have an opening portion exposing the bump pad 202a and the solder bump 202b, respectively. Here, the surface treatment layer as described above is formed on the connection terminal exposed by the opening portion, that is, , the bump pad 202a and the solder pad 202b. According to the above description, the first surface treatment layers 2〇3a, 2〇4a of the surface of the component are formed to have a smaller thickness than the second surface treatment layers 203b and 204b of the soldered surface, and thus, can be offset from the base substrate 1〇 The 〇a is concavely warped to the surface of the component, thereby preventing the ridge of the final semiconductor package substrate 200. 7 and 8 are schematic cross-sectional views illustrating a method of fabricating a semiconductor package substrate in accordance with a third preferred embodiment of the present invention; and FIGS. 9 and 10 illustrate a fourth embodiment in accordance with the present invention A schematic cross-sectional view of a preferred embodiment of a method of fabricating a semiconductor package substrate. A method of manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention includes: providing a base substrate having a surface of a component formed on one surface thereof and a soldering surface formed on the other surface thereof a circuit pattern having a circuit pattern formed therein and the circuit pattern of the surface of the 15 95260 201220410 component includes a bump for mounting a semiconductor, and the splicing surface has a circuit pattern formed therein and the electrical pattern of the solder surface is included And a second surface treatment layer formed on the ridges of the surface of the assembly and on the solder pads of the solder surface, respectively. The first surface treatment layer and the second surface treatment layer have different thicknesses. Preferably, the difference in thickness between the first surface treatment layer and the second surface treatment layer is 3 to l〇em. Preferably, the forming the first surface treatment layer and the second surface treatment layer comprises: forming a first nickel plating layer and a second nickel plating layer on the solder pads of the bump pads and the soldering surfaces of the component surface of the base substrate, respectively. And forming a first gold plating layer and a second gold plating layer on the one nickel plating layer and the second plating layer, respectively. The first nickel plating layer and the second nickel plating layer are formed to have different thicknesses. In addition, the method according to a preferred embodiment of the present invention may further include forming a solder resist layer on each of the two surfaces of the base substrate after the base substrate is disposed, the solder resist layer having a protrusion for respectively exposing the bump and the The opening portion of the solder pad. Hereinafter, a method of manufacturing a semiconductor package substrate in accordance with a third preferred embodiment of the present invention will be described with reference to Figs. However, the portion overlapping the above-described semiconductor package substrate will be omitted. First, referring to FIG. 7, the base substrate 30A has a component surface on one surface of the insulating layer 301, in which a circuit pattern is formed, the circuit pattern includes a bump 302a for mounting a semiconductor, and the substrate 16 95260 8 201220410 The substrate has a soldering surface on the other surface of the insulating layer 301, in which a circuit pattern is formed, the circuit pattern including solder pads 302b for bonding with external components. Here, in the preferred embodiment, referring to the lower portion of FIG. 7, in one case, since the substrate warpage amount of the component surface is considerably smaller than the substrate warpage amount of the soldering surface, the base substrate 3〇〇a is convex. The ground is warped toward the surface of the component. Then, referring to Fig. 8, in order to offset the stress which causes warpage, the first surface treatment layer 3〇3a, 304a formed on the embossment pad 3〇2a of the surface of the component is formed to have a solder pad which is formed on the soldering surface. The second surface treatment layers 303b, 304b on the third support are of a large thickness. As a result, as shown in the lower portion of Fig. 8, the warpage in the opposite direction which can be generated in the warpage of the base substrate 3a is canceled, and thus the warpage of the final semiconductor package substrate 3 is prevented. According to the preferred embodiment, the first surface treatment layers 303a, 304a and the first surface treatment layers 303b, 304b are formed by: forming a first nickel plating layer 303a and a second nickel plating layer 3〇3b on the base substrate 300a, respectively. A bump pad 302a on the surface of the component and a solder pad 302b on the solder surface; and a first gold plating layer 304a and a second gold plating layer 304b are formed on the first nickel plating layer 303a and the second nickel plating layer 303b, respectively. The first nickel plating layer 303a is formed to have a larger thickness than the second nickel plating layer 303b. Here, a first nickel plating layer 303a and a second nickel plating layer 303b may be formed on the ridges 302a of the surface of the component of the base substrate 3A and the solder pads 302b of the soldering surface, respectively, so as to be known to the art. The general plating resist pattern 17 95260 201220410 is formed on the two surfaces, and then two nickel plating layers 303 & and the nickel plating layer 303b' are simultaneously formed or the two recording layers 3〇3a and 303b are completely masked on one surface when necessary. The plating layer is formed on the other surface, and then the other surfaces are alternately formed in such a manner that the entire mask and the electric ore layer are formed on one surface. Similar to this case, a first bond gold layer 304a and a second gold layer 304b may be formed on the first mineral nickel layer 303a and the second mineral nickel layer 303b, respectively, so that the two nickel plating layers 3〇3a and 303b are simultaneously Formed or alternated. Preferably, the difference in thickness between the first nickel plating layer 3?3a and the second nickel plating layer 303b is 3 to 10#m, so that the light curvature of the base substrate 300a can be offset and compensated. Preferably, the first nickel plating layer 303a has a thickness range of 6 to 15/zm, and the second nickel plating layer 303b has a thickness range of 3 to 12 em' thereby causing the warpage of the base substrate 300a to be offset and make up. After the base substrate 300a is prepared, although not shown in the drawings, it is further possible to form a solder resist layer having a surface for respectively exposing the bump pad and the solder pad 3〇2b on the two surfaces of the base substrate 300a. The opening part. Here, the surface treatment layer as described above may be formed on the bump pad 302a and the solder pad 302b exposed through the opening portion. Here, the opening portion can be formed by a method known from the art, such as a general laser direct resection (LDA) method, an optical lithography method, or the like, without being particularly limited. As described above with reference to FIG. 8, when the base substrate 3〇〇a protrudes toward the surface of the assembly 18 95260 8 201220410, the first surface treatment layers 3〇3a and 304a forming the surface of the assembly have a second surface which is larger than the surface of the assembly. The treatment layers such as north and 3〇4b are large thicknesses. As a result, it is possible to offset the curvature which is convex toward the surface of the component, thereby preventing the warpage of the final semiconductor package substrate 3. Hereinafter, a method of manufacturing a semiconductor package substrate in accordance with a fourth preferred embodiment of the present invention will be described with reference to FIGS. 9 and 1 . However, it will be omitted from the above-mentioned semiconductor package substrate. First, referring to Fig. 9, the base substrate 4()0a has an on-surface sheet® on the surface of the insulating layer 4〇1, in which the circuit pattern includes a bump for mounting a semiconductor. 4〇2a, and the base substrate has a soldering surface on the other surface of the insulating layer 401, and a circuit (4) is formed in the soldering surface, and the circuit pattern includes solder pads 4〇2b in which the wires are combined with the external soldering members. Here, in the preferred embodiment, referring to the lower portion of Fig. 9, in one case, since the amount of substrate shrinkage of the surface of the component is considerably smaller than the amount of substrate shrinkage of the soldering surface, the base substrate 4 is recessed. The ground warps toward the surface of the component. Then, referring to Fig. 10, in order to offset the stress which causes warpage, the first surface treatment layers 4?3a, 4?4a formed on the ridges 402a of the surface of the module are formed to have solder pads which are formed on the soldering surface. The second surface treatment layer on the 402b is a small thickness of the lion and the lion. As a result, the distortion in the opposite direction can be offset by the tearing of the base substrate, and thus the warpage of the final semiconductor package substrate 400 is prevented. According to the preferred embodiment, the first surface treatment layer 403a, 95260 19 201220410 404a and the second surface treatment layer 403b, 404b are formed to: form a first nickel plating layer 403a and a second nickel plating layer 403b on the base substrate 400a, respectively. The bump pad 402a of the component surface and the solder pad 4〇2b of the soldering surface; and the first gold plating layer 404a and the second gold plating layer 4〇4b are formed on the first nickel plating layer 403a and the second nickel plating layer 403b, respectively. The first nickel plating layer 4 is formed to have a smaller thickness than the second nickel plating layer 403b. Here, the first nickel plating layer 403a and the second nickel plating layer 403b' may be formed on the bump pads 4〇2a of the component surface of the base substrate 400a and the solder pads 402b of the soldering surface, respectively, so as to be generally known to the art. The plating resist pattern is formed on the two surfaces, and then two nickel plating layers 4〇3& and the nickel plating layer 403b are simultaneously formed, or the two nickel plating layers 403a and 403b are formed on the entire surface by the entire mask and the electric clock layer. The surface, and then again, the other surfaces are alternately formed by the formation of the entire mask and the shovel layer on one surface. Similarly, the first gold layer 404a and the second gold plating layer 404b may be formed on the first nickel plating layer 403a and the second nickel plating layer 403b, respectively, so that the two nickel plating layers 303a and 303b are simultaneously formed or alternated. form. Preferably, the difference in thickness between the first ore nickel layer 403a and the second nickel plating layer 403b is 3 to 10/zm, so that the warpage of the base substrate can be offset and compensated. Preferably, the first nickel plating layer 403a has a thickness range of 3 to 12/zm' and the second nickel plating layer 403b has a thickness range of 6 to 15#m, whereby the distortion of the base substrate 300a can be offset Sales and compensation. After the base substrate 400a is prepared, although not shown in the drawings, a solder resist layer may be further formed, and the solder resist layers are used to respectively swell 20 95260 8 201220410 swell ridges 402a and solder pads 402b respectively on the base substrate 400a The opening portion of the two surfaces. Here, the surface treatment layer as described above may be formed on the bump pad 402a and the solder pad 402b exposed through the opening portion. Here, the opening portion can be formed by a method known from the art, such as a general laser direct resection (LDA) method, an optical lithography method, or the like, without being particularly limited. As described above with reference to the drawings, when the base substrate 400a is warped toward the surface of the component, the first surface treatment layers 403a and 404a forming the surface of the component have the second surface treatment layers 4〇3b and 4〇4b which are larger than the surface of the component. Small thickness. As a result, it is possible to offset the occurrence of warpage of the concave toward the surface of the component, thereby preventing warpage of the final semiconductor package substrate 4. As described above, the present invention can be applied to a thin-thickness product and an injection mold with a maximum influence by broadly changing the thickness of the surface treatment layer of the component surface and the soldering surface and forming them in an asymmetrical manner. Warpage on the substrate. Further, according to the present invention, warpage of the panel substrate, warpage of the strip substrate, and warpage of the unit substrate can be fundamentally improved. Further, according to the present invention, the thickness of the surface treatment layer can be formed asymmetrically before the formation of the surface treatment layer, and the amount of warpage of the substrate can be remarkably reduced, so that the warpage generated on the base substrate can be offset. Still further, the present invention does not require an additional process for significantly reducing the fun of the substrate 'even if the substrate is thinned' and thus can be applied to various products regardless of the size of the panel, the strip substrate, and the unit substrate. 21 95260 201220410 According to the present invention, the glamour of the panel substrate can be substantially improved by changing the thickness of the surface treatment layer. The temperature reduction of the substrate involved in the packaging process causes the substrate to warp due to the difference in thermal expansion coefficient between the layers constituting the substrate. In the present invention, the thickness of the surface treatment layer which protrudes from the warped surface is formed to be larger than the thickness of the surface treatment layer of the concave warpage surface, and the thickness thereof is adjusted in an asymmetric manner. As a result, the amount of substrate shrinkage generated on the base substrate is offset by the amount of substrate shrinkage generated in the surface treatment layer, thereby significantly reducing the amount of lightness of the substrate. Furthermore, the present invention does not require an additional process for significantly reducing the warpage of the substrate even if the substrate is thinned, and thus can be applied to various products irrespective of the size of the panel substrate, the strip substrate, and the unit substrate. Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, the embodiments are intended to specifically illustrate the present invention and thus the semiconductor package substrate and method of manufacturing the same according to the present invention, and the value is reduced. A person skilled in the art will recognize that various modifications, additions, and substitutions are possible without departing from the scope of the invention as disclosed in the appended claims. Therefore, it should be understood that such modifications, additions, and substitutions are also within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are schematic cross-sectional views illustrating a semiconductor package substrate according to the prior art; FIGS. 3 and 4 are schematic cross-sectional views illustrating a semiconductor package substrate in accordance with a preferred embodiment of the present invention; 95260 8 22 201220410 FIGS. 5 and 6 are schematic cross-sectional views illustrating a semiconductor package substrate in accordance with a second preferred embodiment of the present invention; FIGS. 7 and 8 are diagrams illustrating a third preferred embodiment in accordance with the present invention A schematic cross-sectional view of a method of fabricating a semiconductor package substrate; FIGS. 9 and 10 are schematic cross-sectional views illustrating a method of fabricating a semiconductor package substrate in accordance with a fourth preferred embodiment of the present invention. [Major component symbol description] 10, 100, 200, 300, 400 semiconductor package substrate 11 core insulating layer 12a first copper layer 12b second copper layer 13a, 103a, 104a, 203a, 204a, 303a, 304a, 403a, 404a a surface treatment layer 13b, 103b, 104b, 203b, 204b, 303b, 304b, 403b, 404b second surface treatment layer 100a, 300a, 400a base substrate 101, 201, 301, 401 insulation layer 102a, 202a, 302a, 402a Pads 102b, 202b, 302b, 402b solder pads v, .. . . . . 23 95260