201216444 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種三維堆疊晶粒封裝結 造方法；特另是有關於-種二維堆#晶粒封的曰 圓級製造方法。 m構的曰曰 【先前技術】 由於電子產品輕、薄、短、小的需求，以及積體 路之線寬不斷縮小的情況下，為了達到上述 ， 積體電路(3IMC)堆疊構裝孕育而生。 電j 過石夕片貫通孔技術(Tr〇ugh_Sllic〇n-Vias，TSVs)= = 内形成垂直式貫通孔，並將絕緣材料及 料= 該等貫通孔内，以於矽晶片內來㈣古―蜀：抖/尤積於 構，再將石夕晶月予以堆疊。此種封裝結^ 連接結 =短’可避免因線寬不斷縮小所：生物生問=連： 可^傳輸速度’適合應料高速度運算元件或記憶體 =者，該封裝結構朝垂直方向進行晶片堆疊，可 維積體電路堆疊封装已成為未來重要的Πί構: 【發明内容】 方法本ίΓιΪ供一種三維堆疊晶粒封裝結構及其製造 :'、| 矽片貫通孔（Through-Silicon-Vias，TSVs) 电τ生傳輸路徑，進而增加電性傳輸速率。 方味^明提供―種三維堆疊晶粒封裝結構及其製造 穿孔之門舌i本發明結構中塾片上盲孔(via_〇n-_與貫 穿孔之間重佈線(Redis她ution Layer，RDL)的設計，以 201216444 疊仏構的電性從它的第-表面導 方法m 封裝結構及其製造 片，以防止該等墊片二;覆間彼此接合的塾 裝結構的可靠度。進而“心維堆疊晶粒封 方、三維堆疊晶粒封裝結構及其製造 結構的圖案層直接做為製作晶粒上導線 此外，本發明—實施範例提供—種具垂直電性 之晶粒結構’係利用晶粒上盲孔與貫穿孔之間重佈線 設計:以將該晶粒的電性從其―第〜表面導引至相對的 一第二表面。 本發明一實施範例提供一種三維堆疊晶粒封裝結 構，其至少包括一第一基板、一第二基板及至少一第一 導電凸塊’其中該第一基板係包含：至少一晶粒、至少 一第一導電性墊片、至少一貫通孔及至少一盲孔，其中 該第一導電性墊片形成於該第一基板的一第一表面 上，该貫通孔係貫穿該第一導電性墊片及該第一基板， 及該盲孔係形成於該第一導電性墊片上方；一絕緣層係 形成於該貝通孔及盲孔周壁以及該第一基板之該第一 表面及相對的一第二表面上；一電性連接層，係形成於 §玄絕緣層上並填塞该貫通孔及盲孔，以將該第一基板的 電性從其第一表面導引至第二表面。該第二基板結構相 同於s玄第一基板結構，5亥第二基板之第一表面堆疊於該 第一基板之該第二表面下方，並且彼此對應的該等電性 連接層互相接合。該至少一第一導電凸塊包覆該第一基 板及第 '一基板彼此接合的該等電性連接層。 5 201216444 本發明一實施範例提供一種三維堆疊晶粒封裝結 構製造方法，其包括以下步驟：提供一基板，該基板具 有至少一晶粒及至少一第一導電性墊片於其一第一表 面上；形成至少一第一貫通孔貫穿該第一導電性墊片及 該基板；形成一絕緣層覆蓋該基板的第一表面及其相對 的一第二表面並且填塞該第一貫通孔；形成至少一第二 貫通孔貫穿對應的該第一貫通孔内的該絕緣層及至少 一盲孔於對應的一該第一導電性墊片上方；形成一導電 性層填塞該第二貫通孔及該盲孔以及覆蓋該基板的該 第一表面及第二表面上，以將該基板的電性從該第一表 面導引至該第二表面；分別形成一導電性硬質罩幕層於 該基板之該第一表面及第二表面之該導電性層上；蝕刻 該等導電性硬質罩幕層，以分別形成一導線圖案罩幕於 該基板之該第一表面及該第二表面上方；蝕刻該基板之 該第一表面及第二表面之該導電性層，以分別形成一導 線圖案層於該基板之該第一表面及第二表面上；及將至 少兩個前述基板以背面朝正面方式堆疊接合，使彼此對 應的該等導線圖案層互相接合後，該等導電性硬質罩幕 層係包覆彼此接合的該等導電性層。 本發明一實施範例提供一種具垂直電性導通之晶 粒結構，其包括一晶粒、一絕緣層、一電性連接層及至 少一導電性硬質罩幕圖案層。該晶粒係具有至少一導電 性墊片、至少一貫通孔及至少一盲孔，其中該導電性墊 片形成於該晶粒的一第一表面上，該貫通孔係貫穿該導 電性墊片及該晶粒，及該盲孔係形成於該導電性墊片上 方。該絕緣層係形成於該貫通孔及盲孔周壁以及該晶粒 之該第一表面及其相對的一第二表面上。該電性連接層 係形成於該絕緣層上並填塞該貫通孔及盲孔，以將該晶 6 .201216444 粒的電性從其第一表面導引至第二表面。該等導電性硬 質罩幕圖案層係個別形成於該晶粒第—表面及第二表 面之該電性連接層上。 一 【實施方式】 本發明提供一種三維堆疊晶粒封裝結構及其製造 方法，尤指一種以晶圓級製程製造而得的三維堆疊晶粒 封裝結構，係藉由以下具體實施例配合所附圖式予以詳 細明如下。 第一 Α圖至第一 Κ圖係本發明三維堆疊晶粒封裝結 構製造方法之第一具體實施例，分別說明對應各製程階 段的結構截面示意圖。參第一 A圖，首先提供一基板 100 ’该基板100具有至少一晶粒（未示出）及至少一第一 導電性塾片101於其一第一表面上l〇〇a。該基板丨〇〇可 以是一具有複數個積體電路元件及複數個金屬墊片，例 如’ Ni/Au合金墊片於其表面上的矽晶圓。該基板1〇〇 也可以是III-V族晶圓或玻璃晶圓等。參第一 b圖，執 行矽片貫通孔(TSVs)技術，以形成至少一第一貫通孔 102貫穿該第一導電性墊片1〇1及該基板ι〇〇，例如可 以雷射鑽孔(laser drilling)、乾蝕刻（dry etching)或濕式蝕 刻（wet etching)方式形成該第一貫通孔1〇2。參第一 c 圖’形成一絕緣層103覆蓋該基板1〇〇的第一表面100a 及相對的一第二表面100b並且填塞該第一貫通孔1〇2。 該絕緣層103可以是一高分子絕緣材料層，例如， ABF(Ajinomoto Build-up Film)絕緣膜，而可以雙面壓合 方式形成於該基板100的第一表面l〇〇a及第二表面 100b上並填塞該第一貫通孔102。參第一 D圖，形成至 少一第二貫通孔104貫穿對應的該第一貫通孔1〇2内的 201216444 該絕緣層103及至少一盲孔(Via-〇n-Pad)105於對應的一 該第一導電性墊片1〇1上方。在第一具體實施例中，本 發明可以雷射鑽孔方式形成該第二貫通孔104及該盲孔 105。參第一 E圖，接著形成一第一導電性層1〇6於該 第二貫通孔104周壁及該盲孔1〇5中並覆蓋該基板1〇〇 上方該絕緣層上表面l〇3a及該基板1〇〇下方該絕緣層下 表面103b。在第一具體實施例中’由於該盲孔1〇5具有 較小内徑’所以該第一導電性層1〇6係可填滿該該盲孔 105。β玄第一導電性層1〇6係做為一種子層（seed layer) 以利於後續電錄金屬層之製作。該第一導電性層1〇6可 以是以濺鍍方法沈積形成的一鎢化鈦(Tiw)層。參第一 F 圖，接著以電鍍或無電鍍方式沈積形成一第二導電性層 107。例如，銅金屬層於該第一導電性層1〇6上並填塞 該第二貫通孔104，如此一來，即可將該基板1〇〇的電 性從第一表面l〇〇a導引至第二表面100be在第一具體 實施例中，當該盲孔105未被該第一導電性層1〇6所填 滿時，在後續第二導電性層107的製程步驟中，則可由 該第二導電性層1〇7填滿該盲孔ι〇5(圖未示出）。復參第 一 D圖，在第一具體實施例中，本發明亦可以直接以沈 積方式形成一電性連接層填塞該第二貫通孔1〇4及該盲 孔105並覆蓋該基板1〇〇上方該絕緣層上表面1〇3a及該 基板100下方該絕緣層下表面l〇3b，進而將該基板100 的電性從第一表面100a導引至第二表面i〇0b。 復參第一 F圖’接著分別形成一具預定厚度的第三 導電性層108於該基板1〇〇之第一表面100a及第二表面 100b上方之該第二導電性層1〇7上。該第三導電性層 108可以是一以電鑛方式沈積形成的一錫焊料層（s〇lder layer)。該第三導電性層1〇8的電鍍厚度係預先計算好， 8 201216444 以使其最低厚度在後續晶粒堆疊接合回銲(refl〇w)後，該 第三導電性層108可完整包覆堆疊晶粒間彼此接合的墊 片，以防止該等墊片的斷裂。 參第一 G圖，該第三導電性層ι〇8係可供做後續在 該基板100的第一表面l〇〇a及第二表面1〇〇1)上方分別 製作一導線圖案（重佈線圖案）的一導電性硬質罩幕層。 在此製程階段，係以雷射蝕刻方式圖案蝕刻該第三導電 性層108，以在該基板1〇〇的第一表面1〇〇a及第二表面 l〇〇b上方的該第二導電性層1〇7上分別形成一導線圖案 罩幕，以利於後續在該基板10〇的第一表面1〇〇a及第二 表面100b上方分別製作該導線圖案。 參第一 Η圖，以化學或物理姓刻方式，例如，乾姓 刻或濕式钮刻方式钮刻該第二導電性層1〇7。參第一 I 圖，接著以化學或物理蝕刻方式，例如，乾蝕刻或濕式 餘刻方式蝕刻該第一導電性層丨〇6，以在該基板1〇〇的 第一表面100a及第二表面100b上方分別形成前述導線 圖案。該導線圖案包含該第一導電性層106、該第二導 電性層107及該第三導電性層1〇8。 在第一具體實施例中，本發明係透過該第二貫通孔 104與該第一導電性墊片101上方該盲孔1〇5之間的前 述導線圖案做為重佈線，以將該基板100的電性從第一 ，面100a導引至第二表面100b。再者，前述導線圖案 =作係使用該第三導電性層108做為硬質罩幕層，而無 需使用黃光製程，進而可降低本發明的製程成本。 此外，在第一具體實施例中，如前述可以沈積方式 直接形成一電性連接導層填塞該第二貫通孔104及該盲 孔105並覆蓋該基板100上方該絕緣層上表面1〇3&及該 '、邑緣層下表面l〇3b。接著，再形成一具預定厚度的圖案 201216444 化導電性硬質罩幕層於該該絕緣層上表面i〇3a及該絕 緣層下表面103b的該導電性層上。在此情況下 ，可於 後續導線圖案製作階段以一次蝕刻方式 導電性 層，形成該導線圖案。 參第一 J圖，接著進行晶粒堆疊步驟，係將完成上 述製程步驟的至少兩個前述基板1〇〇以背面朝正面方式 堆疊接合，使彼此對應的該等導線圖案層互相接合，並 進行回銲(reflow)步驟，使對應接合的該等第三導電性層 108熔融而完整包覆對應接合的該第—導電性層1〇6及 該第二導電性層1G7。在此情況下，經圖案化的該第一 導電性層106及该第一導電性層107即構成一雪性連捲 層於該基板丨〇〇的該第.一表面100a及該第\表面100b 的忒絕緣層1 〇3上。在第一具體實施例中，該等接合的 第三導電性層108經回銲後可完整包覆上、基板1〇〇 對接的該等電性連接層，並使該等電性連接層透過該第 三導電性層108互相接合，如第一 j圖所示。或者，如 第二圖所示之上、下基板100對接的該等電連接層 該等第二導電性層107,直接接觸，而該第三導電性層 108完整包覆該等電性連接層。上述製程步驟即實現本 發明三維堆疊晶粒封裝結構的晶圓級製造方法。 參第一 K圖，接著進行堆疊晶粒切割步驟，即切割 前述基板堆疊結構，以將個別堆疊晶粒從前述基板堆疊 結構中分離出來。接下來，將分離出來的個別堆疊晶粒 黏著於一電路基板110上，使前述個別堆疊晶粒下方的 基板100的第二表面100b下方的該導線圖案對應接合 該電路基板110上的至少一個第二導電性墊片進 行回銲步驟，使熔融的該第三導電性層1〇8完整包覆下 方基板100第二表面100b下方該電性連接層及對接的 201216444 該電性塾片112。其中，該電路基板110可以日 一印刷電路基板，或其材質可以切或 了二疋 接層及晶粒與該電 電性層108完整包覆，故可防止該等Ξ =連接層及該第二導電性墊片112的斷 ： 該三維堆疊晶粒的封裝結構的可靠度。退』敕问 參將ΐΐ、— L圖，在第—具體實施例中，本發明亦可以 ϊ Ιίΐΐί 製程步驟而具有垂直電性導通的 曰曰拉從该基板100上切割分離出來，接著再以背面 面方式堆疊晶粒，堆疊方式同上述，之後再以如上= 式組裝於該電路基板110上方。如此一來，仍可得= 同的三維堆疊晶粒的封裝結構。 第二Α圖至第二Κ圖係本發明三維堆疊晶粒封裝 結構製造方法第二具體實施例對應各製程階段的結^ 截面示意圖。參第二A圖，首先提供一基板2〇〇，該基 板200具有至少一晶粒（未示出）及至少一第一導電性塾 片201於其一第一表面200a上。該基板200可以是一具 有複數個積體電路元件及複數個金屬墊片，例如，Ni/A= 合金墊片於其表面上的矽晶圓。該基板200也可以是 III-V族晶圓或玻璃晶圓等。參第二b圖，執行碎片貫 通孔(TSVs)技術，以形成至少一第一貫通孔202貫穿該 第一導電性墊片201及該基板200，例如可以雷射鑽孔 (laser drilling)、乾钮刻或濕式钱刻方式形成該第一貫通 孔202。參第二C圖，以沈積方式形成一絕緣層203於 該第一貫通孔202周壁並覆蓋該基板200的第一表面 11 201216444 200a與其相對的一第二表面2〇〇b。該絕緣層2〇3可以是 二氧化矽或氮化矽絕層。當該基板2〇〇為一矽晶圓時， 則可直接以熱氧化方法形成一二氧化矽層於該第一貫 通孔202周壁並覆蓋該基板200的第一表面200a與第二 表面200b。 參第二D圖，以雷射鑽孔技術形成至少一盲孔2〇4 於對應的一該第一導電性墊片2〇1上方。參第二E圖， 接著形成一第一導電性層205於該第一貫通孔202内周 壁的該絕緣層203上及該基板200上方該絕緣層上表面 2〇3a及該基板2〇〇下方該絕緣層下表面203b以及該盲 孔204中。由於該盲孔2〇4具有較小内徑，所以該第一 導電性層205可填滿該盲孔204。該第一導電性層205 係做為一種子層（seed iayer)以利於後續電鍍金屬層之製 作。該第一導電性層205可以是以濺鍍方法沈積形成的 一鎢化鈦(TiW)層。 參第二F圖，接著以電鍍或無電鍍方式沈積形成一 第二導電性層206，例如，銅金屬層於該第一導電性層 205上並填塞該第一貫通孔2〇2及覆蓋該盲孔2〇4上 方、該絕緣層上表面203a上方及該絕緣層下表面203b 下方該第一導電性層205。如此一來，即可將該基板200 的電性從第一表面200a導引至第二表面200b。在第二 具體實施例中，當該盲孔204未被該第一導電性層205 所填滿時’在後續第二導電性層206的製程步驟中，則 可由該第二導電性層206填滿該盲孔204(圖未示出）。 復參第二D圖，在第二具體實施例中，本發明亦可 以直接以沈積方式形成一電性連接層填塞該第一貫通 孔202及該盲孔204内部並覆蓋該基板200上方該絕緣 層上表面203a及該基板下方該絕緣層下表面203b，進 12 201216444 而將該基板200的電性從第一表面2〇〇a導引至第二表面 200b。復參第二F圖’接著分別形成一具預定厚度的第 三導電性層207於該絕緣層上表面2 〇 3 a上方及該絕緣層 下表面203b下方的該第二導電性層206上。該第三導 電性層207可以是一以電鍍方式沈積形成的一錫焊料層 (solder layer)。該第三導電性層2〇7的電鍍厚度係預先 計算好，以使其最低厚度在後續晶粒堆疊接合回銲 (reflow)後’該第三導電性層207可完整包覆堆疊晶粒間 彼此接合的墊片，以防止該等墊片的斷裂。 參第二G圖，該第三導電性層207係可供做後續在 該絕緣層上表面203a上方及該絕緣層下表面203b下方 分別製作一導線圖案（重佈線圖案）的一導電性硬質罩幕 層。在此製程階段，係以雷射蝕刻方式圖案蝕刻該第三 導電性層207,以在該絕緣層上表面203a上方及該絕緣 層下表面203b下方的該第二導電性層206上分別形成 一導線圖案罩幕’以利於後續在該絕緣層上表面203a 上方及該絕緣層下表面203b下方分別製作該導線圖 案。參第二Η圖，以化學蝕刻方式例如乾蝕刻或濕式蝕 刻方式蝕刻該第二導電性層206。參第二I圖，接著以 化學蝕刻方式例如乾蝕刻或濕式蝕刻方式蝕刻該第一 導電性層205,以在該絕緣層上表面203a上方及該絕緣 層下表面203b下方分別形成前述導線圖案。該導線圖 案包含該第一導電性層205、該第二導電性層206及該 第二導電性層207。在第二具體實施例中，本發明係透 過該第一貫通孔202與該第一導電性墊片2〇1上方該盲 孔204之間的前述導線圖案做為重佈線，以將該基板 的電性從第一表面200a導引至第二表面2〇〇b。再者， 前述導線圖案製作係使用該第三導電性層2〇7做為硬質 13 201216444 罩幕層，而無需使用黃光製程，進而可降低本發明的製 程成本。 此外，在第二具體實施例中，如前述可以沈積方式 形成一電性連接層填塞該第一貫通孔202及該盲孔 内。卩並覆蓋該絕緣層上表面2〇3a及該絕緣層下表面 〇3b。接著’再形成—圖案化導電性硬質罩幕層於該絕 g上表面203a及該絕緣層下表面2〇3b的該導電性層 上。在此情況下，可於後續導線圖案製作階段，以一^ 蝕刻方式蝕刻該導電性層，形成該導線圖案。 、+、制參第二；圖’接著進行晶粒堆疊步驟，係將完成上 ^程步驟的至少兩個前述基板以背面朝正面方式 隹疊接合，使彼此對應的該等導線圖案層 進行回鲜_嗜驟，使對應接合的該等第；^ 如7熔融而完整包覆對應接合的該第一導電性層2〇5及 Ϊΐ二導電性層雇。在此情況下，經圖案化二該第一 =電性層205及該第二導電性層2〇6即構成一電性連接 二於該基板200的第-表面2〇〇a及第二表面屢的該 =層203上。在第二具體實施例中，該等接合的第三 ^電性層207經回銲後可完整包覆上、下基板2⑻對接 的该等電性連接層’並使該等電性連接層透過該第三導 ，性層207互相接合，如第二j圖所示。或者如第四圖 ^不之上、下基板200對接的該等電性連接層的該等第 一導電性層206,直接接觸，而該第三導電性層2〇7完整 包覆該等電性連接層。上述晶圓級製程步驟即實現本發 明另一種三維堆疊晶粒封裝結構的製造方法。 ^參第- K圖’接著進行堆疊晶粒切割步驟，即切割 削述基板堆疊結構，以將個別堆疊晶粒從前述基板堆疊 結構中分離出來。接下來，將分離出來的個別堆疊晶粒 201216444 黏著於一電路基板210上，使前述個別堆疊晶粒下方的 基板200的第二表面2〇〇b下方的該導線圖案對應接合 該電路基板210上的至少一個第二導電性塾片212。進 行回銲步驟’使熔融的該第三導電性層207完整包覆下 方基板200第二表面2〇〇b下方的該電性連接層及對接 的s玄第二導電性墊片212，如此即完成本發明三維堆疊 晶粒的封裝結構製作。該電路基板21〇可以是一印刷電 路基板’或其材質可以是矽或陶瓷材料。須注意的是， 在本發明二維堆疊晶粒的封裝結構中堆疊晶粒之間彼 此對接的該等電性連接層及晶粒與該電路基板21〇之間 對接的該電性連接層與該第二導電性墊片212皆被回銲 後的該第三導電性層207完整包覆，故可防止該等電性 ，接層及邊第二導電性墊片212的斷裂，進而可提高該 二維堆疊晶粒的封裝結構的可靠度。 >弟二L圖，#矛一丹菔貫施例中，本發明亦可 級製程步驟而具有垂直電性導通的 1： , u* *置乃忒丨』上述，之後再以如上述方 t ί該電路基板MG上方。如此4，仍可得_ 同的二維堆疊晶粒的封裝結構。 限定：in為本發：之具體實施例而已，並非用以 干之精二之5青專利範圍；凡其它未脫離本發明所揭 之申請專·_。 修飾，均應包含在下述 15 201216444 【圖式簡單說明】 第一 A圖至第一 K圖係本發明三維堆疊晶粒封裝 結構製造方法的第一具體實施例各製程步驟對應的結 構截面示意圖； 第一 L圖係顯示依本發明第一具體實施例之製造方 法製作完成之晶圓進行晶粒切割示意圖； 第二A圖至第二K圖係本發明三維堆疊晶粒封裝 結構製造方法的第二具體實施例各製程步驟對應的結 構截面不意圖， 第二L圖係顯示依本發明第二具體實施例之製造方 法製作完成之晶圓進行晶粒切割不意圖， 第三圖係本發明第一具體實施例之一基板堆疊結 構的一變化例；及 第四圖係本發明第二具體實施例之一基板堆疊結 構的一變化例。 【主要元件符號說明】 100、 200-…基板 100a 、200a-…第一表面 100b 、200b…-第二表面 101、 201-…第一導電性墊片 102、 202-…第一貫通孔 103、 203-…絕緣層 103a、203a-…該絕緣層上表面 103b、203b…-該絕緣層下表面 104-…第二貫通孔 105、204-…盲孔 201216444 106、 205…·第一導電性層 107、 107’、206、206’-·--第二導電性層 108、 207-…第三導電性層 110、電路基板 112、212-…第二導電性墊片 17201216444 VI. Description of the Invention: [Technical Field] The present invention relates to a three-dimensional stacked die package fabrication method; in particular, to a two-dimensional stack # die seal 曰 round-scale manufacturing method.构[Previous technology] Due to the light, thin, short, and small demand for electronic products, and the narrowing of the line width of the integrated circuit, in order to achieve the above, the integrated circuit (3IMC) stacking structure is fostered. Health. j 夕 夕 夕 ( ( ( ( 〇 〇 〇 〇 〇 〇 〇 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 垂直 垂直 夕 夕 夕 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直 垂直蜀 蜀: Shake / especially accumulate in the structure, and then stack Shi Shijing month. This kind of package junction ^ connection knot = short 'can avoid the line width shrinking: bio-study = even: can be ^ transmission speed 'suitable for high-speed computing elements or memory =, the package structure is oriented vertically Wafer stacking, scalable integrated circuit stacking has become an important issue in the future: [Invention] The present invention provides a three-dimensional stacked die package structure and its fabrication: ',| 贯通 through-hole (Through-Silicon-Vias) , TSVs) The electric transmission channel, which in turn increases the electrical transmission rate. Fang Wei ^ Ming provides a kind of three-dimensional stacked die package structure and its manufacture of perforated door i. In the structure of the invention, the blind hole on the die (via_〇n-_ and the through hole between the rewiring (Redis her ution layer, RDL The design of the 201216444 stack of electrical properties from its first-surface guide method m package structure and its manufacture of sheets to prevent the reliability of the spacers; The heart-dimensional stacked die-sealed, three-dimensional stacked die-package structure and the patterned layer of the fabricated structure are directly used as the wires on the die. Furthermore, the present invention provides an embodiment of a vertical-structured grain structure. Rewiring between the blind vias and the vias on the die: to guide the electrical properties of the die from the "surface" to the opposite second surface. An embodiment of the invention provides a three-dimensional stacked die package The structure includes at least a first substrate, a second substrate, and at least one first conductive bump. The first substrate includes: at least one die, at least one first conductive pad, at least one through hole, and At least one blind hole, where the a conductive pad is formed on a first surface of the first substrate, the through hole is penetrated through the first conductive pad and the first substrate, and the blind via is formed on the first conductive pad An insulating layer is formed on the bead hole and the peripheral wall of the blind via and the first surface of the first substrate and the opposite second surface; an electrical connection layer is formed on the § 玄 insulating layer Filling the through hole and the blind hole to guide the electrical property of the first substrate from the first surface to the second surface. The second substrate structure is the same as the first substrate structure of the first substrate, and the second substrate of the fifth substrate A surface is stacked under the second surface of the first substrate, and the electrical connection layers corresponding to each other are bonded to each other. The at least one first conductive bump covers the first substrate and the first substrate are bonded to each other. The embodiment of the present invention provides a method for fabricating a three-dimensional stacked die package structure, comprising the steps of: providing a substrate having at least one die and at least one first conductive pad First table Forming at least one first through hole through the first conductive spacer and the substrate; forming an insulating layer covering the first surface of the substrate and an opposite second surface thereof and filling the first through hole; forming The at least one second through hole penetrates the insulating layer and the at least one blind hole in the corresponding first through hole above the corresponding one of the first conductive pads; forming a conductive layer to fill the second through hole and the a blind hole and the first surface and the second surface covering the substrate to guide the electrical properties of the substrate from the first surface to the second surface; respectively forming a conductive hard mask layer on the substrate Etching the conductive hard mask layer to form a conductive pattern mask on the first surface and the second surface of the substrate; etching the conductive surface of the first surface and the second surface; And the conductive layer of the first surface and the second surface of the substrate to respectively form a conductive pattern layer on the first surface and the second surface of the substrate; and stacking at least two of the foregoing substrates in a front side Joint After the mutually corresponding conductor pattern layers are bonded to each other, the conductive hard mask layers coat the conductive layers bonded to each other. An embodiment of the present invention provides a grain structure having a vertical electrical continuity, comprising a die, an insulating layer, an electrical connection layer, and at least one conductive hard mask pattern layer. The die has at least one conductive spacer, at least one through hole, and at least one blind hole, wherein the conductive pad is formed on a first surface of the die, and the through hole penetrates the conductive pad And the die and the blind via are formed above the conductive pad. The insulating layer is formed on the through hole and the peripheral wall of the blind hole and the first surface of the die and a second surface opposite thereto. The electrical connection layer is formed on the insulating layer and fills the through hole and the blind via to guide the electrical properties of the crystal 6 201233044 from the first surface to the second surface. The conductive hard mask pattern layers are individually formed on the electrical connection layer of the first surface of the die and the second surface. [Embodiment] The present invention provides a three-dimensional stacked die package structure and a manufacturing method thereof, and more particularly to a three-dimensional stacked die package structure manufactured by a wafer level process, which is coordinated by the following specific embodiments. The formula is detailed as follows. The first to first drawings are the first embodiment of the method for fabricating the three-dimensional stacked die package structure of the present invention, and the schematic cross-sections of the structures corresponding to the respective process stages are respectively illustrated. Referring to FIG. 1A, a substrate 100 is first provided. The substrate 100 has at least one die (not shown) and at least one first conductive die 101 on a first surface thereof. The substrate 丨〇〇 can be a tantalum wafer having a plurality of integrated circuit components and a plurality of metal spacers, such as a 'Ni/Au alloy spacer on its surface. The substrate 1〇〇 may be a III-V wafer or a glass wafer. Referring to FIG. 1B, a through-wafer through-hole (TSVs) technique is performed to form at least one first through-hole 102 extending through the first conductive spacer 1〇1 and the substrate ι, for example, laser drilling ( The first through hole 1〇2 is formed by laser drilling, dry etching, or wet etching. Referring to the first c-FIG., an insulating layer 103 is formed to cover the first surface 100a of the substrate 1 and the opposite second surface 100b and to fill the first through hole 1〇2. The insulating layer 103 may be a polymer insulating material layer, for example, an ABF (Ajinomoto Build-up Film) insulating film, and may be formed on the first surface 10a and the second surface of the substrate 100 by double-sided pressing. The first through hole 102 is filled in the 100b. Referring to FIG. 1D, at least one second through hole 104 is formed through the corresponding 1616444 insulating layer 103 and at least one blind hole (Via-〇n-Pad) 105 in the corresponding first through hole 1〇2. The first conductive spacer 1〇1 is above. In the first embodiment, the second through hole 104 and the blind hole 105 can be formed by laser drilling. Referring to FIG. 1E, a first conductive layer 1〇6 is formed in the peripheral wall of the second through hole 104 and the blind via 1〇5, and covers the upper surface of the insulating layer 103a and above the substrate 1? The substrate 1 is below the insulating layer lower surface 103b. In the first embodiment, the first conductive layer 1〇6 can fill the blind via 105 because the blind via 1〇5 has a smaller inner diameter. The β-first conductive layer 1〇6 is used as a seed layer to facilitate the fabrication of the subsequent electrographic metal layer. The first conductive layer 1〇6 may be a titanium tungsten (Tiw) layer deposited by sputtering. Referring to the first F pattern, a second conductive layer 107 is then deposited by electroplating or electroless plating. For example, a copper metal layer is formed on the first conductive layer 1〇6 and the second through hole 104 is filled, so that the electrical properties of the substrate 1〇〇 can be guided from the first surface 10a. To the second surface 100be, in the first embodiment, when the blind via 105 is not filled by the first conductive layer 1〇6, in the process of the subsequent second conductive layer 107, the The second conductive layer 1〇7 fills the blind via ι 5 (not shown). In the first embodiment, in the first embodiment, the present invention can also directly form an electrical connection layer by deposition to fill the second through hole 1〇4 and the blind hole 105 and cover the substrate 1〇〇. The upper surface of the insulating layer 1〇3a and the lower surface of the insulating layer 104b under the substrate 100 further guide the electrical properties of the substrate 100 from the first surface 100a to the second surface i〇0b. The first F pattern ' is then formed to form a third conductive layer 108 having a predetermined thickness on the second conductive layer 1 〇 7 above the first surface 100a and the second surface 100b of the substrate 1 . The third conductive layer 108 may be a tin solder layer formed by electrodeposition. The plating thickness of the third conductive layer 1〇8 is pre-calculated, 8 201216444, so that the minimum thickness is completely covered after the subsequent die stack bonding reflow (refl〇w). A spacer that joins the grains to each other is stacked to prevent breakage of the spacers. Referring to FIG. 1G, the third conductive layer ι 8 is used to make a wire pattern (rewiring) respectively on the first surface 10a and the second surface 1〇〇1) of the substrate 100. A conductive hard mask layer of the pattern). In the process stage, the third conductive layer 108 is patterned by laser etching to the second conductive layer on the first surface 1a and the second surface 10b of the substrate 1? A wire pattern mask is formed on each of the layers 1 to 7 to facilitate subsequent fabrication of the wire pattern on the first surface 1a and the second surface 100b of the substrate 10A. Referring to the first figure, the second conductive layer 1〇7 is engraved in a chemical or physical surname manner, for example, a dry or wet button. Referring to FIG. 1A, the first conductive layer 丨〇6 is then etched by chemical or physical etching, for example, dry etching or wet etching, to form a first surface 100a and a second surface of the substrate 1 The aforementioned wire pattern is formed above the surface 100b, respectively. The wire pattern includes the first conductive layer 106, the second conductive layer 107, and the third conductive layer 1〇8. In the first embodiment, the present invention transmits the foregoing wire pattern between the second through hole 104 and the blind hole 1〇5 above the first conductive pad 101 as a rewiring to the substrate 100. Electrical properties are directed from the first, face 100a to the second surface 100b. Furthermore, the wire pattern = using the third conductive layer 108 as a hard mask layer without using a yellow light process, thereby reducing the process cost of the present invention. In addition, in the first embodiment, an electrical connection layer can be directly formed to fill the second through hole 104 and the blind hole 105 and cover the upper surface of the insulating layer 1〇3& And the ', the lower surface of the edge layer l〇3b. Next, a pattern of a predetermined thickness of 201216444 conductive hard mask layer is formed on the conductive layer upper surface i〇3a and the insulating layer lower surface 103b. In this case, the conductive pattern can be formed in a single etching manner in the subsequent wire patterning stage to form the wire pattern. Referring to FIG. 1J, a step of performing a die stacking step of stacking and bonding at least two of the foregoing substrates 1 to complete the above-mentioned process steps with the back side facing the front side, and bonding the corresponding conductive pattern layers to each other, and performing In the reflow step, the third conductive layers 108 corresponding to the bonding are melted to completely cover the corresponding first conductive layer 1〇6 and the second conductive layer 1G7. In this case, the patterned first conductive layer 106 and the first conductive layer 107 form a snowy continuous layer on the first surface 100a of the substrate and the surface 100b of 忒 insulation layer 1 〇3. In the first embodiment, the joined third conductive layer 108 can be completely covered by the soldering and the electrical connection layer of the substrate 1 〇〇, and the electrical connection layer is transparent. The third conductive layers 108 are bonded to each other as shown in the first j diagram. Alternatively, the second conductive layers 107 are directly in contact with the electrical connection layers of the upper and lower substrates 100 as shown in the second figure, and the third conductive layer 108 completely encapsulates the electrical connection layers. . The above process steps are a wafer level manufacturing method for implementing the three-dimensional stacked die package structure of the present invention. Referring to the first K diagram, a stacked die cutting step is performed to cut the aforementioned substrate stack structure to separate the individual stacked dies from the substrate stack structure. Next, the separated individual stacked die is adhered to a circuit substrate 110 such that the wire pattern under the second surface 100b of the substrate 100 under the individual stacked die corresponds to at least one of the circuit substrate 110. The second conductive pad performs a reflow process, so that the molten third conductive layer 1〇8 completely covers the electrical connection layer under the second surface 100b of the lower substrate 100 and the butted 201216444 electrical defect piece 112. The circuit board 110 can be printed on a circuit board, or the material thereof can be cut or the second layer and the die are completely covered with the electric layer 108, so that the connection layer and the second layer can be prevented. Breakage of the conductive spacer 112: Reliability of the package structure of the three-dimensional stacked die. In the first embodiment, the present invention can also be cut and separated from the substrate 100 by a process of vertical electrical conduction, and then The crystal grains are stacked in the back surface manner in the same manner as described above, and then assembled on the circuit substrate 110 in the above manner. In this way, the package structure of the same three-dimensional stacked die can still be obtained. The second to second drawings illustrate a cross-sectional view of a second embodiment of the three-dimensional stacked die package structure of the present invention corresponding to each process stage. Referring to Figure 2A, a substrate 2 is first provided. The substrate 200 has at least one die (not shown) and at least one first conductive die 201 on a first surface 200a thereof. The substrate 200 may be a germanium wafer having a plurality of integrated circuit components and a plurality of metal pads, for example, Ni/A = alloy pads on the surface thereof. The substrate 200 may be a III-V wafer or a glass wafer. Referring to FIG. 2b, a chip through hole (TSVs) technique is performed to form at least one first through hole 202 penetrating the first conductive pad 201 and the substrate 200, for example, laser drilling and drying. The first through hole 202 is formed by a button or wet pattern. Referring to FIG. 2C, an insulating layer 203 is formed on the peripheral wall of the first through hole 202 and covers a second surface 2〇〇b opposite to the first surface 11 201216444 200a of the substrate 200. The insulating layer 2〇3 may be a tantalum dioxide or tantalum nitride layer. When the substrate 2 is a tantalum wafer, a ruthenium dioxide layer may be directly formed on the peripheral wall of the first through hole 202 by thermal oxidation to cover the first surface 200a and the second surface 200b of the substrate 200. Referring to FIG. 2D, at least one blind hole 2〇4 is formed by a laser drilling technique over a corresponding one of the first conductive pads 2〇1. Referring to FIG. 2E, a first conductive layer 205 is formed on the insulating layer 203 of the inner peripheral wall of the first through hole 202 and the insulating layer upper surface 2〇3a and the substrate 2 below the substrate 200. The insulating layer lower surface 203b and the blind via 204. Since the blind via 2〇4 has a smaller inner diameter, the first conductive layer 205 can fill the blind via 204. The first conductive layer 205 is used as a seed iayer to facilitate the subsequent fabrication of the plated metal layer. The first conductive layer 205 may be a titanium tungsten (TiW) layer deposited by a sputtering method. Referring to FIG. 2F, a second conductive layer 206 is deposited by electroplating or electroless plating. For example, a copper metal layer is formed on the first conductive layer 205 and the first through hole 2〇2 is filled and covered. The first conductive layer 205 is above the blind via 2〇4, above the insulating layer upper surface 203a and below the insulating layer lower surface 203b. In this way, the electrical properties of the substrate 200 can be guided from the first surface 200a to the second surface 200b. In the second embodiment, when the blind via 204 is not filled by the first conductive layer 205, 'in the process of the subsequent second conductive layer 206, the second conductive layer 206 may be filled in. The blind hole 204 is filled (not shown). In the second embodiment, in the second embodiment, the present invention can also directly form an electrical connection layer in a deposition manner to fill the first through hole 202 and the inside of the blind hole 204 and cover the insulation above the substrate 200. The upper surface 203a of the layer and the lower surface 203b of the insulating layer below the substrate are advanced to 12 201216444 to guide the electrical properties of the substrate 200 from the first surface 2A to the second surface 200b. The second F-picture ′ is then formed to form a third conductive layer 207 having a predetermined thickness on the upper surface 2 〇 3 a of the insulating layer and the second conductive layer 206 under the insulating layer lower surface 203b. The third conductive layer 207 may be a solder layer formed by electroplating. The plating thickness of the third conductive layer 2〇7 is pre-calculated so that the lowest thickness thereof is after the subsequent die-stack reflow (the third conductive layer 207 can completely cover the stacked crystal grains) Gaskets that are joined to each other to prevent breakage of the gaskets. Referring to the second G diagram, the third conductive layer 207 is used as a conductive hard mask for subsequently forming a conductive pattern (rewiring pattern) over the insulating layer upper surface 203a and below the insulating layer lower surface 203b. Curtain layer. In the process stage, the third conductive layer 207 is patterned by laser etching to form a second conductive layer 206 above the insulating layer upper surface 203a and below the insulating layer lower surface 203b. The wire pattern mask is adapted to facilitate subsequent fabrication of the wire pattern above the insulating layer upper surface 203a and below the insulating layer lower surface 203b. Referring to the second figure, the second conductive layer 206 is etched by a chemical etching method such as dry etching or wet etching. Referring to FIG. 1A, the first conductive layer 205 is then etched by a chemical etching method such as dry etching or wet etching to form the conductive patterns on the upper surface 203a of the insulating layer and under the lower surface 203b of the insulating layer. . The wire pattern includes the first conductive layer 205, the second conductive layer 206, and the second conductive layer 207. In the second embodiment, the present invention transmits the aforementioned wire pattern between the first through hole 202 and the blind hole 204 above the first conductive pad 2〇1 as a rewiring to electrically charge the substrate. The property is guided from the first surface 200a to the second surface 2〇〇b. Furthermore, the wire patterning process uses the third conductive layer 2〇7 as a hard 13 201216444 mask layer without using a yellow light process, thereby reducing the process cost of the present invention. In addition, in the second embodiment, an electrical connection layer is formed in the deposition manner to fill the first through hole 202 and the blind via. The upper surface 2〇3a of the insulating layer and the lower surface 〇3b of the insulating layer are covered. Next, a pattern is formed to form a conductive hard mask layer on the conductive upper layer 203a and the conductive layer lower surface 2〇3b. In this case, the conductive layer may be etched by etching in a subsequent wire patterning stage to form the wire pattern. And the second step of the ginseng; the method of performing the dies stacking step, wherein at least two of the foregoing substrates which have completed the step of the step are overlapped and joined in a front-side manner, so that the corresponding conductor pattern layers are returned to each other. The first conductive layer 2〇5 and the second conductive layer are integrally coated with the corresponding bonding. In this case, the first electrical layer 205 and the second conductive layer 2〇6 are electrically connected to the first surface 2〇〇a and the second surface of the substrate 200. Repeat this = layer 203. In the second embodiment, the bonded third electrical layer 207 can completely cover the electrically connected layers of the upper and lower substrates 2 (8) after reflowing and pass the electrically connected layers. The third conductive layer 207 is joined to each other as shown in the second j diagram. Or the first conductive layer 206 of the electrical connection layer butted on the lower substrate 200 is directly in contact, and the third conductive layer 2〇7 completely covers the same Sexual connection layer. The wafer level processing step described above implements a method of fabricating another three-dimensional stacked die package structure of the present invention. The reference to the -K diagram is followed by a stacked die cutting step of cutting the substrate stack structure to separate the individual stacked grains from the substrate stack structure. Next, the separated individual stacked die 201216444 is adhered to a circuit substrate 210, so that the wire pattern under the second surface 2〇〇b of the substrate 200 under the individual stacked die is correspondingly bonded to the circuit substrate 210. At least one second conductive cymbal 212. Performing a reflow soldering step 'completely coating the molten third conductive layer 207 with the electrical connection layer under the second surface 2〇〇b of the lower substrate 200 and the butted second conductive spacer 212, thus The package structure of the three-dimensional stacked die of the present invention is completed. The circuit substrate 21A may be a printed circuit substrate ‘ or its material may be tantalum or ceramic material. It should be noted that, in the package structure of the two-dimensional stacked die of the present invention, the electrical connection layer and the die and the electrical connection layer between the die and the circuit substrate 21 are overlapped with each other. The second conductive spacers 212 are completely covered by the third conductive layer 207 after reflow, so that the electrical properties can be prevented, and the connection layer and the second conductive spacer 212 can be broken, thereby improving The reliability of the package structure of the two-dimensional stacked die. >Di Er L diagram, #矛一丹菔例, the invention can also be a step of the process and have vertical electrical conduction of 1:, u* t ί above the circuit board MG. In this way, the package structure of the same two-dimensional stacked die can still be obtained. The invention is limited to the specific embodiment of the present invention, and is not intended to be used in the scope of the patent application; The modification is to be included in the following 15 201216444 [Simplified description of the drawings] The first A to the first K are schematic cross-sectional views of the respective process steps of the first embodiment of the method for fabricating the three-dimensional stacked die package structure of the present invention; The first L diagram shows a schematic diagram of performing grain cutting on a wafer fabricated by the manufacturing method of the first embodiment of the present invention; the second to second K diagrams are the third method of manufacturing the three-dimensional stacked die package structure of the present invention. The second embodiment is not intended to be a wafer cut according to the manufacturing method of the second embodiment of the present invention, and the third figure is the first aspect of the present invention. A variation of the substrate stack structure of one embodiment; and a fourth diagram is a variation of the substrate stack structure of a second embodiment of the present invention. [Description of main component symbols] 100, 200-...substrate 100a, 200a-...first surface 100b, 200b...-second surface 101, 201-...first conductive spacer 102, 202-...first through hole 103, 203-...insulating layer 103a, 203a-...the insulating layer upper surface 103b, 203b...-the insulating layer lower surface 104-...the second through hole 105,204-...blind hole 201216444 106, 205...·first conductive layer 107, 107', 206, 206'----the second conductive layer 108, 207-...the third conductive layer 110, the circuit substrate 112, 212-...the second conductive spacer 17