CN116072607A - Package structure, forming method thereof and electronic equipment - Google Patents
Package structure, forming method thereof and electronic equipment Download PDFInfo
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- CN116072607A CN116072607A CN202310210873.4A CN202310210873A CN116072607A CN 116072607 A CN116072607 A CN 116072607A CN 202310210873 A CN202310210873 A CN 202310210873A CN 116072607 A CN116072607 A CN 116072607A
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 22
- 230000000149 penetrating effect Effects 0.000 claims abstract description 10
- 238000004806 packaging method and process Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 58
- 239000002184 metal Substances 0.000 claims description 58
- 239000003989 dielectric material Substances 0.000 claims description 26
- 235000012431 wafers Nutrition 0.000 description 304
- 238000010586 diagram Methods 0.000 description 12
- 238000009713 electroplating Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000012536 packaging technology Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000009736 wetting Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
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- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The embodiment of the disclosure provides a packaging structure, a forming method thereof and electronic equipment. The forming method comprises the following steps: providing a first wafer having a first face and a second face opposite to each other; forming a first conductive blind hole structure in the first wafer, and exposing the first surface; bonding at least one wafer including a second wafer at the first face, the second wafer having a third face facing the first face and a fourth face opposite the third face and including a second conductive blind via structure; etching the second surface of the first wafer and the fourth surface of the second wafer respectively to form a first conductive through hole structure and a second conductive through hole structure; the first conductive via structure and the second conductive via structure form a mother via structure penetrating the first wafer and the second wafer; and forming conductive wiring layers on the second surface of the first wafer and the fourth surface of the second wafer respectively for electrically connecting the female through hole structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and relates, but is not limited to, a package structure, a method of forming the same, and an electronic device.
Background
The laminated chip packaging technology, namely three-dimensional space integrated circuit (3-Dimension Integrated Circuit, 3 DIC) packaging technology, refers to packaging technology for stacking more than two chips in the vertical direction in the same package body on the premise of not changing the size of the package body. As one of 3DIC packaging technologies, through silicon via (Through Silicon Via, TSV) packaging technology utilizes vertical through silicon vias to complete the interconnection of chips, which can achieve smaller, thinner, better performing, higher density, significantly reduced size and weight packages due to shorter connection distances and higher strength, while also being able to be used for interconnection between heterogeneous chips.
The TSV packaging structure is continuously developed towards the small size direction, so that the diameter of the TSV packaging structure is continuously reduced; accordingly, the TSV packaging technology must also be gradually developed towards a high aspect ratio, so that the interconnection density of the TSV packaging structure is higher and higher. After the depth-to-width ratio of the TSV packaging structure is gradually increased, a compact and uniform copper (Cu) seed layer can not be obtained by adopting a traditional method, particularly, the copper seed layer at an included angle position formed by the bottom of the blind hole and the side wall is thinner, so that Cu filled in the blind hole is uneven, and holes are easy to appear.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a package structure, a method for forming the package structure, and an electronic device.
In a first aspect, an embodiment of the present disclosure provides a method for forming a package structure, including the following steps:
providing a first wafer having opposite first and second sides;
forming a first conductive blind via structure in the first wafer, the first conductive blind via structure being exposed from the first face;
bonding at least one wafer including a second wafer on the first face, the second wafer having a third face facing the first face and a fourth face opposite the third face and including a second conductive blind via structure electrically connected to the first conductive blind via structure;
etching the second surface of the first wafer and the fourth surface of the second wafer respectively to expose the first conductive blind hole structure to form a first conductive through hole structure and expose the second conductive blind hole structure to form a second conductive through hole structure; wherein the first conductive via structure and the second conductive via structure form a female via structure penetrating the first wafer and the second wafer;
And forming conductive wiring layers on the second surface of the first wafer and the fourth surface of the second wafer respectively, wherein the conductive wiring layers are used for electrically connecting the female through hole structure.
In some embodiments of the disclosure, the forming a first conductive blind via structure on the first side of the first wafer includes:
etching the first surface of the first wafer to form at least one first blind hole;
covering a first insulating layer on the first surface and the inner surface of the first blind hole;
and filling conductive metal in the first blind holes covered with the first insulating layer to form the first conductive blind hole structure.
In some embodiments of the present disclosure, the forming method further comprises:
and thinning the first wafer from the second surface of the first wafer.
In some embodiments of the present disclosure, the forming method further comprises:
providing a second wafer, forming the second conductive blind via structure in the second wafer, wherein the second conductive blind via structure is exposed from the third face.
In some embodiments of the present disclosure, the forming the second conductive blind via structure in the second wafer includes:
etching the third surface of the second wafer to form at least one second blind hole;
Covering a second insulating layer on the third surface and the inner surface of the second blind hole;
and filling conductive metal in the second blind holes covered with the second insulating layer to form the second conductive blind hole structure.
In some embodiments of the present disclosure, the forming method further comprises:
and thinning the second wafer from the fourth surface of the second wafer.
In some embodiments of the present disclosure, the bonding at least one wafer including a second wafer at the first face of the first wafer includes:
bonding a third wafer on the first surface of the first wafer, wherein the third wafer is provided with a fifth surface facing the first surface and a sixth surface opposite to the fifth surface, and comprises a third conductive through hole structure electrically connected with the first conductive blind hole structure;
and bonding the second wafer on one side of the third wafer far away from the first wafer, wherein the second conductive blind hole structure is electrically connected with the first conductive blind hole structure through the third conductive through hole structure.
In some embodiments of the present disclosure, the forming method further comprises:
providing the third wafer, forming the third conductive through hole structure in the third wafer, wherein the third conductive through hole structure is exposed from the fifth surface and the sixth surface of the third wafer.
In some embodiments of the present disclosure, the forming the third conductive via structure in the third wafer includes:
forming a third conductive blind via structure in the third wafer, the third conductive blind via structure emerging from the fifth face;
etching the sixth surface of the third wafer to expose the third conductive blind hole structure;
and flattening the third wafer and the third conductive blind hole structure from the sixth surface of the third wafer to form the third conductive through hole structure.
In some embodiments of the present disclosure, the forming a third conductive blind via structure in the third wafer includes:
etching the fifth surface of the third wafer to form at least one third blind hole;
covering the inner surfaces of the fifth surface and the third blind holes with a third insulating layer;
and filling conductive metal in the third blind hole covered with the third insulating layer to form the third conductive blind hole structure.
In some embodiments of the present disclosure, the forming conductive trace layers on the second surface of the first wafer and the fourth surface of the second wafer includes:
forming a first dielectric layer on a second surface of the first wafer;
Forming a second dielectric layer on a fourth surface of the second wafer;
forming a first wiring layer on the surface of one side, far away from the first wafer, of the first dielectric layer;
and forming a second wiring layer on the surface of one side of the second dielectric layer, which is far away from the second wafer.
In some embodiments of the present disclosure, the forming a first dielectric layer on the second surface of the first wafer includes:
forming a first dielectric material on a second surface of the first wafer, wherein the first dielectric material is covered on the first wafer and the first conductive blind hole structure;
and flattening the first dielectric material and the first conductive blind hole structure from the second surface of the first wafer, exposing the conductive metal in the first conductive blind hole structure and forming the first dielectric layer.
In some embodiments of the disclosure, the forming a second dielectric layer on a surface of the second wafer away from the first wafer includes:
forming a second dielectric material on the surface of one side of the second wafer far away from the first wafer, wherein the second dielectric material is covered on the second wafer and the second conductive blind hole structure;
and flattening the second dielectric material and the second conductive blind hole structure from the fourth surface of the second wafer, exposing the conductive metal in the second conductive blind hole structure and forming the second dielectric layer.
In a second aspect, embodiments of the present disclosure provide a package structure, including:
a first wafer having opposite first and second sides, the first wafer including a first conductive via structure;
at least one wafer including a second wafer, located at one side of the first wafer and bonded to the first surface, the second wafer having a third surface facing the first surface and a fourth surface opposite to the third surface and including a second conductive via structure electrically connected to the first conductive via structure, the first conductive via structure and the second conductive via structure forming a through-going female via structure;
and the conductive wiring layer is respectively positioned on the second surface of the first wafer and the fourth surface of the second wafer and is electrically connected with the female through hole structure.
In some embodiments of the present disclosure, the first conductive via structure includes a first insulating layer and a conductive metal, the first wafer has a first via, and inner and outer surfaces of the first insulating layer are in contact with the conductive metal and inner surfaces of the first via, respectively.
In some embodiments of the present disclosure, the conductive trace layer includes a first dielectric layer and a first wiring layer;
The first dielectric layer is covered on one side of the first wafer, which is far away from the second wafer, and exposes the conductive metal in the first conductive through hole structure, and the first wiring layer covers the conductive metal and covers a partial area of the first dielectric layer.
In some embodiments of the present disclosure, the second conductive via structure includes a second insulating layer and a conductive metal, the second wafer has a second via, and inner and outer surfaces of the second insulating layer are in contact with the conductive metal and inner surfaces of the second via, respectively.
In some embodiments of the present disclosure, the conductive trace layer includes a second dielectric layer and a second wiring layer;
the second dielectric layer is covered on one side of the second wafer far away from the first wafer, the conductive metal in the second conductive through hole structure is exposed, and the second wiring layer covers the conductive metal and covers a partial area of the second dielectric layer.
In some embodiments of the present disclosure, the at least one wafer further comprises a third wafer comprising a third conductive via structure;
the third wafer is located between the first wafer and the second wafer and is bonded with the first wafer and the second wafer respectively, and the third conductive through hole structure is electrically connected with the first conductive through hole structure and the second conductive through hole structure respectively.
In a third aspect, embodiments of the present disclosure provide an electronic device including a package structure formed by the forming method of any one of the embodiments of the first aspect.
In the method for forming the package structure provided by the embodiment of the disclosure, the first wafer is bonded with at least one wafer including the second wafer, so that the conductive via structures of the plurality of wafers form a penetrating female via structure, i.e. a via structure with a larger depth-to-width ratio. Because the depth-to-width ratio of the female through hole structure is larger than that of the conductive through hole in any wafer, and the manufacturing difficulty of the conductive through hole structure for one wafer is smaller than that of the female through hole structure formed at one time, the possibility that hole defects are generated in the female through hole structure due to the fact that the depth-to-width ratio of the female through hole structure is higher and the non-uniformity of the conductive metal injection is effectively reduced, and the product yield of the through hole structure with the larger depth-to-width ratio is further improved.
Drawings
Fig. 1 is a flow chart illustrating a method for forming a package structure according to an embodiment of the disclosure;
fig. 2 is a schematic step diagram of a method for forming a package structure according to an embodiment of the disclosure;
fig. 3 is a step-by-step schematic diagram II of a method for forming a package structure according to an embodiment of the disclosure;
Fig. 4 is a step-by-step schematic diagram III of a method for forming a package structure according to an embodiment of the disclosure;
fig. 5 is a step-by-step schematic diagram of a method for forming a package structure according to an embodiment of the disclosure;
fig. 6 is a step-by-step schematic diagram of a method for forming a package structure according to an embodiment of the disclosure;
fig. 7 is a step-by-step schematic diagram sixth of a method for forming a package structure according to an embodiment of the disclosure;
fig. 8 is a step-by-step schematic diagram seven of a method for forming a package structure according to an embodiment of the disclosure;
fig. 9 is a schematic step diagram eight of a method for forming a package structure according to an embodiment of the disclosure;
fig. 10 is a step-by-step schematic diagram nine of a method for forming a package structure according to an embodiment of the disclosure;
fig. 11 is a schematic step diagram ten of a method for forming a package structure according to an embodiment of the disclosure;
fig. 12 is a step-by-step schematic diagram eleven of a method for forming a package structure according to an embodiment of the disclosure.
Reference numerals:
10-a first wafer; 11-a first conductive blind via structure; 111-a first insulating layer; 112-a first conductive metal;
20-a second wafer; 21-a second conductive blind via structure; 211-a second insulating layer; 212-a second conductive metal;
30-a third wafer; 31-a third conductive blind via structure; 311-a third insulating layer; 312-a third conductive metal;
411-a first dielectric material; 412-a first dielectric layer; 421-a second dielectric material; 422 a second dielectric layer;
43-a first wiring layer; 44-second wiring layer.
Detailed Description
In order to facilitate an understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the associated drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, some technical features well known in the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation may be described in detail herein, nor are well-known functions and constructions described in detail.
Generally, the term may be understood, at least in part, from the use of context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a" or "an" may also be understood to convey a singular usage or a plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.
Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
In a first aspect, embodiments of the present disclosure provide a method for forming a package structure. As shown in fig. 1, fig. 1 is a flow chart illustrating a method for forming a package structure according to an embodiment of the disclosure; fig. 2-12 are schematic step diagrams illustrating a method for forming a package structure according to an embodiment of the disclosure. The forming method of the packaging structure comprises the following steps:
s1, providing a first wafer 10, wherein the first wafer 10 is provided with a first surface and a second surface which are opposite;
s2, forming a first conductive blind hole structure 11 in the first wafer 10, wherein the first conductive blind hole structure 11 is exposed from the first surface;
s3, bonding at least one wafer including a second wafer 20 on the first surface, wherein the second wafer 20 is provided with a third surface facing the first surface and a fourth surface opposite to the third surface, and comprises a second conductive blind hole structure 21 electrically connected with the first conductive blind hole structure 11;
S4, etching the second surface of the first wafer 10 and the fourth surface of the second wafer 20 respectively to expose the first conductive blind hole structure 11 to form a first conductive through hole structure and expose the second conductive blind hole structure 21 to form a second conductive through hole structure; wherein the first conductive via structure and the second conductive via structure form a female via structure penetrating the first wafer 10 and the second wafer 20;
s5, forming conductive wiring layers on the second surface of the first wafer 10 and the fourth surface of the second wafer 20 respectively, wherein the conductive wiring layers are used for electrically connecting the female through hole structure.
In this embodiment, at least the first conductive via structure and the second conductive via structure form a female via structure penetrating the first wafer 10 and the second wafer 20 by bonding the first side of the first wafer 10 to at least one wafer including the second wafer 20.
In this embodiment, the female via structure is not formed in one step, and is formed by splicing at least two conductive via structures, including a first conductive via structure and a second conductive via structure. The first surface of the first wafer 10 is bonded to the third surface of the second wafer 20, and the splicing direction of the first conductive via structure and the second conductive via structure is a female via structure penetrating through the first wafer 10 and the second wafer 20, and the aspect ratio of the female via structure is greater than the aspect ratio of either of the first conductive via structure and the second conductive via structure.
The process of making the female through-hole may include at least two of the following:
in at least one embodiment of the first case, the first conductive via structure 11 and the second conductive via structure 21 are fabricated separately, and the first conductive via structure 12 and the second conductive via structure 22 are formed after being spliced with each other. Here, the first wafer 10 is spliced with the second wafer, and a surface of the first wafer 10 exposing the first conductive via structure 11 (i.e., the first surface) and a surface of the second wafer 20 exposing the second conductive via structure 21 (i.e., the third surface) are bonded to each other, so that the first conductive via structure 11 and the second conductive via structure 21 are in communication with each other. At this time, since the second surface of the first wafer 10 is not exposed to the first conductive via structure 11, the surface may be thinned until the first conductive via structure 11 is exposed, and of course, the first conductive via structure 11 is not a blind via, but penetrates through the thinned first conductive via structure of the first wafer 10. Similarly, the side of the second wafer 20 not exposed by the second conductive via structure 21 is thinned until the second conductive via structure 21 is exposed, so as to form a second conductive via structure 22 penetrating through the second wafer 20. At this time, the first conductive via structure and the second conductive via structure form a female via structure which is connected to each other and penetrates the first wafer 10 and the second wafer.
In at least one embodiment of the second case, the first conductive blind via structure 11 and the second conductive blind via structure 21 may be fabricated first. The first wafer 10 and the second wafer 20 are then thinned, respectively, such that the first conductive via structures 11 penetrate the first wafer 10 to obtain first conductive via structures, and the second conductive via structures 21 penetrate the second wafer 20 to obtain second conductive via structures 22. Finally, the thinned first wafer 10 and the thinned second wafer 20 are bonded, so that the first conductive via structure and the second conductive via structure 22 are mutually communicated to form a mother via structure penetrating through the first wafer 10 and the second wafer 20.
In addition to the above two cases, the bonded wafers are not limited to the first wafer 10 and the second wafer 20, but may be bonded together by stacking a plurality of wafers. Illustratively, taking the first case as an example, after bonding the first wafer 10 and the second wafer 20, the two outward surfaces are thinned, and then at least one wafer with a conductive blind via structure or a conductive through via structure is continuously bonded. Specifically, a wafer having the same conductive via structure as the first wafer 10 may be continuously bonded to the thinned surface of the first wafer 10, and the conductive via structure of the wafer, the first conductive via structure and the second conductive via structure 22 together form a mother via structure penetrating through 3 wafers. Further, additional wafers may be bonded on the wafer, and may also be bonded on the surface of the second wafer 20, and in summary, the number of stacked wafers may be determined according to actual requirements, which will not be described herein.
Taking the second case as an example, the first wafer 10 including the first conductive via structure, the second wafer 20 including the second conductive via structure 22, and at least one other wafer also including the conductive via structure may be first fabricated. And then sequentially stacking and bonding the wafers to ensure that the conductive through hole structures of the wafers are mutually communicated to form a mother through hole structure.
Compared with the primary forming of the female through hole structure, the first conductive through hole structure and the second conductive through hole structure are smaller in depth-to-width ratio, and the manufacturing difficulty is smaller than that of the primary forming of the female through hole structure. Under the conditions of reducing the manufacturing difficulty and the process cost, the depth-to-width ratio of the through hole structure in each wafer structure is smaller, the risk of generating holes in the through hole structure is reduced, and the product quality of the through hole structure is improved. Thus, the probability of increased interconnection resistance of the female via structure and even open circuit failure of the component caused by the holes is reduced.
It should be noted that the above method of wafer bonding may be hybrid bonding, and the hybrid bonding method may enable the device to have higher current load capability and better thermal performance. The copper-copper direct connection achieved by hybrid bonding has better applicability to the conductive vias with high aspect ratio structures described above.
In some embodiments of the present disclosure, the forming the first conductive blind via structure 11 on the first surface of the first wafer 10 includes:
etching the first surface of the first wafer 10 to form at least one first blind hole;
covering the first surface and the inner surface of the first blind hole with a first insulating layer 111; as shown in fig. 2.
The first blind via covered with the first insulating layer 111 is filled with a first conductive metal 112 to form the first conductive blind via structure 11. As shown in fig. 3.
On the basis of the above-described embodiment, in the present embodiment, filling the first conductive metal 112 in the first blind hole covered with the first insulating layer 111 is performed using a plating conductive metal. The filling process of electroplating conductive metal is carried out from the side wall of the first blind hole to the axle center of the first blind hole. The deposition rate of a portion of the conductive metal increases with increasing plating current density, such as copper. Because the electroplating current density at the opening of the first blind hole is larger, the opening of the first blind hole is filled earlier than the area close to the bottom in the first blind hole until the opening of the first blind hole is filled. If the aspect ratio of the first blind hole is too large, the area, close to the bottom, in the first blind hole is not filled with the material, and the area, close to the bottom, in the first blind hole is easy to generate holes.
Because the first conductive through hole structure and the second conductive through hole structure which are spliced are utilized to replace the primary formed female through hole structure in the embodiment, the depth-to-width ratio of the first blind hole can be effectively controlled, and the probability of holes in the area, close to the bottom, of the first blind hole is reduced.
In an alternative embodiment, in order to improve the electroplating effect and avoid uneven hole wall and poor wetting caused by the shell effect generated by the etching process, vacuum pretreatment is also adopted in the embodiment. The quality of the surface treatment of the substrate directly influences the quality of the electroplated coating, rare gas such as argon is injected into the vacuum environment to impact the target, and the target is separated into molecules which are adsorbed by the conductive workpiece to form a uniform and smooth metal-like surface. The vacuum pretreated substrate surface will have the electroplated layer in direct contact with and in firm contact with the substrate surface.
In some embodiments of the present disclosure, the forming method further comprises:
the first wafer 10 is thinned from the second face of the first wafer 10. As shown in fig. 4.
In one embodiment, after the first conductive via structure 11 is fabricated and before bonding other wafers, a side of the first conductive via structure 11 away from the opening is thinned to reduce the distance between the bottom of the first conductive via and the second surface of the first wafer 10. Further etching of the second side of the first wafer 10 is facilitated in a subsequent process for fabricating the first conductive via structure.
In another embodiment, after the first conductive via structure 11 is fabricated, the side far from the opening of the first conductive via is not processed for a while and is directly bonded with other wafers. In the subsequent process of forming the first conductive via structure from the first conductive via structure 11, the second surface of the first wafer 10 is directly etched until the first conductive via structure 11 is exposed, so that the first conductive via structure 11 penetrates through the first wafer 10 to form the first conductive via structure.
In some embodiments of the present disclosure, the forming method further comprises:
a second wafer 20 is provided, said second conductive blind via structure 21 is formed in said second wafer 20, said second conductive blind via structure 21 being exposed from said third face.
In one embodiment of the present disclosure, the package structure is composed of a first wafer 10 and a second wafer 20, the second wafer 20 also includes a conductive via structure, defined as a second conductive via structure 21, which is formed by the second conductive via structure 21 in a subsequent process. The female via structure is comprised of a first conductive via structure and a second conductive via structure.
In this embodiment, the forming method includes: bonding a third surface of the second wafer 20 on the first surface of the first wafer 10, wherein the first conductive blind hole structure 11 is directly connected with the second conductive blind hole structure 21;
Etching the second surface of the first wafer 10 and the fourth surface of the second wafer 20 respectively to expose the first conductive via structures 11 to form first conductive via structures and expose the second conductive via structures 21 to form second conductive via structures;
forming conductive trace layers on the second surface of the first wafer 10 and the fourth surface of the second wafer 20, wherein the conductive trace layers are used for electrically connecting the female through hole structure; the conductive trace layer covering the second surface of the first wafer 10 is electrically connected to the conductive trace layer covering the fourth surface of the second wafer 20 through the first conductive via structure and the second conductive via structure.
In some embodiments of the present disclosure, the forming the second conductive blind via structure 21 in the second wafer 20 includes:
etching the third surface of the second wafer 20 to form at least one second blind hole;
covering a second insulating layer 211 on the third surface and the inner surface of the second blind hole;
the second blind via covered with the second insulating layer 211 is filled with a second conductive metal 212 to form the second conductive blind via structure 21.
On the basis of the above-described embodiment, in the present embodiment, filling the second conductive metal 212 in the second blind via covered with the second insulating layer 211 is performed using a plating conductive metal. The filling process of the electroplated conductive metal is carried out from the side wall of the second blind hole to the axle center of the second blind hole. The deposition rate of a portion of the conductive metal increases with increasing plating current density, such as copper. Because the electroplating current density at the opening of the second blind hole is larger, the opening of the second blind hole is filled earlier than the area close to the bottom in the second blind hole until the opening of the second blind hole is filled. If the depth-to-width ratio of the second blind hole is too large, the area, close to the bottom, of the second blind hole is not filled with the material, and the area, close to the bottom, of the second blind hole is easy to generate holes. Because the first conductive through hole structure and the second conductive through hole structure which are spliced are utilized to replace the one-time formed female through hole structure in the embodiment, the depth-to-width ratio of the second blind hole can be effectively controlled, and holes in the area, close to the bottom, of the second blind hole are avoided.
In an alternative embodiment, in order to improve the electroplating effect and avoid uneven hole wall and poor wetting caused by the shell effect generated by the etching process, vacuum pretreatment is also adopted in the embodiment.
In some embodiments of the present disclosure, the forming method further comprises:
the second wafer 20 is thinned from a fourth side of the second wafer 20.
In one embodiment, after the second conductive via structure 21 is fabricated and before bonding other wafers, the side far from the opening of the second conductive via structure 21 is thinned to reduce the space between the bottom of the second conductive via and the fourth surface of the second wafer 20. The fourth surface of the second wafer 20 is further etched during the subsequent process of fabricating the second conductive via structure.
In another embodiment, after the second conductive via structure 21 is fabricated, the side far from the second conductive via opening is not processed for a while and directly bonded with other wafers. In the subsequent process of forming the second conductive via structure from the second conductive via structure 21, the fourth surface of the second wafer 20 is directly etched until the second conductive via structure 21 is exposed, so that the second conductive via structure 21 penetrates through the second wafer 20 to form the second conductive via structure.
In some embodiments of the present disclosure, the bonding at least one wafer including the second wafer 20 on the first face of the first wafer 10 includes:
bonding a third wafer 30 on the first surface of the first wafer 10, wherein the third wafer 30 has a fifth surface facing the first surface and a sixth surface opposite to the fifth surface, and comprises a third conductive via structure electrically connected with the first conductive blind via structure 11;
the second wafer 20 is bonded on a side of the third wafer 30 away from the first wafer 10, and the second conductive via structure 21 is electrically connected to the first conductive via structure 11 through the third conductive via structure.
In another embodiment of the present disclosure, the package structure includes at least one other wafer in addition to the first and second wafers 10, 20, the at least one other wafer including at least one other conductive via structure, and the mother via structure includes at least one other conductive via structure in addition to the first and second conductive via structures. At least one other wafer is located between the first wafer 10 and the second wafer 20, and the mother via structure is composed of a first conductive via structure, at least one other conductive via structure, and a second conductive via structure that extend therethrough.
Taking the third wafer 30 as an example, the third wafer 30 includes a third conductive via structure, and the forming method includes: bonding a fifth side of the third wafer 30 to the first side of the first wafer 10; as shown in fig. 5.
Etching the second surface of the first wafer 10 and the sixth surface of the third wafer 30 respectively to expose the first conductive via structures 11 to form first conductive via structures 11 and expose the third conductive via structures 31 to form third conductive via structures; as shown in fig. 6.
In some embodiments of the present disclosure, the forming method further comprises:
the third wafer 30 is provided, and the third conductive via structure 31 is formed in the third wafer 30, the third conductive via structure being exposed from a fifth, sixth face of the third wafer 30.
In the present embodiment, the third wafer 30 is located between the first wafer 10 and the second wafer 20. Both ends of the third conductive via structure 31 are directly connected to the first conductive via structure and the second conductive via structure, respectively.
In some embodiments of the present disclosure, the forming the third conductive via structure in the third wafer 30 includes:
forming a third conductive blind via structure 31 in the third wafer 30, the third conductive blind via structure 31 emerging from the fifth face;
Etching the sixth surface of the third wafer 30 to expose the third conductive blind via structure 31;
the third wafer 30 and the third conductive via structure 31 are planarized from a sixth face of the third wafer 30, forming the third conductive via structure. As shown in fig. 7.
In this embodiment, after the first wafer 10 is bonded to the third wafer 30, the second surface of the first wafer 10 and the sixth surface of the third wafer 30 are etched respectively to expose the first conductive via structure 11 and the third conductive via structure 31 to form a first conductive via structure and a third conductive via structure respectively.
From the sixth surface of the third wafer 30, the third insulating layer 311 at the end of the third conductive via structure is removed, and the third conductive metal 312 in the third conductive via structure is exposed. The third conductive metal 312 in the third conductive via structure, the third insulating layer 311 covered on the sidewall, and the sixth surface of the third wafer 30 are flush on the surface of the side remote from the first wafer 10.
The sixth surface of the third wafer 30 is bonded to the third surface of the second wafer 20, and the exposed portion of the second conductive via structure 21 in the second wafer 20 is directly connected to the exposed portion of the third conductive via structure. As shown in fig. 8.
The fourth surface of the second wafer 20 is etched to expose the second conductive via structure 21 to form a second conductive via structure. As shown in fig. 9.
In yet another embodiment of the present disclosure, the package structure further includes a fourth wafer or even more wafers, all of which are disposed between the first wafer 10 and the second wafer 20, and the method of forming the wafers is the same as that of the third wafer 30, and the first conductive via structure is connected in series with the second conductive via structure through the respective conductive via structures of the wafers.
In some embodiments of the present disclosure, the forming the third conductive blind via structure 31 in the third wafer 30 includes:
etching on the fifth surface of the third wafer 30 to form at least one third blind hole;
covering the inner surfaces of the fifth surface and the third blind hole with a third insulating layer 311;
third conductive metal 312 is filled in the third blind via covered with the third insulating layer 311 to form the third conductive blind via structure 31.
In this embodiment, before the third wafer 30 is bonded to the first wafer 10, a third conductive via structure 31 is formed in the third wafer 30, and a third conductive metal 312 is filled in the third via covered with the third insulating layer 311 by electroplating a conductive metal.
In an alternative embodiment, in order to improve the electroplating effect and avoid uneven hole wall and poor wetting caused by the shell effect generated by the etching process, vacuum pretreatment is also adopted in the embodiment.
In some embodiments of the present disclosure, the forming conductive trace layers on the second surface of the first wafer 10 and the fourth surface of the second wafer 20 includes:
forming a first dielectric layer 412 on a second surface of the first wafer 10;
forming a second dielectric layer 422 on a fourth surface of the second wafer 20;
forming a first wiring layer 43 on a surface of the first dielectric layer 412 away from the first wafer 10;
a second wiring layer 44 is formed on a surface of the second dielectric layer 422 away from the second wafer 20. As shown in fig. 12.
In this embodiment, the first dielectric layer 412 and the second dielectric layer 422 each have a plurality of openings, each of the first conductive via structures is exposed from one of the openings of the first dielectric layer 412, and the first conductive via structures are flush with the first dielectric layer 412 on a side surface away from the second wafer 20. Each of the second conductive via structures emerges from one of the openings of the second dielectric layer 422 and is flush with a surface of the second dielectric layer 422 on a side remote from the first wafer 10.
The orthographic projection of the first wiring layer 43 on the first dielectric layer 412 covers the first conductive via structure, the orthographic projection of the second wiring layer 44 on the second dielectric layer 422 covers the second conductive via structure, and the first wiring layer 43 is electrically connected with the second wiring layer 44 through the female conductive via structure.
In some embodiments of the present disclosure, the forming the first dielectric layer 412 on the second surface of the first wafer 10 includes:
forming a first dielectric material 411 on a second surface of the first wafer 10, where the first dielectric material 411 is covered on the first wafer 10 and the first conductive blind hole structure 11; as shown in fig. 10.
Planarization is performed from the second face of the first wafer 10 to the first dielectric material 411 and the first conductive blind via structure 11, exposing the first conductive metal 112 in the first conductive blind via structure 11 and forming the first dielectric layer 412. As shown in fig. 11.
In this embodiment, the first dielectric material 411 is formed on the second surface of the first wafer 10, at this time, the first conductive via structure protrudes from the second surface of the first wafer 10, and the first dielectric material 411 is disposed on the surfaces of the first wafer 10 and the first conductive via structure on the side far away from the second wafer 20.
The first dielectric material 411 is an insulating material, and specifically includes one or any combination of silicon oxide (SiO 2), silicon nitride (Si 3N 4), and aluminum oxide (Al 2O 3) materials.
In some embodiments of the present disclosure, the forming the second dielectric layer 422 on a surface of the second wafer 20 away from the first wafer 10 includes:
forming a second dielectric material 421 on a surface of the second wafer 20 away from the first wafer 10, where the second dielectric material 421 covers the second wafer 20 and the second conductive blind via structure 21;
the second dielectric material 421 and the second conductive blind via structure 21 are planarized from the fourth face of the second wafer 20, exposing the second conductive metal 212 in the second conductive blind via structure 21 and forming the second dielectric layer 422.
In this embodiment, the first dielectric material 411 is formed on the fourth surface of the second wafer 20, at this time, the second conductive via structure protrudes from the fourth surface of the second wafer 20, and the second dielectric material 421 covers the surfaces of the second wafer 20 and the second conductive via structure on the side far away from the first wafer 10.
The second dielectric material 421 is an insulating material, and specifically includes one or any combination of silicon oxide, silicon nitride, and aluminum oxide materials.
Based on the same concept, in a second aspect, an embodiment of the present disclosure provides a package structure, including:
a first wafer 10 having opposite first and second sides, the first wafer 10 including a first conductive via structure;
at least one wafer including a second wafer 20, located on one side of the first wafer 10 and bonded to the first surface, the second wafer 20 having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a second conductive via structure electrically connected to the first conductive via structure, the first conductive via structure and the second conductive via structure forming a through-going female via structure;
the conductive trace layer is respectively located on the second surface of the first wafer 10 and the fourth surface of the second wafer 20, and is electrically connected with the female via structure.
In this embodiment, the first side of the first wafer 10 is bonded to at least one wafer including the second wafer 20 such that at least the first conductive via structure and the second conductive via structure form a female via structure extending through the first wafer 10 and the second wafer 20. The aspect ratio of the female via structure is greater than the aspect ratio of either of the first conductive via structure and the second conductive via structure. Under the conditions of reducing the manufacturing difficulty and the process cost, the depth-to-width ratio of the through hole structure in each wafer structure is smaller, the risk of generating holes in the through hole structure is reduced, and the product quality of the through hole structure is improved. Thus, the probability of increased interconnection resistance of the female via structure and even open circuit failure of the component caused by the holes is reduced.
In some embodiments of the present disclosure, the first conductive via structure includes a first insulating layer 111 and a conductive metal, the first wafer 10 has a first via, and inner and outer surfaces of the first insulating layer 111 are respectively in contact with the conductive metal and inner surfaces of the first via.
In the present embodiment, the first insulating layer 111 is located between the first substrate and the first conductive metal 112 in the first wafer 10, and isolates the first substrate from the first conductive metal 112.
In some embodiments of the present disclosure, the conductive trace layer includes a first dielectric layer 412 and a first wiring layer 43;
the first dielectric layer 412 is disposed on a side of the first wafer 10 away from the second wafer 20, exposing the first conductive metal 112 in the first conductive via structure, and the first wiring layer 43 covers the first conductive metal 112 and covers a partial area of the first dielectric layer 412.
In this embodiment, the first dielectric layer 412 and the second dielectric layer 422 each have a plurality of openings, each of the first conductive via structures is exposed from one of the openings of the first dielectric layer 412, and the first conductive via structures are flush with the first dielectric layer 412 on a side surface away from the second wafer 20. Each of the second conductive via structures emerges from one of the openings of the second dielectric layer 422 and is flush with a surface of the second dielectric layer 422 on a side remote from the first wafer 10.
The orthographic projection of the first wiring layer 43 on the first dielectric layer 412 covers the first conductive via structure, the orthographic projection of the second wiring layer 44 on the second dielectric layer 422 covers the second conductive via structure, and the first wiring layer 43 is electrically connected with the second wiring layer 44 through the female conductive via structure.
In some embodiments of the present disclosure, the second conductive via structure includes a second insulating layer 211 and a conductive metal, and the second wafer 20 has a second via, and inner and outer surfaces of the second insulating layer 211 are respectively in contact with the conductive metal and inner surfaces of the second via.
In some embodiments of the present disclosure, the conductive trace layer includes a second dielectric layer 422 and a second wiring layer 44;
the second dielectric layer 422 is disposed on a side of the second wafer 20 away from the first wafer 10, exposing the second conductive metal 212 in the second conductive via structure, and the second wiring layer 44 covers the second conductive metal 212 and covers a partial area of the second dielectric layer 422.
The same as in the above embodiment is not repeated here.
In some embodiments of the present disclosure, the at least one wafer further comprises a third wafer 30, the third wafer 30 comprising a third conductive via structure;
The third wafer 30 is located between the first wafer 10 and the second wafer 20 and is bonded to the first wafer 10 and the second wafer 20, and the third conductive via structure is electrically connected to the first conductive via structure and the second conductive via structure, respectively.
In one embodiment of the present disclosure, the package structure is composed of a first wafer 10 and a second wafer 20, the second wafer 20 also includes a conductive via structure, defined as a second conductive via structure 21, which is formed by the second conductive via structure 21 in a subsequent process. The female via structure is comprised of a first conductive via structure and a second conductive via structure.
In another embodiment of the present disclosure, the package structure includes at least one other wafer in addition to the first and second wafers 10, 20, the at least one other wafer including at least one other conductive via structure, and the mother via structure includes at least one other conductive via structure in addition to the first and second conductive via structures. At least one other wafer is located between the first wafer 10 and the second wafer 20, and the mother via structure is composed of a first conductive via structure, at least one other conductive via structure, and a second conductive via structure that extend therethrough.
Based on the same conception, a third aspect of the present disclosure provides an electronic device, including a package structure formed by the forming method according to any one of the embodiments of the first aspect.
It can be appreciated that, in one embodiment, the present disclosure can avoid via bottom filling holes caused by different deposition rates of conductive metal due to different electroplating current densities when manufacturing a high aspect ratio via structure by one-step molding.
Secondly, the manufacturing of the high-aspect-ratio mother through hole structure can be realized by respectively forming the first conductive through hole structure and the second conductive through hole structure with lower aspect ratios through the processes with lower process difficulty and lower cost, so that the manufacturing difficulty is reduced, and the yield of the silicon through hole is improved.
Third, the present disclosure can increase the current maximum aspect ratio of the through silicon via by multiple times as needed, depending on the need, by whether the third wafer 30 and more other wafers are formed.
It should be noted that, features disclosed in several forming methods or package structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.
The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure. Any person skilled in the art will readily recognize that changes or substitutions are within the technical scope of the present disclosure, and are intended to be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (20)
1. The method for forming the packaging structure is characterized by comprising the following steps:
providing a first wafer having opposite first and second sides;
forming a first conductive blind via structure in the first wafer, the first conductive blind via structure being exposed from the first face;
bonding at least one wafer including a second wafer on the first face, the second wafer having a third face facing the first face and a fourth face opposite the third face and including a second conductive blind via structure electrically connected to the first conductive blind via structure;
etching the second surface of the first wafer and the fourth surface of the second wafer respectively to expose the first conductive blind hole structure to form a first conductive through hole structure and expose the second conductive blind hole structure to form a second conductive through hole structure; wherein the first conductive via structure and the second conductive via structure form a female via structure penetrating the first wafer and the second wafer;
And forming conductive wiring layers on the second surface of the first wafer and the fourth surface of the second wafer respectively, wherein the conductive wiring layers are used for electrically connecting the female through hole structure.
2. The method of forming a package structure of claim 1, wherein forming a first conductive via structure on the first side of the first wafer comprises:
etching the first surface of the first wafer to form at least one first blind hole;
covering a first insulating layer on the first surface and the inner surface of the first blind hole;
and filling conductive metal in the first blind holes covered with the first insulating layer to form the first conductive blind hole structure.
3. The method of forming a package structure of claim 2, further comprising:
and thinning the first wafer from the second surface of the first wafer.
4. The method of forming a package structure of claim 1, further comprising:
providing a second wafer;
forming the second conductive blind via structure in the second wafer, the second conductive blind via structure emerging from the third face.
5. The method of forming a package structure of claim 4, wherein forming the second conductive via structure in the second wafer comprises:
etching the third surface of the second wafer to form at least one second blind hole;
covering a second insulating layer on the third surface and the inner surface of the second blind hole;
and filling conductive metal in the second blind holes covered with the second insulating layer to form the second conductive blind hole structure.
6. The method of forming a package structure of claim 5, further comprising:
and thinning the second wafer from the fourth surface of the second wafer.
7. The method of claim 1, wherein bonding at least one wafer including a second wafer on the first side of the first wafer comprises:
bonding a third wafer on the first surface of the first wafer, wherein the third wafer is provided with a fifth surface facing the first surface and a sixth surface opposite to the fifth surface, and comprises a third conductive through hole structure electrically connected with the first conductive blind hole structure;
And bonding the second wafer on one side of the third wafer far away from the first wafer, wherein the second conductive blind hole structure is electrically connected with the first conductive blind hole structure through the third conductive through hole structure.
8. The method of forming a package structure of claim 7, further comprising:
providing the third wafer;
and forming the third conductive through hole structure in the third wafer, wherein the third conductive through hole structure is exposed from a fifth surface and a sixth surface of the third wafer.
9. The method of forming a package structure of claim 8, wherein forming the third conductive via structure in the third wafer comprises:
forming a third conductive blind via structure in the third wafer, the third conductive blind via structure emerging from the fifth face;
etching the sixth surface of the third wafer to expose the third conductive blind hole structure;
and flattening the third wafer and the third conductive blind hole structure from the sixth surface of the third wafer to form the third conductive through hole structure.
10. The method of forming a package structure of claim 9, wherein forming a third conductive via structure in the third wafer comprises:
Etching the fifth surface of the third wafer to form at least one third blind hole;
covering the inner surfaces of the fifth surface and the third blind holes with a third insulating layer;
and filling conductive metal in the third blind hole covered with the third insulating layer to form the third conductive blind hole structure.
11. The method of forming a package structure according to claim 1, wherein forming conductive trace layers on the second surface of the first wafer and the fourth surface of the second wafer respectively includes:
forming a first dielectric layer on a second surface of the first wafer;
forming a second dielectric layer on a fourth surface of the second wafer;
forming a first wiring layer on the surface of one side, far away from the first wafer, of the first dielectric layer;
and forming a second wiring layer on the surface of one side of the second dielectric layer, which is far away from the second wafer.
12. The method of forming a package structure of claim 11, wherein forming a first dielectric layer on the second surface of the first wafer comprises:
forming a first dielectric material on a second surface of the first wafer, wherein the first dielectric material is covered on the first wafer and the first conductive blind hole structure;
And flattening the first dielectric material and the first conductive blind hole structure from the second surface of the first wafer, exposing the conductive metal in the first conductive blind hole structure and forming the first dielectric layer.
13. The method of forming a package structure of claim 11, wherein forming a second dielectric layer on a surface of the second wafer away from the first wafer comprises:
forming a second dielectric material on the surface of one side of the second wafer far away from the first wafer, wherein the second dielectric material is covered on the second wafer and the second conductive blind hole structure;
and flattening the second dielectric material and the second conductive blind hole structure from the fourth surface of the second wafer, exposing the conductive metal in the second conductive blind hole structure and forming the second dielectric layer.
14. A package structure, comprising:
a first wafer having opposite first and second sides, the first wafer including a first conductive via structure;
at least one wafer including a second wafer, located at one side of the first wafer and bonded to the first surface, the second wafer having a third surface facing the first surface and a fourth surface opposite to the third surface and including a second conductive via structure electrically connected to the first conductive via structure, the first conductive via structure and the second conductive via structure forming a through-going female via structure;
And the conductive wiring layer is respectively positioned on the second surface of the first wafer and the fourth surface of the second wafer and is electrically connected with the female through hole structure.
15. The package structure of claim 14, wherein the first conductive via structure comprises a first insulating layer and a conductive metal, the first wafer having a first via, the first insulating layer having inner and outer surfaces in contact with the conductive metal and the inner surface of the first via, respectively.
16. The package structure of claim 15, wherein the conductive trace layer comprises a first dielectric layer and a first wiring layer;
the first dielectric layer is covered on one side of the first wafer, which is far away from the second wafer, and exposes the conductive metal in the first conductive through hole structure, and the first wiring layer covers the conductive metal and covers a partial area of the first dielectric layer.
17. The package structure of claim 14, wherein the second conductive via structure comprises a second insulating layer and a conductive metal, the second wafer having a second via, the second insulating layer having inner and outer surfaces in contact with the conductive metal and the inner surface of the second via, respectively.
18. The package structure of claim 17, wherein the conductive trace layer comprises a second dielectric layer and a second wiring layer;
the second dielectric layer is covered on one side of the second wafer far away from the first wafer, the conductive metal in the second conductive through hole structure is exposed, and the second wiring layer covers the conductive metal and covers a partial area of the second dielectric layer.
19. The package structure of claim 14, wherein the at least one wafer further comprises a third wafer comprising a third conductive via structure;
the third wafer is located between the first wafer and the second wafer and is bonded with the first wafer and the second wafer respectively, and the third conductive through hole structure is electrically connected with the first conductive through hole structure and the second conductive through hole structure respectively.
20. An electronic device comprising a package formed by the method of any one of claims 1 to 13.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070045779A1 (en) * | 2005-09-01 | 2007-03-01 | Hiatt W M | Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure |
| CN102024782A (en) * | 2010-10-12 | 2011-04-20 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
| TW201216444A (en) * | 2008-05-13 | 2012-04-16 | Ind Tech Res Inst | Method for manufacturing three-dimensional stacking dice |
| CN102468284A (en) * | 2010-11-10 | 2012-05-23 | 中国科学院微电子研究所 | Stacked semiconductor device and method for manufacturing same |
| US9691733B1 (en) * | 2016-07-28 | 2017-06-27 | United Microelectronics Corp. | Bonded semiconductor structure and method for forming the same |
| CN107293515A (en) * | 2017-06-20 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of preparation method of TSV encapsulating structures and its prepared TSV encapsulating structures |
| CN112018096A (en) * | 2020-07-31 | 2020-12-01 | 复旦大学 | Nano-capacitor three-dimensional integrated system for energy buffering and preparation method thereof |
| CN112614807A (en) * | 2020-12-14 | 2021-04-06 | 长江存储科技有限责任公司 | Wafer bonding method and bonded wafer |
| CN113053806A (en) * | 2018-11-29 | 2021-06-29 | 长江存储科技有限责任公司 | Bonding structure and forming method thereof, wafer bonding structure and wafer bonding method |
| CN113066778A (en) * | 2021-03-23 | 2021-07-02 | 浙江集迈科微电子有限公司 | Interposer stacking structure and process |
| CN113380648A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Bonded semiconductor device and method for manufacturing the same |
| CN113990827A (en) * | 2021-10-28 | 2022-01-28 | 西安微电子技术研究所 | TSV back surface hole exposing structure and preparation method |
| CN114334805A (en) * | 2021-12-24 | 2022-04-12 | 华进半导体封装先导技术研发中心有限公司 | Heat dissipation interconnection forming method for 3D packaging |
| US20220399310A1 (en) * | 2021-06-11 | 2022-12-15 | Intel Corporation | Hybrid manufacturing with modified via-last process |
-
2023
- 2023-03-07 CN CN202310210873.4A patent/CN116072607A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070045779A1 (en) * | 2005-09-01 | 2007-03-01 | Hiatt W M | Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure |
| TW201216444A (en) * | 2008-05-13 | 2012-04-16 | Ind Tech Res Inst | Method for manufacturing three-dimensional stacking dice |
| CN102024782A (en) * | 2010-10-12 | 2011-04-20 | 北京大学 | Three-dimensional vertical interconnecting structure and manufacturing method thereof |
| CN102468284A (en) * | 2010-11-10 | 2012-05-23 | 中国科学院微电子研究所 | Stacked semiconductor device and method for manufacturing same |
| US9691733B1 (en) * | 2016-07-28 | 2017-06-27 | United Microelectronics Corp. | Bonded semiconductor structure and method for forming the same |
| CN107293515A (en) * | 2017-06-20 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of preparation method of TSV encapsulating structures and its prepared TSV encapsulating structures |
| CN113053806A (en) * | 2018-11-29 | 2021-06-29 | 长江存储科技有限责任公司 | Bonding structure and forming method thereof, wafer bonding structure and wafer bonding method |
| CN112018096A (en) * | 2020-07-31 | 2020-12-01 | 复旦大学 | Nano-capacitor three-dimensional integrated system for energy buffering and preparation method thereof |
| CN112614807A (en) * | 2020-12-14 | 2021-04-06 | 长江存储科技有限责任公司 | Wafer bonding method and bonded wafer |
| CN113066778A (en) * | 2021-03-23 | 2021-07-02 | 浙江集迈科微电子有限公司 | Interposer stacking structure and process |
| CN113380648A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Bonded semiconductor device and method for manufacturing the same |
| US20220399310A1 (en) * | 2021-06-11 | 2022-12-15 | Intel Corporation | Hybrid manufacturing with modified via-last process |
| CN113990827A (en) * | 2021-10-28 | 2022-01-28 | 西安微电子技术研究所 | TSV back surface hole exposing structure and preparation method |
| CN114334805A (en) * | 2021-12-24 | 2022-04-12 | 华进半导体封装先导技术研发中心有限公司 | Heat dissipation interconnection forming method for 3D packaging |
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