TW201216374A - Method for producing oxide semiconductor thin film, and oxide semiconductor from the said method, thin film transistor and device with thin film transistor produced - Google Patents

Method for producing oxide semiconductor thin film, and oxide semiconductor from the said method, thin film transistor and device with thin film transistor produced Download PDF

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TW201216374A
TW201216374A TW100130215A TW100130215A TW201216374A TW 201216374 A TW201216374 A TW 201216374A TW 100130215 A TW100130215 A TW 100130215A TW 100130215 A TW100130215 A TW 100130215A TW 201216374 A TW201216374 A TW 201216374A
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film
oxide semiconductor
thin film
heat treatment
resistivity
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TWI518791B (en
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Masahiro Takata
Fumihiko Mochizuki
Takeshi Hama
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Fujifilm Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

An IGZO-based oxide thin film, which does not result in low resistance due to annealing and has high reproducibility, is provided. It is suitable for manufacturing the device with extensive area, especially the flexible device. This application comprises a film-forming process for forming the oxide semiconductor thin film which satisfies In, Ga, Zn and O as main constituent elements, the composition ratios of 11/20 ≤ Ga/(In+Ga+Zn) ≤ 9/10, 3/4 ≤ Ga/(In+Ga) ≤ 1 and Zn/(In+Ga+Zn) ≤ 1/3, and a heat treatment process of heat-treating the film-formed oxide semiconductor thin film at 100 DEG C or more and 300 DEG C or less in an oxidizing environment. The film-forming condition of the film-forming process and the heat treatment condition of the heat treatment process are set to the resistivity of the oxide semiconductor thin film after the heat treatment process which is 1 Ω cm or more and 1*10<SP>6</SP> Ω cm or less.

Description

201216374 六、發明說明： 【發明所屬之技術領域】 本發明係關於氧化物半導體薄膜 物半導體薄膜，以及具備氧化物半導 體。又’本發明係關於具備薄膜電晶 像感測器及X射線感測器等之裝置。 【先前技術】 近年來’將In — Ga— Ζη— Ο系（ 物半導體薄膜使用在通道層的薄膜電 行（專利文獻1〜5等）。由於氧化物 溫成膜，且呈現比非晶矽還高的移動 目光呈透明，故可在塑膠板或薄膜等 的透明薄膜電晶體。 在專利文獻1〜4中，從各種觀點 的組成比之較佳範圍。 專利文獻5中報告在將氧化物半 (通道層）的TFT中，移動率或ON 因在於活性層所含有之水分量不同。 專利文獻5中，規定在將具備 TFT實用化時，在實用上不成問題的4 另一方面’在一般的認知上， 質氧化物半導體薄膜適用於薄膜電晶 以350。(：〜4〇〇。〇左右的後續退火處理 性（臨界值移位等）。 [先前技術文獻] 之製造方法及氧化 體薄膜的薄犋電晶 體的顯示裝置、影 IGZ0系）的氧化 晶體之開發極為盛 半導體薄膜係可低 率，並且相對於可 之基板上形成撓性 分別規定IGZ〇系 導體使用在活性層 • OFF比的變動原 ft化物半導體層白勺 〔分取入量之上限。 要將IGZO系非晶 體之際，有必要施 以改善元件的穩定 -4- 201216374 [專利文獻] [專利文獻1 ]特許第4 1 7 0 4 5 4號公報 [專利文獻2 ]特開2 0 0 7 — 2 8 1 4 0 9號公報 [專利文獻3]特表2009 - 533884號公報 [專利文獻4]特開2009 — 253204號公報 [專利文獻5]特開2〇〇8_ 283〇46號公報 【發明内容】 [發明所欲解決之課題j 現在’由於對在耐熱性低的樹脂基板上形成有薄膜 電晶體（TFT )的撓性TFT之需求高漲，故有關在成膜 後為改善電氣特性所進行之後續退火處理方面，被要求 以樹脂基板等所能承受300t以下之較低的退火溫度達 成特性改善。又，亦有裝置的大面積化之要求要求大 面積具有均一的電氣特性之氧化物半導體薄膜而得以大 面積形成特性均一的TFT。 然而，一般的 而驟然地引 的氧分壓設 獲得具有半 度極為敏感 特性仍會大 面積裝置的 法獲得具均 本發明 楚IGZO系 發低電 成極南 導體領 ，所以 不相同 情況， 一特性 係有鑒 氧化物 導體膜。 引起低電 但電阻率 數它的差 特別是在 退火溫度 者，目的 低溫退火 阻化，難以用作半 ’即使在低溫退火 域的電阻率的膜， 即便退火溫度僅有 而使再現性不佳， 會有所s胃因面内的 的裝置之問題。 於上述事情而完成 半導體薄膜中不因 退火處理 將成膜時 阻化亦可 對退火溫 異，電氣 欲形成大 不均而無 在於弄清 而引發低 201216374 2阻2且成膜時的電阻值和低溫退火後的電阻值可成 為同等之組成，提供—種 .商八制你 檀再現性咼，適合製作大面積裝 疋性裝置的1GZ〇系氧化物薄膜之製造方 又本赉明之目的在於提供一種面内之特性不均情 Z兄少的薄冑電晶體及具備薄膜電晶冑之裝置。 [解決課題之手段] 本發月者係發現藉由採用Ga組成比高於—般所用 督IGZ。材=之IGZ〇膜，可極力抑制低溫退火前後的 3〇ϋ率變化^ °又’發現若低溫退火時之退火溫度為 以下的範圍’則就算退火溫度有些許變化，退火後 絮電阻率仍會與退火前的電阻率同等。本發明係依據彼 專的知識見解而完成者。 八本發明的氧化物半導體薄膜之製造方法之特徵為包 :.成臈滿足以In、Ga、Ζη Α 〇作為主要構成元素、 :且成比為 ll/2〇SGa/(In + Ga + Zn)^9/1〇、且 3/4^Ga/ = + Ga)y、且Zn/(In + Ga+Zn)g1/3的氧化物半導體薄 、之成膜步驟；及在氧化性環境t對前述氧化物半導體 =膜施作3G()t:以下的熱處理之熱處理步 :，且以前述熱處理步驟後之前述氧化物半導體薄膜的 :阻率成為mcm以上lxl〇hcm以下的方式設定前述 成膜步驟中之成膜條件及前述熱處理步驟中之熱處理 條件。 在此，所說的「主要構成元素」是意味著，In、Ga、 乙η、0的總和對總構成元素的比例是98%以上。又，斤 塊電阻率係設成在室溫（20°C )下的電阻率。 201216374 「氧化性環境」係意味著包含氧、臭氧、 等之環境。 $ 較佳為’前述成膜步驟中，係進一步成獏滿足 組成比為3/4SGa/(In + Ga)各9/1〇者以作為前述 導體薄膜。 千 此外，本說明書中所謂的成膜步驟係指包含在薄膜 形成後為控制膜的電阻率而因應需求制所施作的處理 (但熱處理除外）’所謂的前述成膜條件係指包含膜 時的條件和因應該需求所對膜施作的處理之條件。' / 又’所S胃刖述熱處理條件，呈辦而_&gt; 什/、體而g係指熱處理溫 度、熱處理環境及處理時間等。 前述熱處理的溫度較佳為設成10(rc以上200它以 下。 較佳為，前述熱處理步驟前之前述氧化物半導 膜的電阻率係與該熱處理步驟後之電阻率同等。 在此’所明的「同等」係指當設熱處理步驟前的電 阻率為Pa，設熱處理步驟後的電阻率為…時，兩電阻率 的關係為0.1paSpb$ l〇Pa者。 較佳為’前述成膜步驟中，兹士 _ 輝甲糟由濺鍍方式成膜前述 氧化物半導體薄膜。 本發明的氧化物半導體薄膜俜换 肤你刼用本發明的氧化物 半導體薄膜之製造方法所製作之以In、Ga、z“ 0為 主要構成元素的氧化物半導體薄膜，其特徵為：滿足組 成比為 n/2(^Ga/(In+Ga+Zn)g9/1()、且 3/4❿心+叫 y、且zn/(In+Ga+Zn)y/3且電阻率為以上 201216374 1 χ 1 〇6Qcm 以下。 本發明的薄膜電晶體係於基板上具有活性層、源極 電極、汲極電極、閘極絶緣膜及間極電極的薄膜電晶體， 其特徵為：前述活性層是由本發明的氧化物半導體薄膜 所構成者。 本發明的薄膜電晶體係以前述基板是具可撓性者較 佳。 本發明的顯示裝置之特徵為具備本發明的薄膜電晶 體。 本發明影像感測器之特徵為具備本發明的薄膜電晶 體。 本發明的X射線感測器之特徵為具備本發明的薄膜 電晶體。 ' [發明效果] 依據本發明的氧化物半導體薄膜之製造方法，係成 膜滿足以In、Ga、Zn及0作為主要構成元素、組成比 為 ll/20SGa/(In + Ga+Zn)S9/l〇、且 3/4 各 Ga/(In + Ga) ^卜且Zn/(In + Ga + Zn)S 1/3的氧化物半導體薄膜，此組 成比的半導體薄膜在之後的熱處理步驟中不會驟然地引 發低電阻化，可容易大面積地形成具均一的電阻率之氧 化物半導體薄膜。亦即，依據本發明之製造方法，藉由 成膜已控制組成的IGZO系氧化物半導體薄膜且施行低 溫退火處理，可獲得不受退火溫度不均之影響而呈再現 性、大面積之均一性優異的氧化物半導體薄膜。 以往所知的一般組成比In:Ga:Zn=1:la的IGz〇氧 -8 - 201216374 化物半導體薄膜，其電阻率會因為在 退火時之溫度不均而產生大的變化， 所期望之電阻率的氧化物半導201216374 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an oxide semiconductor thin film semiconductor thin film and an oxide semiconductor. Further, the present invention relates to a device including a thin film electrophotographic image sensor, an X-ray sensor, and the like. [Prior Art] In recent years, 'In-G- Ζ — Ο ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 物 物 物 物 物 物 物 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( The high-visible moving eye is transparent, so it can be used as a transparent film transistor such as a plastic plate or a film. In Patent Documents 1 to 4, a composition ratio from various viewpoints is preferable. Patent Document 5 reports that an oxide is used. In the TFT of the half (channel layer), the mobility or the ON is different depending on the amount of water contained in the active layer. Patent Document 5 specifies that when the TFT is used, it is practically not problematic. In general, the oxide semiconductor film is suitable for thin film electrowinning at 350 (.: 4 〇〇 后续 的 的 subsequent annealing treatment (threshold shift, etc.) [Previous Technical Literature] Manufacturing method and oxidation The development of an oxide crystal of a thin film transistor of a bulk film, and an oxidized crystal of a shadow IGZ0 system is extremely low, and the IGZ lanthanide conductor is defined separately for the flexibility formed on the substrate. In the active layer • OFF ratio, the original ft-semiconductor layer is changed. [The upper limit of the amount of the FTZO semiconductor layer is required. In order to make the IGZO amorphous, it is necessary to improve the stability of the component. -4-201216374 [Patent Document] [Patent [Patent Document 1] Japanese Patent Laid-Open No. Hei. No. Hei. No. Hei. No. 2009-533884 [Patent Document 3] [Patent Document 5] Japanese Unexamined Patent Application Publication No. Publication No. Publication No. JP-A------ The demand for flexible TFTs for thin film transistors (TFTs) is increasing, so that it is required to achieve a lower annealing temperature of 300 t or less with a resin substrate or the like in order to perform subsequent annealing treatment for improving electrical characteristics after film formation. In addition, there is also a requirement for a large-area device to require a large-area oxide semiconductor film having uniform electrical characteristics to form a TFT having a uniform characteristic over a large area. However, a general and sudden introduction of oxygen partial pressure is obtained. With half The extremely sensitive characteristic is still obtained by the method of large-area device. The IGZO system of the present invention has a low-voltage southern pole conductor, so unlike the case, one characteristic is an oxide conductor film. The difference is especially in the annealing temperature, the purpose of low temperature annealing is resistant, it is difficult to use as a thin film of the resistivity even in the low temperature annealing domain, even if the annealing temperature is only so that the reproducibility is not good, there will be s The problem of the device in the surface. In the semiconductor film, the resistance of the semiconductor film is not affected by the annealing treatment, but the annealing temperature can be different, and the electrical desire to form a large unevenness is not caused by the clarification and the low 201216374 2 resistance. 2 and the resistance value at the time of film formation and the resistance value after low-temperature annealing can be an equivalent composition, providing a kind of 1GZ lanthanide oxide film which is suitable for making a large-area mounting device. The purpose of the manufacturer is to provide a thin tantalum transistor with in-plane characteristics and inconsistent Z-brothers and a device having a thin film transistor. [Means for Solving the Problem] This month's people found that the IGZ was used by using a composition ratio higher than Ga. IGZ 〇 film can suppress the change of 3 〇ϋ rate before and after low temperature annealing ^ ° and 'if the annealing temperature in the low temperature annealing is the following range', even if the annealing temperature changes slightly, the flocculation resistivity after annealing It will be equivalent to the resistivity before annealing. The present invention has been completed in accordance with the knowledge of the subject. The method for producing an oxide semiconductor thin film according to the present invention is characterized in that: 臈 is satisfied with In, Ga, Ζη Α 〇 as main constituent elements, and the ratio is ll/2〇SGa/(In + Ga + Zn ^9/1〇, and 3/4^Ga/ = + Ga)y, and Zn/(In + Ga+Zn)g1/3 of the oxide semiconductor is thin, the film formation step; and in the oxidizing environment t The heat treatment step of heat treatment of the above-mentioned oxide semiconductor film is performed at a temperature of 3 G (g) or less, and the above-mentioned oxide semiconductor film after the heat treatment step is set to have a resistivity of mcm or more and lxl〇hcm or less. The film forming conditions in the film step and the heat treatment conditions in the aforementioned heat treatment step. Here, the term "main constituent element" means that the ratio of the sum of In, Ga, B, and 0 to the total constituent element is 98% or more. Further, the bulk resistivity is set to a specific resistance at room temperature (20 ° C). 201216374 "Oxidative environment" means an environment containing oxygen, ozone, and the like. In the film forming step, it is preferable that the composition film has a composition ratio of 3/4 SSG/(In + Ga) of 9/1 Å as the conductor film. Further, the film formation step in the present specification refers to a treatment which is applied to the resistivity of the control film after the formation of the film and is applied according to the demand (except for the heat treatment). The so-called film formation condition means that the film is contained. The conditions and conditions for the treatment of the membrane applied as required. ' / ‘ s S stomach description of heat treatment conditions, and _ &gt; / / body and g refers to heat treatment temperature, heat treatment environment and treatment time. The temperature of the heat treatment is preferably set to 10 (rc or more and 200 or less. Preferably, the electrical resistivity of the oxide semiconductive film before the heat treatment step is equivalent to the electrical resistivity after the heat treatment step. The term "equivalent" means that when the resistivity before the heat treatment step is Pa and the resistivity after the heat treatment step is ..., the relationship between the two resistivities is 0.1 PaSpb $ l 〇 Pa. Preferably, the film formation is as described above. In the step, the oxide semiconductor thin film is formed by sputtering. The oxide semiconductor thin film of the present invention is in the form of In, which is produced by the method for producing the oxide semiconductor thin film of the present invention. Ga, z "0 is an oxide semiconductor thin film which is a main constituent element, and is characterized by satisfying a composition ratio of n/2 (^Ga/(In+Ga+Zn)g9/1(), and 3/4❿心+叫y, and zn / (In + Ga + Zn) y / 3 and the resistivity is above 201216374 1 χ 1 〇 6Qcm or less. The thin film electro-crystalline system of the present invention has an active layer, a source electrode, a drain electrode, and a thin film transistor of a gate insulating film and an interlayer electrode, characterized in that: the active layer The thin film electrowinning system of the present invention is preferably one in which the substrate is flexible. The display device of the present invention is characterized by comprising the thin film transistor of the present invention. The X-ray sensor of the present invention is characterized by comprising the thin film transistor of the present invention. [Effect of the Invention] The method for producing an oxide semiconductor thin film according to the present invention is The film formation satisfies In, Ga, Zn, and 0 as main constituent elements, and the composition ratio is ll/20SGa/(In + Ga+Zn)S9/l〇, and 3/4 each Ga/(In + Ga) Zn/(In + Ga + Zn)S 1/3 oxide semiconductor film, the semiconductor film of this composition ratio does not suddenly cause low resistance in the subsequent heat treatment step, and can easily form a uniform resistance over a large area. The oxide semiconductor film of the present invention, that is, by the film-forming method of the IGZO-based oxide semiconductor film having a controlled composition and subjected to a low-temperature annealing treatment, it is possible to reproduce without being affected by the unevenness of the annealing temperature. Sex, An oxide semiconductor thin film having excellent uniformity in area. The conventionally known IGz〇oxy-8 - 201216374 semiconductor thin film having a composition ratio of In:Ga:Zn=1:la has a resistivity which is not due to the temperature at the time of annealing. a large change in the desired resistivity of the oxide semiconducting

In:Ga:Zn=1:1:1 的組成比之 IGz〇 膜 ^ 施行退火之際驟然地產生低電阻化， 火/m度極為敏感，所以即便是退火溫 即無法再現，又，在退火時面内有溫 成在面内產生電氣特性不均。The composition ratio of In:Ga:Zn=1:1:1 is slightly lower than that of the IGz〇 film. When the annealing is performed, the fire/m degree is extremely sensitive, so even if the annealing temperature is not reproducible, it is annealed. In the time surface, Wencheng produces uneven electrical characteristics in the surface.

In:Ga:Zn=1:1:1的氧化物半導體薄膜 尚/皿下的退火處理。然而，當高溫退火 則基板或電極材料、絶緣膜材料之材 低。 另—方面’依據本發明之製造方 下的熱處理作成面内的電氣特性均一 等之材料選擇幅度，特別是若熱處理 下’則能採用耐熱性低的樹脂基板， 置。 採用有藉本發明之製造方法獲得 膜之薄膜電晶體可作成大面積具有均 【貫施方式】 以下’針對本發明的氧化物半； 法、薄膜電晶體及具備薄膜電晶體之 說明》 &lt;氧化物半導體薄膜之製造方法&gt; 藉由本發明的氧化物半導體薄膜 3 0 0 °C以下的低溫 所以難以獲得具有 體薄膜。亦即， E 3 0 0 °C以下的低溫 由於其電阻值對退 度稍有差異，特性 度不均的情況，造 因此以往在使用 之情況是施作在更 -處理成為必要時， 料選擇幅度顯著降 法，能以300°C以 者，故能增大基板 溫度設成200°C以 容易應用於撓性裝 的氧化物半導體薄 一特性者。 葶體薄膜之製造方 裝置的實施形態作 之製造方法所製造 201216374 .係以In、Ga、Zn及 體薄膜，滿足組成比 ΟIn: Ga: Zn = 1:1:1 oxide semiconductor film Annealing under the dish. However, when annealing at a high temperature, the material of the substrate or the electrode material or the insulating film material is low. On the other hand, according to the heat treatment in the manufacturing process of the present invention, the material selection width of the electric properties in the plane is uniform, and in particular, when the heat treatment is performed, a resin substrate having low heat resistance can be used. The thin film transistor obtained by the manufacturing method of the present invention can be formed into a large area with the same method. [The following description of the oxide half of the present invention; the method, the thin film transistor, and the thin film transistor] &lt; (Manufacturing Method of Oxide Semiconductor Thin Film) It is difficult to obtain a bulk thin film by the low temperature of the oxide semiconductor thin film of the present invention at 30 ° C or lower. In other words, when the temperature is lower than E 3 0 0 °C, the resistance value is slightly different from the degree of retreat, and the characteristic degree is not uniform. Therefore, in the past, the use is performed when more processing is necessary. The amplitude is significantly reduced, and it can be used at 300 ° C. Therefore, it is possible to increase the substrate temperature to 200 ° C to easily apply it to the thin oxide semiconductor. The manufacturing method of the apparatus for manufacturing a thin film is manufactured by the manufacturing method of the apparatus. 201216374 . The composition ratio is satisfied by In, Ga, Zn and a bulk film.

之氧化物半導體薄膜之特徵為 為主要構成元素的氧化物半導 ll/20^Ga/(In + Ga + Zn)^9/l〇 , ^ 3/4 ^ Ga/(In + Ga) ^ 1 ^ 且Zn/(In + Ga + Zn)S1/3且在室溫（20。〇的電阻率是 ΙΩοηι 以上 1 X 1 Ο6 〇 n m 、. 以下的IGZO膜。更佳為 3/4SGa/(In + Ga)$9/l〇 〇 氧化物半導體溥膜係以非晶質者較佳。若為非晶質 膜，則容易大面積形成均一的膜，由於不存在像多結晶 的粒界，故容易抑制元件特性的不均。 氧化物半V體層是否為非晶質，可利用χ射線繞射 J定來確 &lt; 亦即在藉由x射線繞射測定未檢出呈現結 晶構造的明確峰值之情況，彳判斷其氧化物半導體層是 非晶質。 者 此外，在此，薄膜係指 1 n m以上 1 Ομηι以下程度 本發明的氧化物半導體薄膜之製造方法之特徵為包 含：成膜滿足以In、Ga、Ζη及〇作為主要構成元素、 組成比為 ll/2〇SGa/(In + Ga + Zn)g9/l〇、且 3/4gGa/ (In + Ga) g 1、且Zn/(In+Ga+Zn) ^ 1/3的氧化物半導體薄 膜之f膜步驟；及在氧化性環境中對該成膜的氧化物半 導體薄膜施作1〇0它以上3〇〇〇C以下的熱處理之熱處理步 驟，且以熱處理步驟後之氧化物半導體薄膜在室溫下的 電阻率成為lQcni以上ixiohcm以下的方式設定成膜 步驟中之成膜條件及熱處理步驟中之熱處理條件。 茲說明本發明之具體的氧化物半導體薄膜之製造方 -10- 201216374 法。 (成膜步驟） 氧化物半導體薄膜之成膜’例如可使用濺錢法。 在成膜步驟中採用濺鍍法成膜滿足以In、Ga、Zn 及 〇作為主要構成元素、組成比為ll/20g.Ga/ (In + Ga + Zn)^9/10、且 3/4 S Ga/(In + Ga) $ 1 、且 Zn/ (In + Ga + Zn)$ 1/3的氧化物半導體薄膜之方法方面，可以 疋所成膜之IGZO膜中的in，Ga，Zn組成比能成為如上述 fe圍那樣的複合氧化物標靶之單獨濺鍍，亦可以是In、 Ga、Zn ’或者，彼等的氧化物或組合彼等的複合氧化物 標靶作使用的共濺鍍《共濺鍍的情況為，調整投入於標 靶的電力比’藉以調整組成比。 利用濺鍍法之成膜的成膜條件為，例如，將成膜時 之成膜至内的壓力設成〇4Pa，成膜室内的氧分壓設成 5xl(T4Pa來進行。 上述 低溫退火 壓，變得 於是 任意地控 的氧分壓 時之成膜 壓之手法 法，亦可 若提高氧 &amp;双靶固的IGZ0膜，由於成膜後的電阻率和 後的電阻率同等，所以藉由調整成膜時的氧分 能任意地選擇低溫退火後的電阻率。 為了 k制所獲得之膜的電阻率（導電率），係 制成膜時之成膜室内的氧分壓。此外，成膜時 ，在5 X 1 0 Pa以下，因應所期望的組成及成膜 室内的壓力作&gt; ' 刀作控制。作為控制成膜室内的氧分The oxide semiconductor thin film is characterized by an oxide semiconducting element which is a main constituent element ll / 20 ^ Ga / (In + Ga + Zn) ^ 9 / l 〇, ^ 3 / 4 ^ Ga / (In + Ga) ^ 1 ^ and Zn/(In + Ga + Zn)S1/3 at room temperature (20. The resistivity of 〇 is ΙΩοηι or more 1 X 1 Ο6 〇nm , IGZO film below. More preferably 3/4SGa/(In + Ga) $9/l 〇〇 oxide semiconductor ruthenium film is preferably amorphous. If it is an amorphous film, it is easy to form a uniform film over a large area, and it is easy because there is no grain boundary like polycrystal. Suppression of the unevenness of the characteristics of the element. Whether the oxide half V body layer is amorphous or not, can be determined by the X-ray diffraction J, which is determined by the x-ray diffraction measurement, and the clear peak of the crystal structure is not detected. In the case where the oxide semiconductor layer is amorphous, the film is referred to as 1 nm or more and 1 Ομηι or less. The method for producing an oxide semiconductor thin film of the present invention is characterized in that the film formation satisfies In, Ga, Ζη, and 〇 are the main constituent elements, and the composition ratio is ll/2〇SGa/(In + Ga + Zn)g9/l〇, and 3/4gGa/(In + Ga) g 1 , and Zn/ (In+Ga+Zn) ^ 1/3 of the oxide film of the oxide semiconductor film; and in the oxidizing environment, the oxide semiconductor film formed is 1 〇 0 or more and 3 〇〇〇 C or less In the heat treatment step of the heat treatment, the film formation conditions in the film formation step and the heat treatment conditions in the heat treatment step are set such that the resistivity of the oxide semiconductor film after the heat treatment step is at least ixiohcm or less at room temperature. The specific oxide semiconductor thin film is manufactured by the method of -10-201216374. (film formation step) The film formation of the oxide semiconductor film 'for example, a sputtering method can be used. In the film formation step, the film formation by sputtering is satisfied. Ga, Zn, and yttrium are the main constituent elements, and the composition ratio is ll/20 g.Ga/(In + Ga + Zn)^9/10, and 3/4 S Ga/(In + Ga) $ 1 , and Zn/ (In + Ga + Zn) $ 1/3 of the oxide semiconductor thin film method, the composition ratio of in, Ga, and Zn in the IGZO film formed can be a composite oxide target as described above Individual sputtering, it can also be In, Ga, Zn 'or their oxides or combinations The common oxide target is used for co-sputtering. In the case of co-sputtering, the ratio of the power input to the target is adjusted to adjust the composition ratio. The film formation conditions by the sputtering method are, for example, The pressure at the time of film formation at the time of film formation was set to 〇4 Pa, and the partial pressure of oxygen in the film formation chamber was set to 5x1 (T4Pa). The above-mentioned low-temperature annealing pressure is a method of forming a film pressure at an arbitrarily controlled partial pressure of oxygen, and it is also possible to increase the resistivity of the oxygen-amplified double-targeted IGZ0 film due to the film formation and the subsequent resistivity. Since it is equivalent, the electrical resistivity after low-temperature annealing can be arbitrarily selected by adjusting the oxygen content at the time of film formation. The specific resistance (conductivity) of the film obtained by k is the partial pressure of oxygen in the film forming chamber at the time of film formation. In addition, at the time of film formation, it is controlled by a knife according to the desired composition and the pressure in the film forming chamber at 5 X 1 0 Pa or less. As a control of oxygen in the film forming chamber

，亦可為變化篡λ +人L 文化導入於成膜室内的02氣體量之方 為變化氧自由基、臭氧氣體的導入量之方法。 刀【貝“b降低氧化物半導體薄膜的導電率， 201216374 若降低氧分壓，則使膜中的氧缺陷增加而能提高氧化物 半導體薄膜的導電率。 此外，在即使是停止導入氧氣的情況電阻仍高的情 況’亦可導入h2或n2等之還原性氣體，以增加膜中的 氧缺陷。 又’成膜中的基板温度亦可因應基板而任意地選 擇’但在使用撓性基板的情況，基板溫度以較接近室溫 者為宜。 (熱處理步驟） 熱處理步驟（後續退火處理步驟）是在1 〇〇&lt;^以上 3〇〇°c以下進行。作為形成薄膜的基板，在是使用樹脂基 板等之耐熱性低的可撓性基板之情況，以設成100。〇以 上200 C以下較佳。若為1〇〇〇c以上3〇〇。〇以下，則未使 膜中的氧缺扣量變化’因而退火前後的膜之電阻率變化 變小。若為1〇〇t以上2〇〇。〇以下，則容易適用於耐熱性 低的樹脂基板。 熱處理時間倒無特別限定，但考虞 需的時間[至少保肖1〇分鐘以上較佳 退火處理中的壤境設成氧化性環境較佳。特 在大氣中退火則生连屮士 士， . 產成本亦低，故更佳。當在還原性 ^ ^ ^ 氣化物+導體中的氧會脫落而 生過剩載體，退火步驟前後 ^ B 又J电阻年之變化量容县掸 而谷易引起電氣特性不均， 易増 9 故不如所期。 本發明的重點在於.义 壤瞪士 、.發現在1GZO系氧化物 薄膜中’低溫退火時之電 物+導 电丨且羊變化極小的組成領 201216374 艮 p ， &gt; 4、'且成範圍成獏的IGZO膜幾乎沒有在低溫退 ^ 电低電阻化（伴隨加熱而低電阻化，並在降溫時 :持其低電阻化後的電阻率之狀態）的情況，低溫退火 月」後之電阻率的變化量非常小。所謂的低溫退火前後電 P且率變4卜I , ,, 九 ^ 小’幾乎未受因退火溫度之差異所影響，係 “未著^要在成膜時成膜具任意的電阻率之IGZO膜， 則犯在未精密地控制退火溫度之下，獲得退火後具有所 』望=電阻率之IGZ〇膜，電氣特性的設計變容易。又， 別疋在形成大面積裝置之際，以均一的退火溫度對大 積施作熱處理非常困難，但無需精密控制退火溫度， 因而肊利用較簡便的退火裝置獲得具有均一的電氣特性 之5化物半導體薄膜。由於能以低溫退火形成裝置，所 望此使製以成本降低，且亦能朝向耐熱性低的樹脂基板 形成’故容易應用於撓性裝置。 如同上述，依據本發明的IGZO系氧化物半導體薄 1 la方法可抑制製作成本，可獲得在低溫退火後電 二*之面内均—性非常高的氧化物半導體薄膜，這樣 夕導體薄膜有助於作為適用大面積裝置的薄膜電晶體 之活性層。 &lt;薄膜電晶體&gt; 圖」（）至（D)係顯示本發明之第i〜第4實施 广、的溥膜電晶體i〜4之構成的示意剖面圖。在圖丄 符號）。（D )的各溥膜電晶體中，共通的要素賦與相同 本發明的實施形態之薄膜電晶體卜4係在基板u -13- 1 3、汲極電極1 4、 在活性層1 2方面， 膜。 201216374 上具有活性層1 2、源極電極 緣膜1 5及閘極電極1 6而成， 述之本發明的氧化物半導體薄 圖1 ( A )所示的第1實施形態之薄膜電晶體 閘極：頂接觸型的電晶體’圖1 ( B )所示的第2 態之薄膜電晶Μ 2係頂閘極—底接觸型的電晶體 (C )所7F的帛3實施形態之薄膜電晶體3係底 頂接觸型的電晶體，圖UD)所示的第4實施形 膜電晶體4係底閘極-底接觸型的電晶體。 圖1 ( A)〜（D )所示的實施形態中閘極、 及極電極之對氧化物+ #體層&amp;西己置雖+同，但 相同符號的各要素之機能係相同，可適應同樣的 以下’針對各構成要素進行詳述。 (基板） 有關用以形成薄膜電晶體1的基板11之形法 及大小等並無特別限制，可因應目的作適當選擇 的構造可為單層構造，亦可為積層構造。 作為基板11，例如，可使用由YSZ (釔安定 或玻璃等之無機材料、樹脂或樹脂複合材料等構 板。 . 其中考量輕量及具可撓性時，以由樹脂或樹 材料所構成的基板較佳。具體而f，可使用由聚 甲I丁 —酯、聚對笨二曱酸乙二酯、聚萘二曱酸2 聚對萘一曱酸丁二酯、聚苯乙烯、聚碳酸酯、聚 _砸*聚芳香g旨、稀丙基二甘醇碳酸醋、聚醯 閘極，絶 備有上 1係頂 實施形 ’圖1 閘極 態之薄 源極和 被賦予 材料。 I、構造 。基板 .化錯） 成的基 脂複合 對笨二 j —酉旨、 砜、聚 :、聚醯 -14- 201216374 亞胺、聚醯胺醯亞胺、聚醚醯亞胺'聚笨.、取 + 承本石瓦鍵' 多環烯烴、㈣稀樹脂、聚三氟氯乙稀等之氣樹脂、液 晶聚合物、丙烯酸樹脂、環氧樹脂、聚矽氧樹脂、離= 聚合物樹脂、氰酸酯樹脂、交聯反丁烯二酸二醋、環狀 聚烯烴、芳香族醚、馬來醯亞胺一環烯、纖維素、 硫化物化合物等之合成樹脂所構成的基板、由已提及之 合成樹脂等和氧化矽粒子之複合塑膠材料所構成的= 板、由已提及之合成樹脂等和金屬奈米粒子、無機氧二 物奈米粒子或無機氮化物奈米粒+等之複合塑膠材料所 構成的基板、由已提及之合成樹料和碳纖維或奈米碳 管之複合塑膠材料所構成的基板、由已提及之合成樹脂 等和玻璃碎片、玻璃纖維或玻璃珠之複合塑膠材料所構 成的基板、由已提及之合成樹脂等和具有黏土礦物或雲 母何生結晶構造的粒子之複合塑膠材料所構成的基板、 在薄玻璃和已提及之任一合成樹脂之間具有至少丄次的 接合界面之積層塑膠基板、藉由交互地積層無機層和有 機層（已提及之合成樹脂）而具有至少有1次以上的接 合界面之障壁性能的複合材料所構成的基板、將不鏽鋼 基板或不錄鋼和異種金屬積層所成的金屬多層基板、鋁 土板或表面虼以氧化處理（例如陽極氧化處理）而提升 表面、、色緣性之帶有氧化皮膜的鋁基板等。 此外，作為樹脂基板，係以耐熱性、尺寸穩定性、 耐溶劑性、雷維绝认 ， 、、色緣性、加工性、低通氣性，及低吸濕性 等優異者較佳。 于月曰基板亦可具備用以防止水分、氧透過的氣體障 -15- 201216374 壁層或用以提升樹脂基板的平坦性或與下部電極之密接 性的底塗層等。 又’基板的厚度係50μηι以上5〇〇μηι以下較佳。基 板的厚度為50μηι以上時，基板自體的平坦性更提升。 基板的厚度為5〇〇μηι以下時’基板自體的可撓性更提 升’作為撓性裝置用基板來使用更為容易。此外，由於 具有充分的平坦性及可撓性的厚度是依構成基板的材料 而異故有必要因應基板材料來設定其厚度，該範圍大 約在 5〇μηι — 500μπι。 (活性層） ^在活性層12方面，備有以本發明之製造方法製造的 氧化物半‘體薄膜（以下’稱為氧化物半導體層1 2。）。 亦Ρ氧化物半導體層12滿足以In、Ga、Ζη及0作為 主要構成元素、其組成比為u/2〇SGa/(in + Ga + Zn) WIG、且 3/GGa/(In + Ga⑷、且 Zn/(in + Ga + Zngi/3 且在室溫（2(TC)的電阻率是以上ιμ()6ω⑽以下 的IGZO膜。 氧化物半導體層 時間的觀點而言，以 氧化物半導體層 專來進行。 1 2的膜厚從薄膜的平坦性及成膜 5nm以上1 50nm以下者較佳。 1 2之成膜係如同上述可利用濺鍍 (源極-汲極電極） 只要源極電極]1 ,'tL ^ ^ 。电極14皆為具有高導雷神 者即可，並盔特別卩ρ μ , 八令同等電性 丁· J 將 Al、Mo、Cr、Ta 'It is also possible to change the amount of oxygen gas and ozone gas introduced by changing the amount of 02 gas introduced into the film forming chamber by the change 篡λ + human L culture. The knife "b" reduces the conductivity of the oxide semiconductor film, 201216374 If the oxygen partial pressure is lowered, the oxygen deficiency in the film is increased to increase the conductivity of the oxide semiconductor film. Further, even if the introduction of oxygen is stopped When the resistance is still high, a reducing gas such as h2 or n2 may be introduced to increase the oxygen deficiency in the film. Further, the substrate temperature in the film formation may be arbitrarily selected depending on the substrate, but in the case of using a flexible substrate. In other cases, the substrate temperature is preferably closer to room temperature. (Heat treatment step) The heat treatment step (subsequent annealing treatment step) is performed at 1 〇〇 &lt;^ or more and 3 〇〇 ° C or less. As a substrate for forming a film, In the case of using a flexible substrate having a low heat resistance such as a resin substrate, it is preferably 100. Preferably, 〇 is 200 C or more. If it is 1 〇〇〇 c or more, 3 〇〇 is less than 〇. The change in the amount of oxygen deficiency is changed, so that the change in the resistivity of the film before and after the annealing is small. When it is 1 〇〇 t or more and 2 〇〇 or less, it is easily applied to a resin substrate having low heat resistance. The heat treatment time is not particularly limited. However, the time required for the test is at least 1 minute or more. The soil in the better annealing treatment is better in the oxidizing environment. It is especially suitable for annealing in the atmosphere, and the production cost is also low. Preferably, when the oxygen in the reducing ^ ^ ^ vapor compound + conductor will fall off and the excess carrier is generated, the change of the electric resistance of the B and the electric resistance is measured before and after the annealing step, and the electric property is uneven, and the electric property is uneven. Therefore, it is not as expected. The focus of the present invention is on the Yigang gentleman. It is found that in the 1GZO-based oxide film, the electric material + conductive enthalpy during low-temperature annealing and the change of the sheep is extremely small 201216374 艮p , &gt; 4 The IGZO film having a range of enthalpy is hardly decompressed at a low temperature (low resistance with heating, and reduced in temperature: in the state of resistivity after low resistance), low temperature annealing The amount of change in resistivity after the month is very small. The so-called low-temperature annealing before and after the electric P and the rate change 4 I, ,, 九 ^ small 'almost unaffected by the difference in annealing temperature, is "not to be formed at the time of film formation, the film has an arbitrary resistivity of IGZO The film is made under the uncontrolled annealing temperature, and the IGZ film with the desired resistivity after annealing is obtained, and the design of electrical characteristics becomes easy. Moreover, when forming a large-area device, uniformity is achieved. The annealing temperature is very difficult to heat-treat the large product, but it is not necessary to precisely control the annealing temperature. Therefore, a simple semiconductor device is used to obtain a semiconductor film having uniform electrical characteristics. Since the device can be formed by low-temperature annealing, it is expected The IGZO-based oxide semiconductor thin 1 la method according to the present invention can be easily reduced in cost and can be obtained at a low temperature, because it can be formed in a resin substrate having a low heat resistance and can be easily formed. An oxide semiconductor film having a very high uniformity in the surface of the second layer after annealing, so that the dielectric film can contribute to the activity of a thin film transistor suitable for a large-area device. &lt;Thin Film Transistor&gt; Figs. (A) to (D) are schematic cross-sectional views showing the structures of the yttrium film transistors i to 4 which are widely used in the ith to fourth embodiments of the present invention. In the figure 丄 symbol). In each of the ruthenium film transistors of (D), the common elements are the same as the thin film transistor 4 of the embodiment of the present invention, and the substrate u-13-13, the drain electrode 14 and the active layer 1 2 , membrane. In 201216374, the active layer 12, the source electrode edge film 15 and the gate electrode 16 are formed, and the thin film transistor gate of the first embodiment shown in Fig. 1 (A) of the oxide semiconductor of the present invention is described. Pole: top contact type transistor 'Fig. 1 (B) shows the second state of the thin film transistor 系 2 is the top gate-bottom contact type transistor (C) 7F of the 帛3 embodiment of the thin film The crystal 3 is a bottom contact type transistor, and the fourth embodiment of the film transistor 4 shown in FIG. UD) is a bottom gate-bottom contact type transistor. In the embodiment shown in Fig. 1 (A) to (D), the gate electrode and the electrode of the electrode and the electrode layer of the electrode are the same as the same, but the functions of the elements of the same symbol are the same and can be adapted. The same as the following 'detailed each component. (Substrate) The shape, size, and the like of the substrate 11 for forming the thin film transistor 1 are not particularly limited, and a structure which can be appropriately selected depending on the purpose may be a single layer structure or a laminated structure. As the substrate 11, for example, an inorganic material such as yttrium or glass or the like, a resin or a resin composite material can be used. Among them, when it is lightweight and flexible, it is composed of a resin or a tree material. The substrate is preferably. Specifically, f can be used, such as polymethyl butyl acrylate, polyethylene terephthalate, polynaphthalene dibutyl phthalate, polystyrene, polycarbonate Ester, poly-砸* poly-aromatic g, dipropyl diglycol carbonate vinegar, polythene ruthenium, and the upper 1 series top-form implementation of the thin source of the gate state and the material to be given. , structure. Substrate. False-based compounding of the base grease, stupid, sulfone, poly:, polyfluorene-14-201216374 imine, polyamidimide, polyetherimine ., take + bearing stone tile key 'polycyclic olefin, (four) thin resin, polychlorotrifluoroethylene and other gas resin, liquid crystal polymer, acrylic resin, epoxy resin, polyoxyn resin, ion = polymer resin , cyanate resin, cross-linked fumaric acid diacetate, cyclic polyolefin, aromatic ether, maleimine monocycloolefin, cellulose, a substrate composed of a synthetic resin such as a sulfide compound, a composite plate composed of a synthetic resin such as a synthetic resin and cerium oxide particles, a synthetic resin or the like, and a metal nanoparticle or inorganic oxygen A substrate composed of a composite plastic material such as a binary nanoparticle or an inorganic nitride nanoparticle +, a substrate composed of a composite plastic material and a composite plastic material of carbon fiber or carbon nanotube, as mentioned a substrate composed of a composite plastic material such as a synthetic resin or the like, glass shards, glass fibers or glass beads, a composite plastic material composed of a synthetic resin or the like, and particles having a clay mineral or a mica crystal structure. a laminated plastic substrate having at least a plurality of bonding interfaces between the thin glass and any of the synthetic resins mentioned, having at least 1 by alternately laminating an inorganic layer and an organic layer (the synthetic resin already mentioned) a substrate composed of a composite material having a barrier property of a joint interface or more, a metal multilayer formed by laminating a stainless steel substrate or a non-recorded steel and a dissimilar metal layer Plate, aluminum plate or surface earth oxide flea treatment (e.g. anodic oxidation) while lifting the edge of the surface of the aluminum substrate ,, color with an oxide film and the like. Further, the resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, Levi's ignorance, color rim property, workability, low air permeability, and low moisture absorption. The substrate may also be provided with a gas barrier for preventing moisture and oxygen from permeating. -15- 201216374 A wall layer or an undercoat layer for improving the flatness of the resin substrate or the adhesion to the lower electrode. Further, the thickness of the substrate is preferably 50 μm or more and 5 μm or less. When the thickness of the substrate is 50 μm or more, the flatness of the substrate itself is further improved. When the thickness of the substrate is 5 〇〇μηι or less, the flexibility of the substrate itself is increased. It is easier to use as a substrate for a flexible device. Further, since the thickness having sufficient flatness and flexibility is different depending on the material constituting the substrate, it is necessary to set the thickness in accordance with the substrate material, and the range is about 5 〇 μη - 500 μm. (Active Layer) ^ In the active layer 12, an oxide semi-body film (hereinafter referred to as an oxide semiconductor layer 12) produced by the production method of the present invention is provided. Further, the oxide semiconductor layer 12 satisfies In, Ga, Ζη, and 0 as main constituent elements, and has a composition ratio of u/2〇SGa/(in + Ga + Zn) WIG and 3/GGa/(In + Ga(4), And Zn/(in + Ga + Zngi/3 and an IGZO film having a resistivity of 2 (TC) at a room temperature (2 (TC) is ωμ() 6 ω (10) or less. From the viewpoint of oxide semiconductor layer time, the oxide semiconductor layer is specialized The film thickness of 1 2 is preferably from the flatness of the film and the film formation of 5 nm or more and 150 nm or less. The film formation of 1 2 is as described above for sputtering (source-drain electrode) as long as the source electrode] 1 , 'tL ^ ^. The electrodes 14 are all high-conducting Raytheon, and the helmet is especially 卩ρ μ, eight equal electrical D · J will be Al, Mo, Cr, Ta '

Ti、Au、Ag等之金屬，Al_Ti, Au, Ag, etc., Al_

Nd，Ag合金，氧化錫，氧 201216374 化辞，氧化銦，氧化銦錫（IT〇)，氧化鋅錮（ιζ〇)等 之金屬氧化物導電膜等作為單層或2層以上的積層構造 來使用。 源極電極13和汲極電極14均能依據考慮到與例如 方式、塗布方式等之濕式方式、真空蒸鍍法、藏鑛 法、離子電鍍法等之物理方式、CVD、電漿CVD法等之 化予方式等中所使用的材料之適應性所適當選擇的方法 進行成膜。 在以上述金屬構成源極電極1 3和沒極電極1 4的情 況，當考慮到基於成膜性、蝕刻或掀離（lift 〇ff)法的圖 案化I1生及導電性等時，其厚度設成l0nm以上l〇〇〇nma 下較佳，设成50nm以上1 〇〇nm以下更佳。 (閘極絶緣膜） 作為閘極絶緣膜丨5，以具有高絶緣性者較佳，例如 I 由 si〇2、SiNx、Si0N ' Αΐ2〇3、Υ2〇3、Ta2〇5、町〇2 寺之絶緣膜’ A至少含有2個以上彼等的化合物之絶緣 膜等所構成。 閘極絶緣膜1 5係可依考慮與印刷方式、塗布方式等 之濕式方式、真空蒸鍍法、濺鍍法、離子電鍍法等之物 理方式、CVD、電漿CVD法等之化學方式等中使用的材 料之適應性所適當選擇的方法來進行成膜。 此外，為降低漏電流及提升耐電壓性，閘極絶緣膜 15需要具有足夠的厚度’但另一方面，厚度過大則會招 致驅動電壓上昇。閘極絶緣膜15的厚度係因材質而異， 但以10nm〜ΙΟμιη較佳，5〇nm〜 1〇〇〇nm更佳，〜 201216374 4 0 0nm特佳。 (閘極電極） 在間極電極1 6方面，只要是具有高導電性者即可， 並無特別限制，例如可將A卜Mo、Cr、Ta、Ti、An ' Ag等之金屬、A1— Nd、Ag合金、氧化錫、氧化鋅、氧 化叙I、氧化銦錫（ΙΤ〇 )、氧化辞銦（IZ〇 )等之金屬氧 化物導電膜等作為單層或2層以上的積層構造來使用。 問極電極1 6係可依考慮與例如印刷方式、塗布方式 等之濕式方式、真空蒸鍍法、濺鍍法、離子電鍍法等之 物理方式、CVD、電漿CVD法等之化學方式等中使用的 材料之適應性所適當選擇的方法來進行成膜。 利用上述金屬構成閘極電極1 6的情況，當考慮到成 膜性、基於蝕刻或掀離（Hft_〇ff)&amp;的圖案化性及導電性 專夺/、厚度a又成1 〇nm以上1 〇〇〇nm以下敕佳，設成 術m以上200nm以下更佳。 &lt;薄膜電晶體之製造方法&gt; 錄針對圖1 ( A )所不的頂閘極-頂接觸 晶體1之製造方法作簡單說明。 準備基S 1卜利肖已提及之濺鍍法等其 板η上成膜屬活性層的氧化物半導體薄膜η。此乃相 =〇提：之：發明的氧化物半導體薄獏之製造方法中 的IGZO膜之成膜步驟。 其次將氧化物半導體層12圖荦化。 刻及敍刻方式進行。且體而〜上：圖案化係採用光 J具體而s ，在殘存的邱八別田氺釗 形成光阻圖案’利用鹽酸、硝酸、稀访酸 柿碌酸、或磷酸、硝 -18- 201216374 酸及乙酸的混合液等之酸溶液進行蝕刻而形。 此外，在氧化物半導體層12上，可於源極、汲極電 極钮刻時形成用以保護氧化物半導體層的㈣^㈣ 膜亦可和氧化物半導體層進行連 半導體層之圖案化後形成。編亦可在氧化物 接著，在氧化物半導體層1 2 --極電極13、14的金屬膜層2之上形成用以形成源極 規-2 Γ金屬M利用#刻或掀離（肋蝴法圖案化成 規疋的形狀，形成源極電極13和汲極電極…此時， 以同^將源極-汲極電極13、14及與彼等的電極（ 不）連接之配線圖案化者較佳。 %緣=成沒極電極13、14及配線後，形成閘極 規开膜广再針對間極絶緣膜15’利用光刻及钮刻進行 規疋形狀之圖案化。 膜成：ΓΓ絶緣膜15後，形成閘極電極16。電極 护狀= 刻或掀離（lift-off)法圖案化成規定的 =極T極…6。此時，以同時將間極… 及閘極配線圓案化較佳。 (後續退火） 後續ΐ 1’ ： a極圖案化後實施熱處理(後續退火處理）。 ^、处理若是在氧化物半導 序上倒盈特別pp ^ 千導-層12成膜之後，則程 杆，介寺別限疋’可在氧化物半導體成膜後隨即進 進行:、Ιί電極、絶緣膜的成膜、圖案化全部結束後再 導體薄：：製：後續退火步驟也只有已提及之氧化物半 201216374 後績退火溫度係在1 〇 〇。〇以上3 〇 〇 行，當考慮使用可撓性基板的情況時，X下的條件下進 且20CTC以下進行更佳。若為1〇〇〇c 乂在1〇〇&lt;3以上 上3 0 0 °C以下，由 於以有讓膜中的氧缺損量變化的情形，、 的電阻率變化變小。若為1〇〇aC以上故退火别後之膜 用於耐熱性低的樹脂基板。 C以下則谷易適 又’後續退火中的環境設成.氧化 „ 12· %境較佳。堂友 還原性環境中施行後續退火時，氧彳 礼化物半導體層中 會脫落而產生過剩載體，容易引起雷# 丨篼罨軋特性不均。 透過以上的程序可製作圖1 ( A 1邮- 、A )所不的薄膜電晶體 本發明的薄膜電晶體之用途倒無特 合於作為電氣光學裝置的顯示裂置（置 有機 EL ( E1 ectro Luminescence ) 別限定，例如適 例如液晶顯示裝 顯示裝置、無機 EL顯示裝置等） 中的驅動元件 均一性高，故適合於大面積裝置。 。特別是由於特性的面内 再者，本發明的薄膜電晶體係使用Ga組成比高於 一般IGZO材料的IGZO膜，因而光學能帶間隙較寬， 其結果係能使可見光的短波長域（例如4〇〇nm左右）之 光吸收降低，所以無需在電晶體設置遮光手段，生產處 理間便’且能將EL發光有效率地取出。 再者，本發明的薄膜電晶體係可適用在採用有樹脂 基板且能以低溫處理製作的撓性顯示器等之裝置、CCD (Charge Coupled Device)' CM〇S( Complementary Metal Oxide Semiconductor)等之影像感測器、x射線感測器 -20- 201216374 4之各種感測器、mems i iu. ^ Micro Electro Mechanicala metal oxide conductive film such as Nd, Ag alloy, tin oxide, oxygen 201216374, indium oxide, indium tin oxide (IT〇), zinc oxide bismuth (ITO), or the like, as a single layer or a laminated structure of two or more layers use. The source electrode 13 and the drain electrode 14 can be based on a physical method such as a wet method such as a method or a coating method, a vacuum vapor deposition method, a mining method, an ion plating method, or the like, a CVD method, a plasma CVD method, or the like. The film is formed by a method appropriately selected for the suitability of the material used in the method and the like. In the case where the source electrode 13 and the electrodeless electrode 14 are made of the above metal, the thickness is considered in consideration of patterning I1 growth and conductivity based on film formation, etching or lift-off method. It is preferable to set it as l0 nm or more and l〇〇〇nma, and it is more preferable to set it as 50 nm or more and 1 〇〇 nm or less. (Gate Insulation Film) As the gate insulating film 丨5, it is preferable to have high insulation, for example, I consists of si〇2, SiNx, SiONO' Αΐ2〇3, Υ2〇3, Ta2〇5, and Machi 2 Temple. The insulating film 'A' is composed of an insulating film containing at least two or more of the compounds. The gate insulating film 15 can be selected from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as a CVD method or a plasma CVD method, or the like. The film is prepared by a method appropriately selected for the suitability of the material used. Further, in order to reduce leakage current and improve withstand voltage, the gate insulating film 15 needs to have a sufficient thickness ', but on the other hand, if the thickness is too large, the driving voltage rises. The thickness of the gate insulating film 15 varies depending on the material, but is preferably 10 nm to ΙΟμηη, more preferably 5 〇 nm to 1 〇〇〇 nm, and particularly preferably 201216374 4 0 0 nm. (Gate Electrode) The inter-electrode electrode 16 is not particularly limited as long as it has high conductivity. For example, a metal such as A, Mo, Cr, Ta, Ti, An 'Ag, or the like may be used. A metal oxide conductive film such as Nd, an Ag alloy, tin oxide, zinc oxide, oxidized I, indium tin oxide, or indium oxide (IZ) is used as a single layer or a laminated structure of two or more layers. . The polarity electrode 16 can be considered, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as a CVD method or a plasma CVD method, or the like. The film is prepared by a method appropriately selected for the suitability of the material used. In the case where the gate electrode 16 is formed of the above-mentioned metal, film formation property, patterning property based on etching or detachment (Hft_〇ff) &amplitude, conductivity specificity, and thickness a become 1 〇 nm. The above 1 〇〇〇 nm or less is better, and it is better to set it to m or more and 200 nm or less. &lt;Manufacturing Method of Thin Film Transistor&gt; The manufacturing method of the top gate-top contact crystal 1 which is not shown in Fig. 1 (A) will be briefly described. The oxide semiconductor thin film η which is an active layer of the film formation on the plate η such as the sputtering method which has been mentioned by the base S1 Blishaw is prepared. This is the phase: step: the film formation step of the IGZO film in the method for producing an oxide semiconductor thin film of the invention. Next, the oxide semiconductor layer 12 is patterned. Engraved and narrated. And the body ~ ~: the patterning system uses light J specific and s, in the remaining Qiu Ba Bian Tian, the formation of a photoresist pattern 'utilizing hydrochloric acid, nitric acid, dilute acid persimmon acid, or phosphoric acid, nitrate-18-201216374 acid and An acid solution such as a mixed solution of acetic acid is etched to form. Further, on the oxide semiconductor layer 12, a (four)^(4) film which is formed to protect the oxide semiconductor layer when the source and the drain electrode are formed may be formed by patterning the semiconductor layer with the oxide semiconductor layer. . The embossing may also be formed on the metal film layer 2 of the oxide semiconductor layer 1 2 -electrode 13, 14 to form a source gauge - 2 Γ metal M utilizing #刻刻掀The pattern is patterned into a regular shape, and the source electrode 13 and the drain electrode are formed. In this case, the wiring pattern is connected to the source-drain electrodes 13 and 14 and the electrodes (not). Preferably, the % edge = the electrodeless electrodes 13, 14 and the wiring are formed, and the gate electrode is formed into a wide film, and then the pattern of the regular shape is patterned by photolithography and button etching for the interlayer insulating film 15'. After the film 15, the gate electrode 16 is formed. The electrode protection pattern = patterning or lift-off method is patterned into a predetermined = pole T pole ... 6. At this time, at the same time, the interpole ... and the gate wiring are rounded up. It is better. (Subsequent annealing) Subsequent ΐ 1' : After a patterning of the a pole, heat treatment (subsequent annealing treatment) is performed. ^, If the treatment is inverted on the oxide semi-guide, especially pp ^ 1000 - layer 12 after film formation , then the process rod, the temple is limited to 疋' can be carried out immediately after the formation of the oxide semiconductor film: Ιί electrode, film formation of the insulating film, After the completion of the case, the conductor is thin:: The subsequent annealing step is only the oxide half of the 201216374 post-annealing temperature is 1 〇〇. 〇 above 3 ,, when considering the use of flexible substrates In the case of X, the conditions under X are better than 20 CTC. If 1〇〇〇c 乂 is 1〇〇&lt;3 or more above 300 °C, the amount of oxygen deficiency in the film is allowed. In the case of a change, the change in resistivity becomes small. If it is 1 〇〇 aC or more, the film after annealing is used for a resin substrate having low heat resistance. Below C, the environment of the subsequent annealing is set to . 12% is better. When the subsequent annealing is performed in the reducing environment of the buddy, the oxygen rafting semiconductor layer will fall off and generate excess carrier, which may cause unevenness in the rolling characteristics of the ray # 。. Fig. 1 (A1 mail-, A). The use of the thin film transistor of the present invention is not particularly suitable for display cracking as an electro-optical device (E1 ectro Luminescence), for example, Suitable for example, LCD display display The driving element in the inorganic EL display device or the like has high uniformity, so it is suitable for a large-area device. Especially, due to the in-plane characteristics of the present invention, the thin film electro-crystalline system of the present invention uses a Ga composition ratio higher than that of a general IGZO material. The IGZO film has a wide optical band gap, and as a result, the light absorption in the short wavelength range of visible light (for example, about 4 〇〇 nm) is reduced, so that it is not necessary to provide a light shielding means in the transistor, and the production process is The EL light-emitting system of the present invention can be efficiently taken out. The thin-film electro-crystal system of the present invention can be applied to a device such as a flexible display having a resin substrate and capable of being processed at a low temperature, or a CCD (Charge Coupled Device) CM〇S. (Complementary Metal Oxide Semiconductor) and other image sensors, x-ray sensors -20- 201216374 4 various sensors, mems i iu. ^ Micro Electro Mechanical

System )等各種電子# ^ 、置中的驅動元件（驅動電路）。 採用有本發明的薄膜雷a 内，目,丨哭仏寻膜電日日體之本發明的顯示裝置及 性」，在顯示裂置的情·兄”二。此外’此處所說的「特 指感度特性。 顯示特性，感測器的情況是 &lt;液晶顯示裝置&gt; 圖2中係顯示有關本發明 的液晶顯示裝晋夕* ^、員不裝置之-實施形態 氣配線的概略構成圖。 略d面圖’圖3顯示其電 圖1 ( A)所戶;：’本實施形態的液晶顯示裝置5係具備 1的保護頂二極型的薄膜電晶體卜在被電晶體 55及其對向上 電極16上被畫素下部電極 上。P電極5 6包夾沾、.★ n e r。 各畫素而發出 、液日日層57、及用以對應 ®不同色的RGB、、磨土 板11側及濾色$ w , v 4色器58，且TFT10的基 匕态5 8上分別且规 又，如圖 八備偏光板59a、59b的構成。System ^ and other electronic # ^, centering drive components (driver circuits). In the case of the film of the present invention, the display device and the property of the present invention are used to display the film, and the display device and the property of the present invention are displayed. In the case of the sensor, the sensor is a liquid crystal display device. Figure 3 shows the electric diagram 1 (A);: 'The liquid crystal display device 5 of the present embodiment is provided with a protective top dipole type thin film transistor in the transistor 55 and its The upper electrode 16 is on the lower electrode of the pixel. The P electrode is covered with a pinch, and the φ. Each pixel is emitted, the liquid layer 57, and the RGB, the ground plate for the corresponding color. 11 side and color filter $ w, v 4 color device 58, and the base state 5 of the TFT 10 is separately and regularly arranged as shown in FIG.

N J所不，太杂大A 具備相互平彳_ m &amp;屯態的液晶顯示裝置5係 ^ T之複數條閘極S? μ &amp; '、 父又之相互承/ Ί 5 1、及與遠閘極配線$ 1 -穴士丨 卞4丁的資料配線52 . 1L Ba , 舅料配線5) / 。在此，閘極配線5 1和 係電氣絶緣。在pq Λ 之交又部附〗 3極配線5 1和資料配線52 _ 叹備有薄膜電晶體 缚膜電晶舯,^ 1。 aa體1的閘極柄； &gt;專膜電晶體] 5 ° 16連接於閘極配線5 1， P 1的源極電極1 3 1 a 溥膜電晶骼， ^ 13連接於資料配線52。又， 1的沒極電極14 4 的接觸孔19 (導雷、經由設置在閘極絶緣膜 租里入於接觸孔19)而連接於晝 •iivf -2 素下部電 電極56 - 在圖 成具備頂 置即液晶 可為底閘 本發 靠性非常 又，由於 可製作具 作為基板 示裝置。 201216374 ^ 55。此晝素下部電極55係 _起構成電容器53。 … 2及圖3略_ 間極型的：：之本實施形態的液 :的缚膜電晶體者，但在本發q &quot; 所用的薄膜電晶體不限為 極型的薄膜電晶體。 j的4膜電晶體由於面内均_性、希 门所以適合於液晶顯示裝置中的&gt; 本發明的薄膜電晶體藉由在低溫下合 有充分特，Η：去·，u t Γ生者故可使用樹脂基板（ ，能提供大㈣、均-、穩定且撓,, &lt; X射線感測器&gt; 圖4中係顯示有關本發明的感測器之一實 射線感測器之一部分的概略剖面圖，圖5顯 線的概略構成圖。 更具體言之，圖4传γ 4+ 保Χ射線感測器陣列的 之概略剖面圖。本實絲丑彡能&amp; ν 頁狍形態的X射線感測器γ 具備有形成在基板上的薄骐電晶體^及電容器 在電容器70上的電荷收集用電極7卜X射線變 以及上部電極73。在薄膜電晶體1上設有保讀 電容器70係成為以電容器用下部電極76 用上部電㈣包爽絶緣膜78而成的構造。電 部電極77係經由設置在絶緣膜η的接觸孔乃 電晶體1的源極電極13和汲極電極14當中任 ^地的對向 :置中雖作 丨的顯示震 丨極型，亦 ;定性及可 晝面化。 退火處理 塾膠基板） 的液晶顯 形態的X 其電氣配 部分放大 係建構成 7〇、形成 換層72、 膜75。 和電容器 容器用上 而與薄膜 一方（圖 -22- 201216374 4中為汲極電極1 4 )連接。 電荷收集用電極7 1係設在電容器70中的電容器用 上部電極77上，與電容器用上部電極77相接觸。 X射線變換層72係由非晶質硒構成的層，且設置成 覆蓋薄膜電晶體1及電容器70。 上部電極73係設在X射線變換層72上，與X射線 變換層72相接觸。 如圖5所示，本實施形態的X射線感測器7係具備 相互平行之複數條閘極配線8 1、及與閘極配線8 1交叉 之相互平行的複數條資料配線82。在此，閘極配線8 1 和資料配線8 2係電氣絶緣。在閘極配線8 1和資料配線 82之交叉部附近備有薄膜電晶體1。 薄膜電晶體1的閘極電極16連接於閘極配線8 1， 薄膜電晶體1的源極電極1 3連接於資料配線82。又， 薄膜電晶體 1的汲極電極 1 4連接於電荷收集用電極 7 1，然後此電荷收集用電極71係連同接地的對向電極 76 —起構成電容器70。 在本構成的X射線感測器7中，X射線在圖4中， 從上部（上部電極73側）照射，在X射線變換層72生 成電子-電洞對。藉由上部電極73對此X射線變換層72 施加高電場，使所生成的電荷蓄積於電容器70，藉由依 序掃描薄膜電晶體1而被讀出。 本發明的X射線感測器係具備面内均一性高、可靠 性優異的薄膜電晶體1，因而能獲得均一性優異的圖像。 此外，在圖4所示之本實施形態的X射線感測器 -23- 201216374 中 測 底 者，但本發明的感 頂閘極型，亦可為 雖作成具備頂閘極型的薄膜電晶體 盗中所用的》專膜電晶體並未限定為 閘極型的薄膜電晶體。 [實施例] 試 成 行 針對氧化物半導體薄膜 料並進行電氣特性之測定 範圍的氧化物半導體薄膜 TFT特性的評估。 ，作成實施例、比較例的各 且’製作具備本發明之組 之薄膜電晶體的實施例，進 〈驗證實驗i : In_Ga t匕改變後的脱〇膜之原位 In-situ )電氣測定〉 ' 膜 料 化 膜 作 料 板 比 罩 氧- 針對In、Ga組成比不同的氧化物半導體薄膜⑽z〇 )之退火溫度和電氣特性的關係，製作如同以下的試 並進行評估。 作為電阻測定用試料，係在基板上將規定大小之氧 物半導體薄膜以後述的各實施例、比較例的條件成 ，製作出在其上形成有電極者。 '參照圖6及目7，針對電阻測定用試料的製作方法 ' 囷6 7中为別（A )是俯視圖，（B )是剖面圖。 、作為基板100，係使用合成石英玻璃基板（科發倫材 司製口口零件號T-4040，1英吋匚| x i mmt)，於該基 100上將氧化物半導體薄膜101以後述的各實施例、 較例的2件濺鍍成膜所製作出。在成膜之際採用金屬 於1英叫□基板100上成膜3mmx9inm的圖案狀之 丨匕物半導體薄膜1〇1 (參照圖6)。 成膜係以知用In2〇3標靶、Ga203標靶及ZnO標靶 -24- 201216374 的共減:鍍（co-sputter)之方式來進行，組成比的調整係藉 由變化投入於各標靶的電力比來進行。 在所獲得之氧化物半導體薄膜1 〇 1上利用濺錄方式 將電極102成膜。電極1〇2係作成由Ti和Au之積層膜 所構成者。在氧化物半導體薄膜i 0丨上將Ti成膜1 〇nm 後’將Au成膜40nm而作成電極102。藉由在電極成膜 中亦使用金屬罩進行圖案成膜而形成4端子電極（參照 圖7 )。 (實施例1 ) 在實施例1方面，利用以下的濺鍍成膜條件成膜作 為氧化物半導體薄膜的IGZ0膜。 陽離子組成比 In: Ga:Zn = 0.2:1.8 :1.0 膜厚 5 Onm 成膜室到達真空度 6M(T6Pa 成膜時壓力 A r 流量 3 0 s c c m 〇2 流置· Osccm θ在實施例2、比較例1〜4方面，製作出陽離子組成 是不同於實〜例丨@ IGZC)膜。此外，由於當陽離子 組成比-變化時，會使膜的初期電 :較載體量:2故調整成膜時的氧流量，使膜的：二 ?收斂在10〜10 + 5Ω_的範圍内。在此，初期電阻率 ^刀期值）係指在熱處理前之在室溫（20。〇的電阻率。 :!广實施例、比較例的成膜條件，陽離子組成比及氧 机里（2流量）顯示如下。如同上述，成膜係以.採用In2〇3 -25- 201216374 払靶Ga2〇3標靶及Zn〇標靶的共濺鍍之方 ，來進仃，且變化投入於各標靶的電力比以形成各組成 比。其他條件係與實施例1相同 (實施例2) 實施例2中之氧化物半導體薄膜的成膜條件如 所示。 陽離子組成比 In: Ga:Zn= 0.4:1.6:1.0 〇2 流量 Osccm (比較例1 ) 比較例1中之氧化物半導體薄膜的成膜條件係如下 所示。 陽離子組成比 In:Ga:Zn=0.5:1.5:1.〇 流量 Osccm (比較例2) 比較例2中之氧化物半導體薄膜的成膜條件係如下 所示。 陽離子組成比In:Ga:Zn = 〇.8:1 1 〇 〇2 流量 O.lsccm (比較例3) 比較例3中之氧化物半導护箨 干导虹溥膜的成膜條件係如下 所示。 陽離子組成比IiKGiZi^m Q:1 〇 〇 2 流量 〇. 1 5 s c c m (比較例4) 比較例4中之氧化物半導體薄 守朕的或膜條件係如下 -26- 201216374 所示。 陽離子組成比 In:Ga:Zn=1.5:〇.5:l.〇 〇 2 流量 0.4 5 s c c m &lt;電阻率的溫度變化測定&gt; 關於上述6種試料（實施例1、2、比較例1〜4 )， 可控制環境，且一邊作熱處理一邊設定在可進行電阻測 定之裝置上，測定了在昇溫-降溫過程之電阻率的變化。 腔至内的環境係設成 Ar 160sccm，〇2 40sccm，且以 l〇°C/min昇溫至200°C，在20(TC下保持10分鐘後，藉 爐冷方式進行冷卻迄至成為室溫為止。 實施例1、2及比較例1〜4之昇溫-降溫過程之溫度 和電阻率的關係顯示於圖8。 如圖8所示，可知熱處理前的電阻率和熱處理後的 電阻率之差會隨著Ga組成比減少、In組成比增加而變 大。如同實施例1、2，很清楚的是在Zn/(In + Ga + Zn) = 1/3 時，若4/5 gGa/(In + Ga)則熱處理後的膜之電阻率會和熱 處理則的電阻率同等。在此所說的同等係指將熱處理步 驟後的電阻率作成Pb之際，熱處理步驟前的電阻率h “進到0_lpaSpb$l〇pa的範圍（以下相同。）。一方面， 確認了比較例1〜4在昇溫過程時會驟然地引起低電阻 化，之後，在降溫過程中電阻率亦未回復成熱處理前的 值，熱處理前後的電阻率變化大。 在製造大面積的半導體薄膜之情況，難以將面内全 域的溫度均-地保持’—般會在退火之際產生面内溫度 不均。如比較你&quot;〜4 ’在電阻值伴隨溫度上昇而變化且 -27- 201216374 在溫度下降後未回復成溫度上昇前的電阻值之情况，依 面内的溫度不均，會在面内產生電阻值不均亦即電氣特 性不均。相對i也，如實施例i及2，於昇溫_降溫過：中 幾乎無電阻值經歷的情況，就算在退火時面内發生溫度 不均，仍無導致面内的電氣特性不均的情形，可說== 獲得電氣特性之面内均一性高的半導體薄膜。 此 〈驗也貫驗2 . Zn組成比不同的IGZ〇膜之原位 (Ιη-situ)電氣特性測定&gt; ” 接著針對Zn組成比不同的IGz〇膜之後續退火溫度 和電氣特性的關係’與驗證實驗1同樣地製作電阻測； 用試料，進行電阻率的溫度變化測定並作評估。 以下述實施例3' 4及比較例5、6的濺鍍條件製作 IGZO膜’作為電阻測定用試料。 ^各=施例、比較例的濺鍍條件中所未記載的條件係 設成與實施例1之電阻測定用試料的製作方法相同，電 I1且率的Μ度變化測定方法及條件係作成與驗證實驗1相 同。 (實施例3 ) κ鼽例3中之氧化物半導體薄膜的成膜條件係如下 所示。 陽離子组成比In:Ga:Zn= 〇.2:1ι8:〇 〇2 流量 Osccm (實施例4 ) 一實％例4中之氧化物半導體薄膜的成膜條件係如下 所示。 -28- 201216374 陽離子組成比 I n: G a: Ζ η = 0 · 2:1. 8 :0.5 〇 2 流量 〇 s c c m (比較例5) 比較例5中之氧化物半導體薄膜的成膜條件 所示。 陽離子組成比 In:Ga:Zn = 0.2:1.8:2.0 〇2 流量 〇.〇3sccm (比較例6) 比較例6中之氧化物半導體薄膜的成膜條件 所示。 陽離子組成比 In:Ga:Zn = 0.2:1.8:3.5 〇 2 流量 〇 . 1 s c c m 針對上述試料（實施例3、4，比較例5、6 ) 了在昇溫-降溫過程之電阻率的變化。測定裝置及 件係作成與驗證實驗1相同。 圖9係顯示實施例3、4及比較例5、6在昇； 過程之溫度和電阻率的關係之圖表。圖9中為作 一併顯示實施例1的資料。 即使In:Ga比相同’當Zn量變化時，熱處理 電阻率之差還是會明顯不同。具體而言，了解到 前的電阻率和熱處理後的電阻率之差會隨著Zn 而灸大。又，很清楚的是在Ga/(jn + Ga) = 9/ l〇NJ does not, too much A has a mutual 彳 m &amp; 的 state of the liquid crystal display device 5 series ^ T of the plurality of gates S? μ &amp; ', the father and the other / / 5 1 , and Remote gate wiring $ 1 - The data wiring of the hole 丨卞 4 52 4 . 1L Ba , 舅 wiring 5) / . Here, the gate wiring 5 1 is electrically insulated. At the intersection of pq Λ and the attached section, the 3-pole wiring 5 1 and the data wiring 52 _ sighs with a thin film transistor, a bonded transistor, ^ 1. Gate of the aa body 1; &gt;Special film transistor] 5 ° 16 is connected to the gate wiring 5 1, the source electrode 1 3 1 a of the P 1 is connected to the data wiring 52. Further, the contact hole 19 of the electrodeless electrode 14 4 of 1 (the lightning guide is placed in the contact hole 19 via the gate insulating film) is connected to the lower electric electrode 56 of the 昼•iivf -2 element. The overhead setting, that is, the liquid crystal, can be very reliable for the bottom gate, since it can be fabricated as a substrate display device. 201216374 ^ 55. This halogen lower electrode 55 is configured to constitute a capacitor 53. 2 and Fig. 3 _ Interpolar type:: The liquid of the present embodiment: the bonded film transistor, but the thin film transistor used in the present invention is not limited to a very thin film transistor. The 4-film transistor of j is suitable for use in a liquid crystal display device due to in-plane uniformity and Ximen. The thin film transistor of the present invention is sufficiently characterized by a low temperature, and the ut: ut Γ 者Therefore, a resin substrate (which can provide a large (four), uniform-, stable, and flexible, &lt;X-ray sensor&gt;" is shown in Fig. 4 as a part of a real-ray sensor of the sensor of the present invention. A schematic cross-sectional view of the schematic line of Fig. 5. More specifically, Fig. 4 is a schematic cross-sectional view of the γ 4+ ray ray sensor array. The ugly ugly energy & The X-ray sensor γ is provided with a thin tantalum transistor formed on the substrate, and a charge collecting electrode 7 on the capacitor 70 and an upper electrode 73. The film transistor 1 is provided with a reading permit. The capacitor 70 has a structure in which the capacitor lower electrode 76 is made of an upper electric (four) insulating insulating film 78. The electric portion electrode 77 is a source electrode 13 and a drain electrode of the transistor 1 via a contact hole provided in the insulating film η. The opposite direction of any of the electrodes 14: although the display is a shocking type, Qualitative and temperable. Annealing process Silicone substrate of the liquid crystal display form X The electrical part is enlarged and the structure is 7〇, and the layer 72 and the film 75 are formed. And the capacitor container is connected to the film side (the drain electrode 1 4 in Figure -22-201216374 4). The charge collecting electrode 713 is provided on the capacitor upper electrode 77 in the capacitor 70, and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer composed of amorphous selenium, and is provided to cover the thin film transistor 1 and the capacitor 70. The upper electrode 73 is provided on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72. As shown in Fig. 5, the X-ray sensor 7 of the present embodiment includes a plurality of gate wirings 8 1 that are parallel to each other, and a plurality of data wirings 82 that are parallel to each other and intersect with the gate wirings 8 1 . Here, the gate wiring 8 1 and the data wiring 8 2 are electrically insulated. A thin film transistor 1 is provided in the vicinity of the intersection of the gate wiring 8 1 and the data wiring 82. The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 181, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 82. Further, the drain electrode 14 of the thin film transistor 1 is connected to the charge collecting electrode 171, and this charge collecting electrode 71 constitutes the capacitor 70 together with the grounded counter electrode 76. In the X-ray sensor 7 of the present configuration, X-rays are irradiated from the upper portion (the upper electrode 73 side) in Fig. 4, and an electron-hole pair is generated in the X-ray conversion layer 72. A high electric field is applied to the X-ray conversion layer 72 by the upper electrode 73, and the generated electric charge is accumulated in the capacitor 70, and is read by sequentially scanning the thin film transistor 1. The X-ray sensor of the present invention is provided with a thin film transistor 1 having high in-plane uniformity and excellent reliability, and thus an image excellent in uniformity can be obtained. Further, in the X-ray sensor -23-201216374 of the present embodiment shown in FIG. 4, the bottom sensor is used, but the top gate type of the present invention may be a thin film transistor having a top gate type. The "special film transistor" used in the theft is not limited to a gate type thin film transistor. [Examples] Evaluation of TFT characteristics of an oxide semiconductor thin film in the range of measurement of electrical characteristics of an oxide semiconductor thin film was carried out. In the examples of the examples and the comparative examples, the examples of the production of the thin film transistor having the group of the present invention were carried out, and the verification test i: the in-situ In-situ of the untwisted film after the change of In_Ga t匕 was determined> The relationship between the annealing temperature and the electrical characteristics of the oxide film-coated oxide film (10), which is different from the composition ratio of In and Ga, was measured and evaluated as follows. As a sample for electric resistance measurement, the conditions of the respective examples and comparative examples of a predetermined size of the oxygen semiconductor thin film described later on the substrate were prepared, and an electrode was formed thereon. With reference to Fig. 6 and Fig. 7, the method for producing a sample for resistance measurement is 俯视6 7 (A) is a plan view and (B) is a cross-sectional view. As the substrate 100, a synthetic quartz glass substrate (porter part number T-4040, 1 inch xi mmt) is used, and the oxide semiconductor thin film 101 is described later on the substrate 100. Two examples of sputtering and film formation of the examples and the comparative examples were produced. At the time of film formation, a metal semiconductor thin film 1〇1 having a pattern of 3 mm x 9 inm was formed on the substrate 100 by a metal (see Fig. 6). The film formation system is performed by using the In2〇3 target, the Ga203 target, and the ZnO target-24-201216374 by co-sputter: the adjustment of the composition ratio is changed by the standard. The power of the target is compared. The electrode 102 was formed into a film by sputtering on the obtained oxide semiconductor film 1 〇 1 . The electrode 1〇2 is formed of a laminate film of Ti and Au. On the oxide semiconductor thin film i 0 , Ti was formed into a film of 1 〇 nm, and Au was formed into a film of 40 nm to form an electrode 102. A 4-terminal electrode is formed by patterning a film using a metal cover in electrode film formation (see Fig. 7). (Example 1) In the first embodiment, an IGZO film as an oxide semiconductor thin film was formed by the following sputtering film formation conditions. The cation composition ratio In: Ga: Zn = 0.2: 1.8 : 1.0 The film thickness is 5 Onm The film forming chamber reaches a vacuum of 6M (T6Pa film formation pressure A r flow rate 3 0 sccm 〇 2 flow · Osccm θ in Example 2, comparison In the case of Examples 1 to 4, a film having a cationic composition different from that of the actual example 丨@IGZC) was produced. Further, when the cation composition ratio is changed, the initial electric charge of the film is adjusted to be smaller than the amount of the carrier: 2, so that the oxygen flow rate at the time of film formation is adjusted so that the film converges in the range of 10 to 10 + 5 Ω. Here, the initial resistivity (knife value) refers to the room temperature before heat treatment (20. 电阻 resistivity: : widely, the film formation conditions of the comparative example, the cation composition ratio, and the oxygen machine (2) The flow rate is shown as follows. As described above, the film formation system uses the In2〇3 -25-201216374 払 target Ga2〇3 target and the Zn〇 target to be co-sputtered, and the change is input to each mark. The power ratio of the target was formed to form each composition ratio. Other conditions were the same as in Example 1 (Example 2) The film formation conditions of the oxide semiconductor thin film in Example 2 are as shown. The cation composition ratio In: Ga: Zn = 0.4 : 1.6 : 1.0 〇 2 Flow rate Osccm (Comparative Example 1) The film formation conditions of the oxide semiconductor thin film in Comparative Example 1 are as follows. The cation composition ratio In: Ga: Zn = 0.5: 1.5: 1. 〇 Flow Osccm ( Comparative Example 2) The film formation conditions of the oxide semiconductor thin film in Comparative Example 2 are as follows. The cation composition ratio In: Ga: Zn = 〇. 8: 1 1 〇〇 2 Flow rate O.lsccm (Comparative Example 3) Comparison The film formation conditions of the oxide semi-conductive etched rainbow raft film in Example 3 are as follows. Cation composition ratio IiKGiZi^m Q: 1 〇 2 Flow rate 1 1 5 sccm (Comparative Example 4) The thin film or film conditions of the oxide semiconductor in Comparative Example 4 are as follows -26 - 201216374. The cation composition ratio In: Ga: Zn = 1.5: 〇. 5: l 〇〇2 Flow rate 0.4 5 sccm &lt;Measurement of temperature change of resistivity&gt; With respect to the above six kinds of samples (Examples 1 and 2 and Comparative Examples 1 to 4), the environment can be controlled and set while being heat-treated. On the device for measuring resistance, the change in resistivity during the temperature rise-down process was measured. The cavity to the internal environment was set to Ar 160 sccm, 〇 2 40 sccm, and the temperature was raised to 200 ° C at 10 ° C / min, at 20 (The temperature was kept at room temperature for 10 minutes, and then cooled to room temperature. The relationship between the temperature and the specific resistance of the temperature rise-cooling processes of Examples 1, 2 and Comparative Examples 1 to 4 is shown in Fig. 8. As shown in Fig. 8, it is understood that the difference between the resistivity before the heat treatment and the resistivity after the heat treatment increases as the Ga composition ratio decreases and the In composition ratio increases. As in Examples 1 and 2, it is clear that Zn/( When In + Ga + Zn) = 1/3, if 4/5 gGa/(In + Ga), the resistivity of the film after heat treatment will The heat resistance is the same as that of the heat treatment. Here, the equivalent means that the resistivity h before the heat treatment step is "in the range of 0_lpaSpb$l〇pa (the same applies hereinafter) when the resistivity after the heat treatment step is made Pb. On the other hand, it was confirmed that Comparative Examples 1 to 4 suddenly caused a decrease in resistance during the temperature rising process, and thereafter, the resistivity did not return to the value before the heat treatment during the temperature reduction, and the change in the resistivity before and after the heat treatment was large. In the case of manufacturing a semiconductor film having a large area, it is difficult to uniformly maintain the temperature of the entire in-plane region, which causes uneven in-plane temperature during annealing. For example, if you compare the resistance value with the temperature rise and -27-201216374 does not return to the resistance value before the temperature rise after the temperature drop, the temperature unevenness in the surface will be generated in-plane. Uneven resistance values, that is, uneven electrical characteristics. In the case of i, as in the case of the examples i and 2, when there is almost no resistance value experienced in the temperature rise_cooling over, even if temperature unevenness occurs in the surface during annealing, there is no possibility of uneven electrical characteristics in the plane. It can be said that == a semiconductor film having high in-plane uniformity of electrical characteristics is obtained. This test also tests the in-situ (Ιη-situ) electrical characteristics of the IGZ tantalum film with different Zn composition ratios. ” Next, the relationship between the subsequent annealing temperature and electrical characteristics of the IGz〇 film with different Zn composition ratios' A resistance measurement was performed in the same manner as in the verification experiment 1. The temperature change of the resistivity was measured and evaluated using the sample. The IGZO film was prepared as the sample for resistance measurement by the sputtering conditions of the following Examples 3' 4 and Comparative Examples 5 and 6. ^ Each of the conditions of the sputtering conditions of the examples and the comparative examples is the same as the method for producing the sample for electric resistance measurement of the first embodiment, and the method and conditions for measuring the change in the degree of electric I1 are made. The same procedure as in the verification experiment 1. (Example 3) The film formation conditions of the oxide semiconductor thin film in Example 3 are as follows. The cation composition ratio In: Ga: Zn = 〇. 2: 1 ι 8 : 〇〇 2 Flow rate Osccm (Example 4) The film formation conditions of the oxide semiconductor thin film in Example 4 are as follows. -28 - 201216374 Cation composition ratio I n: G a: Ζ η = 0 · 2:1. 8 : 0.5 〇2 flow rate 〇sccm (Comparative Example 5) Oxide semiconductor in Comparative Example 5 The film formation conditions of the film are shown as follows: cation composition ratio In:Ga:Zn = 0.2:1.8:2.0 〇2 Flow rate 〇.3 sccm (Comparative Example 6) The film formation conditions of the oxide semiconductor thin film in Comparative Example 6 are shown. The cation composition ratio In:Ga:Zn = 0.2:1.8:3.5 〇2 Flow rate 1 1 sccm The change in resistivity in the above-mentioned sample (Examples 3 and 4, Comparative Examples 5 and 6) in the temperature rising-cooling process was measured. The apparatus and the parts were created in the same manner as in the verification experiment 1. Fig. 9 is a graph showing the relationship between the temperature and the resistivity of the examples 3 and 4 and the comparative examples 5 and 6 in the process of liters. 1) Even if the In:Ga ratio is the same 'When the amount of Zn changes, the difference in heat treatment resistivity will be significantly different. Specifically, it is known that the difference between the former resistivity and the heat resistion after heat treatment will vary with Zn. Moxibustion is big. Again, it is clear that Ga/(jn + Ga) = 9/ l〇

Zn/(In + Ga + Zn)g 1/3則熱處理後的膜之電阻率會 理前的電阻率同等。 〈驗證實驗3 :其他組成比不同的IGZ〇膜 係如下 係如下 ，測定 測定條 昆-降溫 比較而 前後的 熱處理 量增加 時，若 和熱處 之原位 -29- 201216374 (In-situ )電氣測定〉 針對其他組成比不同的IG2；0时 _ „ y J膜之退火溫度和電氣 特性的關係’與驗證實驗1同姆 A敏 J樣地製作電阻測定用試 料，進行電阻率的溫度變化測定。 以下述實施例5、6及比敕你丨1 〇 敉例7、§、9的濺鍍條件製 作IGZO膜，作為電阻測定用試料。 各實施例、比較例的濺鍍條件中所未記載的條件係 設成與實施例k電阻測定用試料的製作方法相同，電 [I且率的溫度變化測定方法及條侔 乃沃及絛件係作成與驗證實驗1相 同。 (實施例5) 貫把例5中之氧化物半導體薄膜的成膜條件係如下 所示。 本實施例5的氧化物半導體薄膜是不含以 In-Ga-0 (IGO)膜。 陽離子組成比In:Ga..Zn = 〇·5:1 5.〇 〇2 流量 Osccm (實施例6 ) 實％例6中之氧化物半導體薄膜的成膜條件係如 所示。 陽離子組成比 In:Ga:Zn= 〇.5:1 5:() 5 〇2 流量 Osccm (實施例7) -例7中之氧化物半導體薄祺的成膜條件係如 所示。 Γ -30- 201216374 陽離子組成比 IniGaiZns 8:24.13 〇2 流量 Osccm (比較例7) 所示 比較例7中之氧化物半導體薄膜 的成骐條件係如下 比較例7的氧化物半導體薄膜係盥/ 一見她例5同樣為 不含 Zn 的 In-Ga-0 ( IGO )膜。 陽離子組成比 In:Ga:Zn=l 1 〇 2 流量 0.1 5 s c c m (比較例8) 所示 比較例8中之氧化物半導體 薄膜的成膜條件係如下 陽離子組成比In:Ga:Zn = 〇:l.0:1 〇 〇2 流量 Osccm 7及比較例7、8 )，測定 變化。測定裝置及測定條 針對上述試料（實施例5〜 了在昇溫-降溫過程之電阻率的 件係作成與驗證實驗1相同。 圖係表示實施例5〜7及比較例7 溫過程之溫度和電阻率的關係之圖表。 昇，皿-降 確認了有關Ga組成吐鲈士从_ 實施例1同樣地在昇溫ϋ，貫施例5、6及7係與 初期值，熱處理前的電^王後’膜的電阻率恢復成 等，而相對地，以比理後的片電阻率是同 然地引起低電阻化， σ，會在幵溫過程時驟 高之下，-邊大:;維2’在電阻率未於降溫過程中變 、在200 C的值一邊恢復回來，因 -31- 201216374 而熱處理前後之電阻率大不相同。 此外，上述驗證實驗1、2中的各實施例及比較例中 的陽離子組成比係表示成膜後之膜的組成比。成膜後之 膜的組成比係使用螢光X射線分析裝置（Panalytical製 Axi〇s )作評估。又，有關各例’ X射線繞射測定的結果 為’未確認出表示結晶構造的峰值，均為非晶質。 圖11係將實施例 組成比繪製於三元相圖中。在三元相圖中，一併顯示由 本發明所規定的組成範圍及迄今為止所報告之規定了 IGZO的組成比之各專利文獻！〜4所規定的組成範圍。 圖11中，本發明之IGZ〇膜的組成範圍以領域A表示， 其中#父佳組成範圍以領域B表示。又，專利文獻丨所記 載之IGZO膜的组成範圍是以領域c、專利文獻2所記 載之IGZO膜的組成範圍是以領域β、專利文獻3所記 載，IGZ0獏的組成範圍是以領域E、以及專利文獻* 所記載之IGZO膜的組成範圍是以領域F分別來表示。 各專利文獻卜4中，雖從作為爪使用之際的移 」S值或光照射特性的觀點做了各種組成範圍的報 I好ίί沒有檢討有關可作成在後續退火之際的面内之 、2孔特性的均一性之最佳組成的報告例。 經本發明者的詳細研究 穩定^ 研九、纟。果，可瞭解從電氣特性的 、丨土々规點而言，这入火土 膜是最適合的。美太被發表之組成範圍的IGZ0 In組成比、Zn组疋透過將Ga組成比設高’亦即 膜中水A旦U 設低而使膜中水分量降低，可將由 =所引起之電氣特性不均抑制成極小。當 -32- 201216374Zn/(In + Ga + Zn)g 1/3 is the same as the resistivity before the heat treatment of the film after heat treatment. <Verification experiment 3: The other IGZ ruthenium film systems with different composition ratios are as follows, and the measurement is performed when the temperature of the heat treatment is increased, and if the heat treatment amount is increased, the heat is in situ -29-201216374 (In-situ) Measurement > For IG2 with different composition ratios; 0: _ _ y J film relationship between annealing temperature and electrical characteristics' and verification experiment 1 with the same A sample, the sample for resistance measurement was prepared, and the temperature change of resistivity was measured. The IGZO film was produced as the sample for electric resistance measurement by the sputtering conditions of the following Examples 5 and 6 and the above-mentioned Examples 7, §, and 9. The sputtering conditions of the respective examples and comparative examples were not described. The conditions are the same as those in the sample k for measuring the resistance measurement, and the method of measuring the temperature change of the I and the rate is the same as that of the verification experiment 1. (Example 5) The film formation conditions of the oxide semiconductor thin film of Example 5 are as follows. The oxide semiconductor thin film of Example 5 is free of an In-Ga-0 (IGO) film. The cation composition ratio In: Ga.. Zn = 〇·5:1 5.〇〇2 Flow Osccm (real Example 6) The film formation conditions of the oxide semiconductor thin film in Example 6 are as shown. The cation composition ratio In: Ga: Zn = 〇. 5: 1 5: () 5 〇 2 Flow rate Osccm (Example 7) - The film formation conditions of the oxide semiconductor thin crucible in Example 7 are as shown. Γ -30 - 201216374 Cation composition ratio IniGaiZns 8: 24.13 〇 2 Flow rate Osccm (Comparative Example 7) The oxide semiconductor in Comparative Example 7 is shown. The film formation conditions of the film are as follows. The oxide semiconductor thin film system of Comparative Example 7 is the same as the Zn-free In-Ga-0 (IGO) film. The cation composition ratio In:Ga:Zn=l 1 〇 2 Flow rate 0.1 5 sccm (Comparative Example 8) The film formation conditions of the oxide semiconductor thin film in Comparative Example 8 are as follows: cation composition ratio In: Ga: Zn = 〇: 1.0: 1 〇〇 2 Flow rate Osccm 7 and Comparative Examples 7 and 8) Measurements were measured. The measurement apparatus and the measurement strip were prepared for the sample (Example 5 to the resistivity of the temperature rise-down temperature process was the same as that of the verification experiment 1. The figure shows Examples 5 to 7. And Comparative Example 7 A graph of the relationship between the temperature and the resistivity of the temperature process. The rise, the dish-drop confirmed the composition of Ga. In the same manner as in Example 1, the gentleman warmed up, and the examples 5, 6 and 7 were combined with the initial values, and the electrical resistivity of the film before the heat treatment was restored to the same, and relatively, after the comparison, The sheet resistivity is the same as the low resistance, σ, which will be under the high temperature during the enthalpy temperature process, and the side is large: the dimension 2' is changed during the resistivity without cooling, and recovered at the value of 200 C. Come back, due to -31- 201216374, the resistivity before and after heat treatment is very different. Further, the cation composition ratios in the respective examples and comparative examples in the above verification experiments 1 and 2 indicate the composition ratio of the film after film formation. The composition ratio of the film after film formation was evaluated using a fluorescent X-ray analyzer (Axi〇s manufactured by Panalytical). Further, as a result of the X-ray diffraction measurement in each of the examples, the peak indicating the crystal structure was not confirmed, and all of them were amorphous. Fig. 11 is a diagram showing the composition ratio of the embodiment in a ternary phase diagram. In the ternary phase diagram, the patent ranges specified by the present invention and the patent ratios constituting the composition ratio of IGZO reported so far are shown together! The composition range specified in ~4. In Fig. 11, the composition range of the IGZ ruthenium film of the present invention is represented by the field A, wherein the range of the composition of the parent is indicated by the field B. In addition, the composition range of the IGZO film described in the patent document 是以 is that the composition range of the IGZO film described in the field c and the patent document 2 is described in the field β and the patent document 3, and the composition range of the IGZ0貘 is in the field E, The composition range of the IGZO film described in the patent document* is represented by the field F, respectively. In each of the patent documents, the report has been made in various ranges from the viewpoint of the "S value" or the light irradiation characteristic at the time of use as a claw, and has not been reviewed for the surface which can be formed in the subsequent annealing. A report example of the best composition of the uniformity of the 2-hole characteristics. A detailed study by the inventors of the present invention is stable. As a result, it can be understood that from the point of view of the electrical characteristics and the earthworms, this is the most suitable for the film. The IGZ0 In composition ratio of the composition range of the US and the Zn group 电气 can reduce the water content in the film by setting the Ga composition ratio higher, that is, the water in the film is lower, and the electrical characteristics caused by = can be The unevenness is suppressed to a minimum. When -32- 201216374

Ga組成比太高時則成為絶緣膜，難以使用 * &amp; €晶體，拫 清楚的是若為本發明的範圍之組成，則除了 1卸制膜中水 分量不均的效果以外，還適合作為用以呈 兄巧移動率之 電晶體的活性層。 &lt;驗證實驗4 : TFT特性評估&gt; 製作採用有本發明之組成範圍的IGZO模之TFT 進行其特性評估。 在基板方面是使用帶有熱氧化膜的p型 〇 1暴板’製 作出將熱氧化膜用作閘極絶緣膜的簡易型圖 (A )為簡易型TFT的俯視圖，同圖（Β)糸立，二门 y句刮面圖。 (實施例TFT1 ) 實施例TFT1的簡易型TFT係按以下那樣來製作（參 照圖1 2 )。 ’When the Ga composition ratio is too high, it becomes an insulating film, and it is difficult to use * &amp; € crystals, and it is clear that if it is a composition of the scope of the present invention, it is suitable as an effect of dispersing the unevenness of water content in the film. An active layer of a transistor used for the mobility of the brother. &lt;Verification Experiment 4: Evaluation of TFT Characteristics&gt; A TFT having an IGZO mode having the composition range of the present invention was produced for evaluation of its characteristics. In the substrate, a simple pattern (A) using a thermal oxide film as a gate insulating film using a p-type 暴1 blasting plate with a thermal oxide film is a top view of a simple TFT, and the same figure (Β)糸Li, two-door y sentence scraping map. (Example TFT1) The simple TFT of the TFT1 of the example was produced as follows (refer to Fig. 12). ’

在表面備有l〇〇nm的熱氧化膜1 1 1的p型Si i英呀 □基板110上以實施例1的成膜條件將IGZ〇膜丨丨2進 行5Onm，3mmX4mm的圖案成膜。接著在可控制環境的 電氣爐她作後續退火處理。後續退火環境係設成AThe IGZ ruthenium film 2 was patterned into a film of 5 Onm and 3 mm X 4 mm under the film formation conditions of Example 1 on a p-type Si y y substrate 110 having a thermal oxide film 11 1 having a thickness of 10 nm. She then performs a subsequent annealing process in an electric furnace that can control the environment. The subsequent annealing environment is set to A

16 0sccm、02 40sccm，以 ltTc/min 昇溫至 200°c，在 2〇(TC 下保持1 0分鐘後，藉爐冷方式進行冷卻迄至成為室溫為 止。 之後’在IGZO膜11 2上利用濺鍍將源極_汲極電極 11 3成膜。源極-汲極電極成膜係以採用金屬罩的圖案成 膜所製作。將Ti成膜l〇nm後且將Au成膜40nm者形成 源極-汲極電極11 3。源極-汲極電極尺寸分別設成 1mm□’電極間距離設成〇.2mm。 -33- 201216374 (實施例TFT2) 除了 IGZO膜以實施例2的成膣攸从 幻成膜條件成膜以外，其 餘是與實施例TFT 1同樣地來製造TF丁。 (實施例TFT3 ) 除了 IGZO膜以實施例3的成 J双膜條件成臈以外，其 餘是與實施例TFT1同樣地來製造TFT。 (實施例T F T 4 ) 除了1GZ0膜以實施们的成膜條件成膜以外，其 餘疋與貫施例T F Τ 1同樣地來製造τ ρ τ。 (實施例TFT5 ) 除了 IGZO膜以實施例7的成膜條件成膜以外，丈 餘是與實施例TFT1同樣地來製造TFT。 ’、 針對按上述那樣所獲得之實施例TFT丨〜5的簡易型 TFT，使用半導體參數分析儀4156匸（ Technologies ;安捷倫科技公司製品）進行了電晶體特性 (Vg-Id特性）及移動率μ之測定。 此外v g 1 d特性之測定，係透過將沒極電壓（ν」）固 定成5V，使閘極電壓（Vg)在]5v〜+4〇v的範圍内變化， 以測定在各閘極電壓（Vg)中之汲極電流（1〇而進行。 圖1 3〜1 7係分別表示實施例TFT丨〜5的Vg — h特性 之圖表。 1。圖1 3所示的實施例TFT i係可獲得截止電流為 1〇 A級，且〇n/〇ff比為〜1〇6的值，以常閉型進行驅 動。呈現電場效應移動率為3cm2/Vs，低溫形成且相較 於非晶矽具有相當高移動率之良好的電晶體特性。 201216374 關於圖14〜17所示的實施例 表示良好的電晶體特性。 【圖式簡單說明】 圖1係表不（A )頂開極_頂 —底接觸型、（C)底閘極—頂接觸 一底接觸型的薄膜電晶體之構成的 圖2係表示實施形態之液晶顯 略剖面圖 圖3係圖2的液晶顯示裝置之 圖 ® 4係表示實施形態之X射線 之概略剖面圖 圖5係圖4之X射線感測器陣 構成圖 圖6係表示電阻測定用樣品之 視圖、（B )為剖面圖 圖7係表示電阻測定用樣品之 視圖、（B )為剖面圖 圖8係表示實施例1、2及比較 導體薄膜在昇溫-降溫過程之溫度# 表 圖9係表示實施例1、3、4及丨 膜在昇溫-降溫過程之溫度和電阻率 圖1 〇係表示實施例5〜7及比」 在昇溫-降溫過程之溫度和電阻率的 T F T 2〜5亦是同樣地 接觸型、（B )頂閘極 型、及（D)底閘極 不意剖面圖 示裝置的一部分之概 電氣配線的概略構成 感測器陣列的一部分 列的電氣配線之概略 製作步驟，（A )為俯 概略構成，（A)為俯 .例1〜4的氧化物半 口電阻率的關係之圖 七較例5、6的IGZO 的關係之圖表 较例7、8的IGZO膜 關係之圖表 -35- 201216374 圖1 1係表示本發明之I η、G a、Ζ η的組成比範圍之 三元相圖 圖12係（A )為簡易型TFT的俯視圖、（Β )為剖 面圖 圖13係表示實施例TFT1的Vg-Id特性之圖表 圖14係表示實施例TFT2的Vg-Id特性之圖表 圖15係表示實施例TFT3的Vg-Id特性之圖表 圖16係表示實施例TFT4的Vg-Id特性之圖表 圖17係表示實施例TFT5的Vg-Id特性之圖表 【主要元件符號說明】 1、2、3、4 薄膜電晶體 11 基板 12 活性層（氧化物半導體薄膜） 13 源極電極 14 汲極電極 15 閘極絶緣膜 16 閘極電極 -36-16 0 sccm, 02 40 sccm, and the temperature was raised to 200 ° C at ltTc/min, and after being kept at 2 Torr for 10 minutes, it was cooled by furnace cooling until it became room temperature. Then, it was used on the IGZO film 11 2 . Sputtering forms the source-drain electrode 11 3 into a film. The source-drain electrode film formation is formed by patterning using a metal cover pattern. After Ti is formed into a film of 10 nm, and Au is formed into a film of 40 nm. Source-drain electrode 11 3. Source-drain electrode size is set to 1 mm□', and the distance between electrodes is set to 〇.2 mm. -33-201216374 (Example TFT2) In addition to the IGZO film, the formation of Example 2 TF was produced in the same manner as in the TFT 1 of the example except that the film was formed under the conditions of the phantom film formation. (Example TFT3) The IGZO film was formed by the J double film condition of Example 3, In the same manner as in the case of the TFT 1, the TFT was fabricated. (Example TFT 4) τ ρ τ was produced in the same manner as in the example TF Τ 1 except that the 1 GZ0 film was formed under the film formation conditions of the examples. (Example TFT5) A TFT was produced in the same manner as in the TFT 1 of the example except that the IGZO film was formed under the film formation conditions of Example 7. With respect to the simple TFTs of the TFTs 〜5 of the examples obtained as described above, the transistor characteristics (Vg-Id characteristics) and the mobility μ were measured using a semiconductor parameter analyzer 4156 (manufactured by Agilent Technologies, Inc.). In addition, the measurement of the vg 1 d characteristic is performed by fixing the gate voltage (Vg) to a range of 5V to +4〇v by fixing the gate voltage (ν) to 5V to measure the voltage at each gate. The drain current in (Vg) is performed in 1 。. Fig. 1 3 to 1 7 are graphs showing the Vg — h characteristics of the TFTs 〜 5 of the embodiment. 1. The TFT i system of the embodiment shown in Fig. 13. The off current is 1 〇A, and the 〇n/〇ff ratio is ~1〇6, which is driven by the normally closed type. The electric field effect is 3cm2/Vs, which is formed at a low temperature and is amorphous.矽Good transistor characteristics with a relatively high mobility. 201216374 The embodiment shown in Figures 14 to 17 shows good transistor characteristics. [Simplified Schematic] Figure 1 shows the top (A) top open electrode _ top - bottom contact type, (C) bottom gate - top contact and bottom contact type of thin film transistor 2 is a schematic cross-sectional view showing a liquid crystal display of the embodiment. FIG. 3 is a view showing a liquid crystal display device of FIG. 2. FIG. 4 is a schematic cross-sectional view showing an X-ray according to an embodiment. FIG. 5 is an X-ray sensor array of FIG. 6 is a view showing a sample for electric resistance measurement, (B) is a cross-sectional view, FIG. 7 is a view showing a sample for electric resistance measurement, and (B) is a cross-sectional view. FIG. 8 is a view showing Examples 1 and 2 and a comparative conductor film. Temperature of the temperature rising-cooling process # Table 9 shows the temperature and electrical resistivity of the first, third, and fourth enthalpy films during the temperature rising-cooling process. Figure 1 shows the examples 5 to 7 and the ratio" in the temperature rising-cooling process. The temperature and resistivity of the TFTs 2 to 5 are also similar to the contact type, (B) top gate type, and (D) the bottom gate is not intended to be a part of the device. The outline of the electrical wiring in a part of the column, (A) is a schematic configuration, (A) is the relationship between the oxide half-resistance of the examples 1 to 4, and the relationship between the IGZO of the examples 5 and 6. Chart of the relationship between the chart and the IGZO film of Examples 7 and 8 -35- 201216374 1 1 shows a ternary phase diagram of a composition ratio range of I η, G a, Ζ η of the present invention. FIG. 12 is a plan view of a simple TFT, (Β) is a cross-sectional view, and FIG. 13 shows an embodiment TFT1. FIG. 14 is a graph showing the Vg-Id characteristics of the TFT 2 of the embodiment. FIG. 15 is a graph showing the Vg-Id characteristics of the TFT 3 of the embodiment. FIG. 16 is a graph showing the Vg-Id characteristics of the TFT 4 of the embodiment. 17 is a graph showing the Vg-Id characteristics of the TFT5 of the embodiment [Description of main component symbols] 1, 2, 3, 4 thin film transistor 11 substrate 12 active layer (oxide semiconductor film) 13 source electrode 14 drain electrode 15 gate Pole insulating film 16 gate electrode-36-

Claims (1)

201216374 七、申請專利範圍： !· 一種氧化物半導體薄膜之製造方法，其特徵為包含： 成膜滿足以In、Ga、Zn及Ο作為主要構成元素、 組成比為 ll/20$Ga/(In + Ga + Zn)S9/10 、且 3/4$Ga/(In + Ga)$ 1、且 Zn/(In + Ga + Zn)S 1/3 的氧化 物半導體薄膜之成膜步驟；及 在氧化性環境中對前述氧化物半導體薄膜施作 l〇〇°C以上300°C以下的熱處理之熱處理步驟， 且以前述熱處理步驟後之前述氧化物半導體薄 膜的電阻率成為lf2cm以上1 x 1〇6Qcrn以下的方式設 定前述成膜步驟中之成膜條件及前述熱處理步驟中 之熱處理條件。 2 _如申請專利範圍第1項之氧化物半導體薄膜之製造方 法，其中前述成膜步驟中，係成膜進一步滿足 、 別逆組 成比為3/4各Ga/(In + Ga)S9/10者以作為前述急 半導體薄膜。 ^ 3 ·如申請專利範圍第1項之氧化物半導體薄膜之製造 法，其中將前述熱處理的溫度設成1〇(rc以上方 4·如申請專利範圍第1項之氧化物半導體薄膜之製造 法，其中前述熱處理步驟前之前述氧化物半 =方 ,,, τ隨溥腺 的電阻率係與該熱處理步驟後之電阻率同等。 、 5.如申請專利範圍第i項之氧化物半導體薄膜之製造 法，其中前述成膜步驟中，藉由賤鍍方式成祺前 化物半導體薄膜。 L氣 -37- 201216374 6 . —種氧化物半導體薄膜，係使用如申請專利範圍第1 至5項中任一項的氧化物半導體薄膜之製造方法所製 作之以In、Ga、Zn及Ο作為主要構成元素的氧化物 半導體薄膜，其特徵為：組成比係滿足11/20 $ Ga/ (In + Ga + Zn)S9/10 、且 3/4 S Ga/(In + Ga) S 1 、且 Zn/(In + Ga + Zn)^ 1/3，並且電阻率是 lQcm 以上 1 X 1 06 Ω c m 以下。 7. —種薄膜電晶體，係於基板上具有活性層、源極電 極、汲極電極、閘極絶緣膜及閘極電極的薄膜電晶 體，其特徵為： 前述活性層是由如申請專利範圍第6項之氧化物 半導體薄膜所構成者。 8 .如申請專利範圍第7項之薄膜電晶.體，其中前述基板 是具可撓性者。 9 . 一種顯示裝置，其特徵為：具備如申請專利範圍第7 項之薄膜電晶體。 1 0 . —種影像感測器，其特徵為：具備如申請專利範圍第 7項之薄膜電晶體。 11. 一種X射線感測器，其特徵為：具備如申請專利範圍 第7項之薄膜電晶體。 -38-201216374 VII. Patent application scope: !· A method for producing an oxide semiconductor film, comprising: forming a film satisfying In, Ga, Zn, and yttrium as main constituent elements, and having a composition ratio of ll/20$Ga/(In Film formation step of +Ga + Zn)S9/10 and 3/4$Ga/(In + Ga)$ 1 and Zn/(In + Ga + Zn)S 1/3 oxide semiconductor film; In the oxidizing atmosphere, the oxide semiconductor film is subjected to a heat treatment step of heat treatment at 100 ° C or higher and 300 ° C or lower, and the resistivity of the oxide semiconductor film after the heat treatment step is lf 2 cm or more and 1 x 1 〇 The film formation conditions in the film formation step and the heat treatment conditions in the heat treatment step described above are set in a manner of 6Qcrn or less. (2) The method for producing an oxide semiconductor thin film according to the first aspect of the invention, wherein in the film forming step, the film formation is further satisfied, and the composition ratio is 3/4 Ga/(In + Ga)S9/10 It is used as the above-mentioned emergency semiconductor film. ^3. The method for producing an oxide semiconductor film according to the first aspect of the invention, wherein the temperature of the heat treatment is set to 1 〇 (rc is above 4). The method for producing an oxide semiconductor film according to claim 1 , wherein the resistivity of the sacrificial gland is the same as the resistivity of the parotid gland before the heat treatment step. 5. The oxide semiconductor thin film of claim i is as claimed in claim i. In the manufacturing method, in the film forming step, a germanium semiconductor film is formed by a ruthenium plating method. L gas - 37 - 201216374 6 - an oxide semiconductor film is used as in the first to fifth aspects of the patent application. An oxide semiconductor thin film having In, Ga, Zn and hafnium as main constituent elements produced by the method for producing an oxide semiconductor thin film, characterized in that the composition ratio satisfies 11/20 $ Ga/ (In + Ga + Zn)S9/10 and 3/4 S Ga/(In + Ga) S 1 and Zn/(In + Ga + Zn)^ 1/3, and the specific resistance is 1×10 Ω cm or less. 7. A thin film transistor having an active layer on a substrate, a thin film transistor of a pole electrode, a gate electrode, a gate insulating film, and a gate electrode, wherein: the active layer is composed of an oxide semiconductor film as claimed in claim 6 of the patent application. The thin film electro-crystal body of the seventh aspect, wherein the substrate is flexible. 9. A display device comprising: a thin film transistor according to claim 7 of the patent application. 10 . A sensor comprising: a thin film transistor according to claim 7 of the patent application. 11. An X-ray sensor, comprising: a thin film transistor according to claim 7 of the patent application. -38-
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