201213826 六、發明說明： 【發明所屬之技術領域】 本發明為提供一種邏輯分析儀之資料預覽裝置及 其方法，尤指一種可預覽邏輯分析儀所截取之全部訊 號資料，並依據該資料進一步選擇所需要細部檢視的 資料區段。 【先前技術】 電子儀器於測試時會藉由量測輸出端之數值，來 为析該電子儀器功率之變化；在此概念下產生了示波 器，並發展出定時分析儀和狀態分析儀，而邏輯分析 儀則是結合數字定時和狀態分析兩種技術，其主要作 用在於時序判定，相較於示波器有許多電壓等級，邏 輯分析儀僅顯示兩個電壓（邏輯丨和0)，邏輯分析儀 通吊會先设定一參考電壓值，高於該參考電壓者邏輯 分析儀會判定為High，低於該參考電壓者則為L〇w , 藉此在High與Low之間形成數字波型；例如一個待測 仏號使用200MHz的邏輯分析儀，當參考電壓設定為 1.5V時’在測量時邏輯分析儀平均每5ns採取一個 點，超過1.5V者為High(邏輯1)，低於1.5V者為Low (邏輯0)，其邏輯丨和〇可連接成一個簡單波型，藉 此可在此連續波型中找出系統中異常錯誤之處；此 外’邏輯分析儀與示波器有通道數目不同之差異，— 201213826 般的不波器只有2個或4個通道，而邏輯分析儀可以 擁有從16個、32個《64個通道甚至更多，因此邏輯 分析儀具備同時進行多通道測試之優勢。 邏輯分析儀具有高迷量測數值、量測通道數目繁 多等特性’然而在邏輯分析儀擷取訊號資料之期間， Λ號資料產出速率非f冑，因在匕一般邏輯分析儀會將 量測所得之資料先儲存於記憶體組成之緩衝區，待該 緩衝區之記憶體儲存滿後再傳至電腦，但現今記憶體 的容量越來越大，甚至可達數Gbit，如此龐大的記憶 體=貝料要傳給電腦會花費很多時間，傳給電腦之後也 需要花費很多處理時間，而經處理後之每段資料也並 非皆為操作者所需要的資料。 故’上述問題，將是在此領域技術者所欲解決之 困難所在。 【發明内容】 故’本發明之發明人有鑒於上述先前技術所述之 不足，提出一種邏輯分析儀之資料預覽裝置及其方 法’其主要具有下列之目的： 本發明之主要目的在於：操作者可以迅速地判別 邏輯分析儀截取之訊號資料，以檢視特定區段資料； 其方法在於邏輯分析儀之資料預覽裝置可將邏輯分析 儀截取之原始資料另編成新訊號碼，透過檢視新訊號 201213826 碼波型之變化，藉此直接選擇細部檢視之原始資料區 段’以縮短傳輸與處理資料的時間。 【實施方式】 為了達成上述各項目的及功效，於此僅搭配圖 式，舉一較佳實施例，俾便在此領域中具通常知識者 能夠就各項目的據以實施。 首先，請參閱第一圖與第二圖，為本發明之結構 方塊圖與流程圖，圖中清楚指出—種邏輯分析儀之資 料預覽裴置1，藉由先預覽邏輯分析儀所截取之全部 訊號資料，再進一步選擇需要細部檢視的資料區段， 相較於習用的邏輯分析儀，本發明主要包括一系統控 制電路模組4、一訊號輸入介面模組2、一記憶模組 3以及一 USB輸出介面模組5、一編碼電路模組6與 一編碼儲存記憶模組7，該編碼電路模組6與該編碼 儲存記憶模組7串接後，分別與該訊號輸入介面模組 2與該USB輸出介面模組5相連接，可將原始資料另 編成新訊號碼以檢視新訊號碼波型之變化，藉此直接 選擇細檢視之原始資料區段，以縮短傳輸與處理資 料的時間，且能幫助操作者更快地判斷異常資料。 上述之邏輯分析儀之資料預覽裝置i可解決習用 邏輯分析儀儲存與處理資料花費較長時間之問題，透 過編碼電路模組6將邏輯分析儀所截取之訊號資料編 201213826 撰成新訊號碼，以利操作者進行觀測，其方法步驟為： (1) 編撰新訊號碼，將待測物與邏輯分析儀之資料預覽 裝置1相接，其訊號資料將會傳送至訊號輸入介面 模組2，再透過編碼電路模組6將邏輯分析儀所戴 取之訊號k料編撰成新訊號碼，並儲存於編竭儲存 記憶模組7中，新訊號碼再經由USB輸出介面模組 5上傳至電腦9中； (2) 檢視新訊號碼，電腦9顯示其新訊號碼以及其波 型，藉此可直接判別新訊號碼中資料變化之區段； (3) 細部檢視原始資料，根據資料變化之區段，選擇需 要細部檢視的特定資料區段，進一步檢視特定之原 始資料。 ^用之邏輯分析儀因為高速量測數值與量測通道 數目繁多，因此會將量測所得之資料先儲存於記憶模 組3組成之緩衝區，待該緩衝區容量儲滿後再經由系 統控制電路模組4與USB輸出介面模組5傳至電腦 9，但現今記憶體的容量越來越大，甚至已達數GMt， 如此龐大的記憶體資料要傳給電腦9會花費很多時 間，而且並非每段資料皆為操作者所需要的，若記憶 模組3組成緩衝區大小為1〇〇〇〇〇〇〇〇〇 (接近ig)，欲 在寬度為1〇〇〇點的晝面上顯示原始訊號資料其每一 點所顯示的資料量為1000000000 / 1000 = uooooo , 201213826 即晝面上每1點寬度實際上包含著1000000筆的資 料’故只有1點寬度的資料實際上代表著很長的波型 訊號，本發明其中之一實施例如下： 將待測物與邏輯分析儀之資料預覽裝置1相接， 其訊號資料將會傳送至訊號輸入介面模組2，再透過 、烏碼電路模組6將邏輯分析儀所戴取之訊號資料編撰 成新訊號碼，可將邏輯分析儀擷取到晝面上1個點寬 •度約loooooo筆的資料量，以二位元編碼方式將訊號 編碼儲存’測量時邏輯分析儀平均每5ns採取一個點， 且°又定參考電壓為l5V時’若該段訊號資料全部為低 準位時則儲存為「⑽」，全部為高準位時則儲存為 「11」’但若這段時間訊號資料有變化時則存為「01」， 當畫面解碼時可將剛〇_筆資料濃縮為2 bit的大 +絲存於編碼儲存記㈣諸7巾，新减碼再經由 USB輸出介面模組5上傳至電腦9中’操作者可直接檢 視新訊號碼波型之變A，並可選擇要細部檢視之原始 資料區段，藉由系統控制電路模組4於記憶模組3中 搜尋原始訊號資料，再經USB輸出介面模組5傳輸至 電腦9，將特定區段之原始資料呈現給操作者，以縮 短傳輸與處理資料的時間。 综〇上述，以上為本發明之一較佳實施例，非因 此即局限本發明之專利範圍，本案專利範圍仍應以後 201213826 附之專利申請範圍所定義為準。201213826 VI. Description of the Invention: [Technical Field] The present invention provides a data preview device and method thereof for a logic analyzer, and more particularly, a signal data that can be previewed by a logic analyzer and further selected according to the data. The section of data that requires detailed inspection. [Prior Art] When the electronic instrument is tested, the value of the output is measured to analyze the change of the power of the electronic instrument; under this concept, an oscilloscope is generated, and a timing analyzer and a state analyzer are developed, and logic The analyzer is a combination of digital timing and state analysis. Its main function is timing determination. Compared with oscilloscopes, there are many voltage levels. The logic analyzer only displays two voltages (logic 丨 and 0), and the logic analyzer is hanged. A reference voltage value is first set. Above the reference voltage, the logic analyzer determines that it is High, and below the reference voltage, it is L〇w, thereby forming a digital waveform between High and Low; for example, one The nickname to be tested uses a 200MHz logic analyzer. When the reference voltage is set to 1.5V, the logic analyzer takes a point every 5 ns on the measurement. If it exceeds 1.5V, it is High (logic 1). Below 1.5V, it is Low (logic 0), the logic 丨 and 〇 can be connected into a simple waveform, in which the abnormality in the system can be found in the continuous waveform; in addition, the number of channels of the logic analyzer and the oscilloscope The difference is that – 201213826, there are only 2 or 4 channels, and the logic analyzer can have 16 or 32 “64 channels or more, so the logic analyzer has simultaneous multi-channel testing. Advantage. The logic analyzer has the characteristics of high measurement value and a large number of measurement channels. However, during the period when the logic analyzer extracts the signal data, the output rate of the nickname data is not f胄, because the general logic analyzer will measure the amount. The measured data is first stored in a buffer formed by the memory. After the memory of the buffer is full, it is transferred to the computer. However, the capacity of the memory is now larger and larger, even up to several Gbits. Body = shell material will take a lot of time to pass to the computer, it will take a lot of processing time after passing to the computer, and each piece of data after processing is not all the information required by the operator. Therefore, the above problems will be the difficulties that the technicians in this field want to solve. SUMMARY OF THE INVENTION The inventors of the present invention have in view of the above-mentioned deficiencies of the prior art, and propose a data preview device for a logic analyzer and a method thereof, which mainly have the following objects: The main purpose of the present invention is: an operator The signal data intercepted by the logic analyzer can be quickly discriminated to view the specific segment data. The method is that the data preview device of the logic analyzer can separately encode the original data intercepted by the logic analyzer into a new message number, and view the new signal 201213826 code. The change of the waveform shape, thereby directly selecting the original data section of the detailed inspection to shorten the time for transmitting and processing the data. [Embodiment] In order to achieve the above objects and effects, only a preferred embodiment will be described with reference to the drawings, and those skilled in the art can implement the items for each purpose. First, please refer to the first figure and the second figure, which are structural block diagrams and flow charts of the present invention. The figure clearly indicates that the data preview device 1 of the logic analyzer is previewed by previewing the logic analyzer. The signal data further selects a data section that requires detailed inspection. Compared with the conventional logic analyzer, the present invention mainly includes a system control circuit module 4, a signal input interface module 2, a memory module 3, and a a USB output interface module 5, an encoding circuit module 6 and a code storage memory module 7, the code circuit module 6 and the code storage memory module 7 are serially connected to the signal input interface module 2 and The USB output interface module 5 is connected, and the original data can be separately edited into a new news number to view the change of the new wave number waveform, thereby directly selecting the original data section of the fine view to shorten the time for transmitting and processing data. And can help the operator to judge abnormal data more quickly. The data preview device i of the logic analyzer described above can solve the problem that the conventional logic analyzer stores and processes the data for a long time, and the signal circuit module 6 writes the signal data edited by the logic analyzer 201213826 into a new news number. The method steps are as follows: (1) Compiling the new message number, connecting the object to be tested to the data preview device 1 of the logic analyzer, and transmitting the signal data to the signal input interface module 2, Then, through the encoding circuit module 6, the signal k received by the logic analyzer is compiled into a new message number, and stored in the edited memory module 7, and the new message number is uploaded to the computer via the USB output interface module 5. 9; (2) Viewing the new news number, the computer 9 displays its new news number and its waveform, which can directly identify the section of the new information number change; (3) detail the original data, according to the data changes Section, select the specific data section that needs to be detailed, and further view the specific original data. ^The logic analyzer uses a large number of high-speed measurement values and measurement channels, so the measured data will be stored in the buffer formed by the memory module 3, and then the system will be controlled after the buffer capacity is full. The circuit module 4 and the USB output interface module 5 are transmitted to the computer 9, but the capacity of the memory is now larger and larger, even reaching a few GMts, and it takes a lot of time for such a large amount of memory data to be transmitted to the computer 9 and Not every piece of data is required by the operator. If the memory module 3 has a buffer size of 1〇〇〇〇〇〇〇〇〇 (close to ig), it is intended to be on the face of 1〇〇〇 width. Displaying the original signal data, the amount of data displayed at each point is 1000000000 / 1000 = uooooo, 201213826 That is, the width of every 1 point on the surface of the skull actually contains 1,000,000 pieces of data', so the data with only 1 point width actually represents a long The wave type signal, one of the embodiments of the present invention is as follows: the object to be tested is connected to the data preview device 1 of the logic analyzer, and the signal data is transmitted to the signal input interface module 2, and then transmitted through the U-code circuit. Group 6 compiles the signal data worn by the logic analyzer into a new message number, and can take the logic analyzer to the data volume of a dot width and a loooooo pen on the surface, and use the binary code to transmit the signal. Code storage 'When the logic analyzer takes a point every 5 ns, and ° also determines the reference voltage is l5V', if the signal data is all low level, it will be stored as "(10)", all of them are high level. Stored as "11"', but if there is a change in the signal data during this time, it will be stored as "01". When the screen is decoded, the data can be concentrated to 2 bits and stored in the code storage record (4) 7 The towel, the new subtraction code is then uploaded to the computer 9 via the USB output interface module 5 'The operator can directly view the change A of the new wave number waveform, and can select the original data section to be detailed, through the system control circuit The module 4 searches the memory module 3 for the original signal data, and then transmits the data to the computer 9 via the USB output interface module 5, and presents the original data of the specific segment to the operator to shorten the time for transmitting and processing the data. In view of the above, the above is a preferred embodiment of the present invention, and the scope of the patent of the present invention is not limited thereby, and the scope of the patent in this case is still subject to the definition of the patent application scope of 201213826.
8 201213826 【圖式簡單說明】 第一圖係本發明之結構方塊圖。 第二圖係本發明之流程圖。 【主要元件符號說明】 邏輯分析儀之資料預覽裝置 訊號輸入介面模組 ® 記憶模組 系統控制電路模組 USB輸出介面模組 編碼電路模組 編碼儲存記憶模組 待測物8 201213826 [Simplified description of the drawings] The first figure is a block diagram of the structure of the present invention. The second drawing is a flow chart of the present invention. [Key component symbol description] Logic analyzer data preview device Signal input interface module ® Memory module System control circuit module USB output interface module Code circuit module Code storage memory module Test object