201201650 六、發明說明： 【發明所屬之技術領威】 [0001] 本發明涉及電路板製作領域，尤其涉及一種具有凹槽結 構之電路板製作方法。 【先前技術】 [0002] 隨著科學技術進少，印刷電路板於電子領域得到廣泛應 用。關於電路板之應用請參見文獻Takahashi，A.201201650 VI. Description of the Invention: [Technical Leadership of the Invention] [0001] The present invention relates to the field of circuit board fabrication, and more particularly to a method of fabricating a circuit board having a groove structure. [Prior Art] [0002] With the advancement of science and technology, printed circuit boards have been widely used in the field of electronics. For the application of the circuit board, please refer to the literature Takahashi, A.
Ooki, N. Nagai. A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board f〇r HITAC M-880 » IEEE Trans, on Components, Packaging, and Manu- facturing Technology, 1992， 15(4): 418-425。 [0003] 由於電子設備小塑化之需求’通常於電路板中設置有凹 槽結構，該凹槽用於收容封裝或者插接之電子元件，從 而減小整個電路板封裝所饰據之空間。然两，先前技術 中’製作上述之凹槽於電路板製作過程中需要於電路板 之每一膠層形成對應開口’然後進行壓合及線路製作等 步驟，從而開口對應之區域於電路板製作過程中容易產 生涨縮不一致而產生稽敏。膠層於加壓加熱之條件下其 轉化為液態，雖然膠層對應凹槽之區域設有開口，但由 於溢膠量不易控制，這樣膠仍會流至凹槽底部之導電線 路表面，容易造成膠層與導電線路不易分離，並造成凹 槽内導電線路被損壞，從而影響整個電路板之性能。 【發明内容】 [0004] 有鑑於此，提供一種能夠有效保護凹槽内部之線路圖形 099119796 表單編號A0101 第4頁/共25頁 0992035016-0 201201650 之電路板製作方法實屬必要。 [0005] 以下將以實施例說明一種電路板製作方法。 [0006] 一種電路板製作方法，包括步驟：提供内層基板，所述 内層基板包括第一内層導電層；將第一内層導電層形成 第一内層線路圖形，第一内層線路圖形包括與欲形成之 凹槽結構對應之凹槽區域及所述凹槽區域以外之非凹槽 區域；於凹槽區域對應之第一内層線路圖形上印刷覆蓋 整個凹槽區域之液態油墨材料並固化形成保護層；於非 凹槽區域對應之第一内層線路圖形之表面及保護層之表 面依次壓合第一膠層及第一外層導電層，並將於非凹槽 區域對應之第一外層導電層製作形成第一外層線路圖形 :沿著凹槽區域之邊界對第一外層導電層及第一膠層進 行切割以形成開口，並將凹槽區域對應之第一外層導電 層、第一膠層及保護層去除以得到凹槽結構。 [0007] 相較於先前技術，本技術方案提供之電路板製作方法， 於凹槽結構内之内層導電線路表面形成保護層，可有效 避免後續進行壓合過程中膠層與上述之内層導電線路接 觸，從而可保護凹槽結構之底部之導電線路於形成凹槽 結構之過程中受到損壞。並且，由於設置有保護層，於 膠層中與凹槽結構對應之區域之膠層中無須開設開口， 從而可簡化電路板之製作流程，亦可有效之避免於膠層 中形成開口而導致壓合過程中產生褶皺。 【實施方式】 [0008] 下面結合複數附圖及實施例對本技術方案提供之電路板 099119796 製作方法作進一步說明。 表單編號A0101 第5頁/共25頁 0992035016-0 201201650 _9]本技術隸供之電路板製作料包括如下步驟·· [〇〇1〇]第一步，請參閱圖1，提供内層基板11{)。 國纟實施射，内層基板11〇為一個雙面覆銅板，内層基板 110包括第-内層導電層⑴、第二内層導電層112及夹 設於第-内層導電層U1及第二内層導電層112之間之絕 緣層113。 剛帛二步，請-併參閱圖2，將第一内層導電層iu形成第 -内層線路圖形11U，將第二内層導電層U2形成第二内 層線路圖形1121。 [_纟實施例中’採用影像轉移及餘刻工藝分別將第一内層 導電層111形成第一内層線路圖Blm，將第二内層導電 層112形成第二内層線路圖形112卜其中，第—内層線路 圖形mi包括第一導電線路1112及連接墊1113。第一内 層線路圖形1111之中間部分區域定義為凹槽區域1114， 用於製作具有凹槽結構之電或板之凹#之▲部。圖2中兩 條虛線之間界定之區域為凹槽區蜂1丨14，凹槽區域1114 以外之為非凹槽區域1115。凹槽區域1114之形狀可根據 實際需要製作之電路板之凹槽之形狀進行設定。本實施 例中，凹槽區域1Π4之形狀大致為長方形。連接墊丨丨13 及。15分之第一導電線路1Π2設置於凹槽區域1Π4内。連 接墊1113用於與封裝於電路板之凹槽内之電子元件相互 電連接，凹槽區域1114内之第一導電線路丨丨12用於將連 接墊1113與凹槽區域1U4外其他之第一導電線路m2相 互電連接。當然’凹槽區域1114内亦可不設置第一導電 099119796 表單編號Α0101 0992035016-0 201201650 [0014] [0015] Ο [0016] Q [0017] [0018] 線路1112。 於形成第一内層線路圖形11U及第二内層線路圖形112ι 之前’還可包括於内層基板11()之絕緣層113内製作導通 孔結構，以將後續製作形成之第一内層線路圖形ml& 第二内層線路圖形1121相互電導通。 第三步，請一併參閱圖3，於凹槽區域1114對應之第一導 電線路1112之表面形成内層防焊層114，以覆蓋凹槽區域 1114内之第一導電線路m2，而連接墊1113從内層防焊 層114露出。 ：V ； :； ： 本實施例中，藉由絲網印刷防焊油墨之方式於凹槽區域 1114對應之第一導電線路1112之表面及通過第一内層線 路圖形1111露出之絕緣層113之表面形求内層防焊層114 。於内層防焊層114與連接墊1113相對應芝區域形成有通 ... ： 孔1131 ’使得每個連接墊1113均從與其對應之通孔Π31 露出。 當凹槽區域1114内不包括有第广導電線路m2時，可不 於凹槽區域1114對應之表面形成内層防焊層114。 第四步’請一併參閱圖4 ’於凹槽區域1114對應之内層防 焊層114及連接墊1113之表面形成覆蓋整個凹槽區域 1114之保護層115。 [0019] 本實施例中’藉由於凹槽區域1114對應之内層防焊層114 及連接墊1113之表面印刷液態油墨材料之方式形成保護 層115。所述液態油墨材料可為熱固可剝型油墨，亦可為 顯影型油墨。所採用之液態油墨材料於固化後，其可承 099119796 表單編號A0101 第7 1/共25頁 0992035016-0 201201650 又^最同/皿度應大於200攝氏度，能夠承受璧強為千克 每平方屋米之壓力。並且液態油墨材料於固化後具有良 好之耐酸、鹼及氧化劑之腐蝕性能。 [0020] [0021] [0022] [0023] 當採用熱固可剝型油墨時，可直接將液態之油墨材料印 刷於凹槽區域1114對應之内層防焊層114及連接塾1113 之表面，並且經過加熱處理，使得液態之油墨材料固化 形成保護層115。熱固型可剝型油墨具有易於剝除之㈣ ’從而可避免於進行剝除過程中損傷連接签1113及内層 防焊層114。採用之熱固型油墨可ALM__ pSMs熱硬化 可剝離型油墨。 當採用顯影型油墨時，可先將直接將液態之油墨材料印 刷於凹槽區域1114對應之内層防焊層114及連接墊1113 之表面’然:後對形成之液態之油墨材料進行曝光顯影， 從而得到硬化後之保護層115。顯影型油墨材料固化後需 要採用對應之剝膜液將其♦除,.用之顯影型油墨材料 可為PR 2000SA感光型油赛。 !；；... ： 當凹槽區域111 4沒有形成内廣鰱谭時，可直接於第 一内層線路圖形1111之表面形成保護層115。 第五步，請一併參閱圖5及圖6，於非凹槽區域1115對應 之第一内層線路圖形1111之表面及保護層115之表面依次 壓合第一膠層120及第一外層導電層丨30，於第二内層線 路圖形11 21之表面依次壓合第二膠層14〇及第二外層導電 層150，並將非凹槽區域1115對應之第一外層導電層13〇 2作形成第一外層線路圖形1301，將第二外層導電層15〇 099119796 表單編號A0101 第8頁/共25頁 0992035016-0 201201650 [0024] Ο [0025]Ooki, N. Nagai. A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board f〇r HITAC M-880 » IEEE Trans, on Components, Packaging, and Manu-facturing Technology, 1992, 15(4): 418-425. [0003] The need for miniaturization of electronic devices has been generally provided with a recessed structure in the circuit board for receiving packaged or plugged electronic components, thereby reducing the space provided by the entire circuit board package. However, in the prior art, the process of making the above-mentioned groove in the manufacturing process of the circuit board requires forming a corresponding opening in each adhesive layer of the circuit board, and then performing pressing and circuit fabrication, so that the corresponding area of the opening is made on the circuit board. In the process, it is easy to produce inconsistency in the expansion and contraction. The rubber layer is converted into a liquid state under the condition of pressure heating. Although the rubber layer is provided with an opening corresponding to the groove, the glue is still difficult to control due to the amount of overflow, so that the glue will still flow to the surface of the conductive line at the bottom of the groove, which is easy to cause The glue layer and the conductive line are not easily separated, and the conductive lines in the groove are damaged, thereby affecting the performance of the entire circuit board. SUMMARY OF THE INVENTION [0004] In view of the above, it is necessary to provide a circuit board manufacturing method capable of effectively protecting the inside of the groove 099119796 Form No. A0101 Page 4 / Total 25 page 0992035016-0 201201650. [0005] A method of fabricating a circuit board will be described below by way of embodiments. [0006] A circuit board manufacturing method, comprising the steps of: providing an inner layer substrate, the inner layer substrate comprising a first inner layer conductive layer; forming a first inner layer conductive layer to form a first inner layer circuit pattern, wherein the first inner layer circuit pattern comprises and is to be formed a groove region corresponding to the groove structure and a non-groove region outside the groove region; printing a liquid ink material covering the entire groove region on the first inner layer circuit pattern corresponding to the groove region and curing to form a protective layer; The surface of the first inner layer circuit pattern corresponding to the non-groove area and the surface of the protective layer are sequentially pressed against the first adhesive layer and the first outer conductive layer, and the first outer conductive layer corresponding to the non-groove area is formed into the first surface. The outer layer pattern: the first outer conductive layer and the first adhesive layer are cut along the boundary of the groove region to form an opening, and the first outer conductive layer, the first adhesive layer and the protective layer corresponding to the groove region are removed A groove structure is obtained. [0007] Compared with the prior art, the circuit board manufacturing method provided by the technical solution forms a protective layer on the surface of the inner conductive line in the groove structure, which can effectively avoid the adhesive layer and the inner conductive line in the subsequent pressing process. The conductive traces that contact to protect the bottom of the recess structure are damaged during formation of the recess structure. Moreover, since the protective layer is provided, there is no need to open an opening in the adhesive layer in the region corresponding to the groove structure in the adhesive layer, thereby simplifying the manufacturing process of the circuit board, and effectively avoiding the formation of an opening in the adhesive layer and causing pressure Wrinkles are generated during the process. [Embodiment] [0008] The method for fabricating the circuit board 099119796 provided by the present technical solution will be further described below with reference to the accompanying drawings and embodiments. Form No. A0101 Page 5 of 25 0992035016-0 201201650 _9] The circuit board fabrication materials supplied by this technology include the following steps: [〇〇1〇] The first step, please refer to Figure 1, providing the inner substrate 11{ ). The inner substrate 11 is a double-sided copper clad plate, and the inner substrate 110 includes a first inner conductive layer (1), a second inner conductive layer 112, and a first inner conductive layer U1 and a second inner conductive layer 112. The insulating layer 113 is between. Just two steps, please - and referring to Fig. 2, the first inner conductive layer iu is formed into the first inner layer wiring pattern 11U, and the second inner conductive layer U2 is formed into the second inner layer wiring pattern 1121. [_纟In the embodiment, the first inner layer conductive layer 111 is formed into a first inner layer wiring pattern Blm by an image transfer and a residual process, and the second inner conductive layer 112 is formed into a second inner layer wiring pattern 112, wherein the first inner layer The line pattern mi includes a first conductive line 1112 and a connection pad 1113. The intermediate portion of the first inner layer pattern 1111 is defined as a recessed region 1114 for making a portion of the recess or the recess of the electric or plate having the recessed structure. The area defined between the two broken lines in Fig. 2 is the groove area bee 14 and the groove area 1114 is the non-groove area 1115. The shape of the groove region 1114 can be set according to the shape of the groove of the circuit board which is actually required to be fabricated. In the present embodiment, the shape of the groove region 1Π4 is substantially rectangular. Connect the pads 13 and . The first conductive line 1Π2 of 15 minutes is disposed in the recessed area 1Π4. The connection pad 1113 is for electrically connecting with the electronic components encapsulated in the recesses of the circuit board. The first conductive traces 12 in the recessed area 1114 are used to connect the connection pads 1113 with the recess area 1U4. The conductive lines m2 are electrically connected to each other. Of course, the first conductive area may not be provided in the recessed area 1114. 099119796 Form No. Α0101 0992035016-0 201201650 [0015] [0016] Q [0017] [0018] Line 1112. Before forming the first inner layer wiring pattern 11U and the second inner layer wiring pattern 112ι, a via hole structure may be formed in the insulating layer 113 of the inner substrate 11 () to form a first inner layer wiring pattern formed by the subsequent fabrication. The two inner layer wiring patterns 1121 are electrically conducted to each other. In the third step, referring to FIG. 3, an inner solder resist layer 114 is formed on the surface of the first conductive line 1112 corresponding to the recessed area 1114 to cover the first conductive line m2 in the recessed area 1114, and the connection pad 1113 is connected. It is exposed from the inner solder resist layer 114. :V ; :; : In this embodiment, the surface of the first conductive line 1112 corresponding to the recessed region 1114 and the surface of the insulating layer 113 exposed through the first inner layer trace pattern 1111 are formed by screen printing solder resist ink. The inner solder resist layer 114 is formed. The inner solder resist layer 114 is formed with a via hole corresponding to the connection pad 1113: a hole 1131' such that each of the connection pads 1113 is exposed from the corresponding via hole 31. When the wide conductive line m2 is not included in the recessed region 1114, the inner solder resist layer 114 may not be formed on the surface corresponding to the recessed portion 1114. The fourth step 'please refer to FIG. 4' to form a protective layer 115 covering the entire recessed region 1114 on the surface of the inner solder resist layer 114 and the connection pad 1113 corresponding to the recessed region 1114. [0019] In the present embodiment, the protective layer 115 is formed by printing the liquid ink material on the surface of the inner solder resist layer 114 and the connection pad 1113 corresponding to the recessed region 1114. The liquid ink material may be a thermosetting strippable ink or a development type ink. After the liquid ink material used is cured, it can bear 099119796 Form No. A0101 No. 7 1 / Total 25 Page 0992035016-0 201201650 And the same / the degree should be greater than 200 degrees Celsius, able to withstand barely for kilograms per square meter The pressure. And the liquid ink material has good corrosion resistance to acid, alkali and oxidant after curing. [0023] [0023] When a thermosetting strippable ink is used, the liquid ink material can be directly printed on the surface of the inner solder resist layer 114 and the connection port 1113 corresponding to the groove region 1114, and After heat treatment, the liquid ink material is cured to form the protective layer 115. The thermoset strippable ink has an easy peeling (4)' to avoid damage to the joint sign 1113 and the inner solder resist layer 114 during the stripping process. The thermosetting ink used can be thermally cured with ALM__ pSMs. When the developing ink is used, the liquid ink material may be directly printed on the surface of the inner solder resist layer 114 and the connection pad 1113 corresponding to the recessed region 1114. Then, the formed liquid ink material is exposed and developed. Thereby, the cured protective layer 115 is obtained. After the curing ink material is cured, it needs to be removed by using the corresponding stripping liquid. The developing ink material used for the development can be a PR 2000SA photosensitive oil race. When the groove region 111 4 is not formed, the protective layer 115 may be formed directly on the surface of the first inner layer wiring pattern 1111. In the fifth step, referring to FIG. 5 and FIG. 6, the surface of the first inner layer wiring pattern 1111 corresponding to the non-groove area 1115 and the surface of the protective layer 115 are sequentially pressed together with the first adhesive layer 120 and the first outer conductive layer.丨30, the second adhesive layer 14〇 and the second outer conductive layer 150 are sequentially pressed on the surface of the second inner layer pattern 11 21, and the first outer conductive layer 13〇2 corresponding to the non-groove region 1115 is formed. An outer layer pattern 1301, the second outer layer conductive layer 15 〇 099119796 Form No. A0101 Page 8 / Total 25 Page 0992035016-0 201201650 [0025] 00 [0025]
製作形成第二外層線路圖形15〇1。 為使得第二内層線路圖形丨丨21及外露之第—導電線路 1112與後續壓合於其上之縣之間具有良好之於壓合後 能保持較強之固著力。於進行墨合第一膠層120、第一外 層導電層130、第二膠層14〇及第二外層導電層15〇之前 ’可對形成有保護層115後之第二内層線路圖形U2i及外 露之第一導電線路1112進行粗化處理，以增加第二内層 線路圖形1121及外露之第一導電線路1112表面之粗輪度 。所述粗化處理可採用黑化或者棕化處理，即將第二内 層線路圖形1121及外露之第一導電線路1112表面之銅進 行氧化處理，使得部分銅氧化為一價銅或者二價銅使 得第二内層線路圖形1121及外露之第一導電線路HI〗表 面粗化。 本實施例中，採用加熱加壓之方式將第一膠層12〇及第一 外層導電層130形成非凹槽區域1115對應之第一内層線路 圖形1111之表面及保護層115之表面，將第二膠層14〇及 第二外層導電層150形成於余二内層線路圖形丨ι21之表面 。第一膠層120及第二膠層140可為半固化勝片（ Prepreg)。第一外層導電層13〇及第二外層導電層15〇 可為銅荡。 [0026] 本實施例中，與形成第一内層線路圖形lln及第二内層 線路圖形1121相同之方法形成第一外層線路圖形及 第二外層線路圖形1501。第一外層線路圖形13〇1與非凹 槽區域1115相對應，以避免後續形成凹槽結構損壞第一 099119796 外層線路圖形1301。為方便後續形成凹槽結構，於凹槽 表單編號A0101 笫9 1/共25頁 第9頁/共25頁 0992035016-0 201201650 區域1114對應之區域之第一外層導電層13〇内形成有對位 標記1 302。本實施例中，對位標記13〇2對應部分之第一 外層導電層130沒有去除，對位標記13〇2之形狀與凹槽區 域1114之形狀相對應，對位標記13〇2與第一外層線路圖 形1301相互分離，於後續形成凹槽結構時，可沿著對位 標記1 302之邊緣進行對位。 [0027] [0028] 099119796 於形成第一外層線路圖形1301及第二外層線路圖形15〇1 之前，還可進一步包括於第一膠層12〇及第二膠層14〇内 形成導通結構，以將後續形成之第_外層線路圖形13〇1 及第一内層線路圖形1 1 1 1之間及第二内層線路圖形丨丨2 i 及第二外層線路圖形1501之間相互導通。形成導通結構 可採用如下方式製作：首先於膠層及對應之外層導電層 中開孔，然後藉由電鍍之方式於所述孔之内壁形成導電 層形成導通孔，從而將外層導電層與内層基板n〇兩侧之 線路圖形對應導通，從”外層導電層形成外層線路圖 形時，外層線路圖形與内4^4圖_藉由對應之導通孔 電導通。當然’亦可於形成之孔内填充導電材料之方式 將外層導電層與内層基板11Q兩侧之内層線路圖形對應導 通0 當製作更多層之電路板時，還可於第一外層線路圖形 1301及第二外層線路圖形15〇1之表面繼續壓合第三膠層 及第三外層導電層’並將第三外層導電層製作形成第三 外層線路圖形，從而可得到更多層之電路板。 第六步，請一併參閱圖7及圖8，沿著凹槽區域1114之邊 緣對第-外層導電層m及第一膠層m進行切割以形成 0992035016-0 表單編號A0101 第10頁/共25頁 [0029] 201201650 開口 101，並將凹槽區域1114對應之第一外層導電層13〇 、第一膠層120及保s蔓層115去除，從而得到具有凹槽 102之電路板1〇〇。 [0030] 於進行切割之前，還可於第一外層線路圖形13〇1及第二 外層線路圖形1 5 01之表面形成外層防焊層，以將第一外 層線路圖形1301及第二外層線路圖形15〇1中需要進行保 A之區域覆蓋。外層防焊層均採用印刷防焊油墨之方式 形成，並於第一外層線路圖形13〇1及第二外層線路圖形 〇 1501中需要與外界進行連通之區域對應形成開口 ’從而 外層防焊層覆蓋第一外層線路圖形1301及第二外層線路 圖开> 15 01中需要外界絕緣隔離之部分，而使得需要與外 界進行導通之區域暴露於外。 [0031] 凹槽102之形成可採用如下方法： [0032] 首先，採用錯射切割或者機械定深切割之方式，沿著凹 槽區域1114之邊界，形成貫穿第一外邊導杳層1 3〇、第一 膠層120之開口 1〇1 »第一開口 ι〇1之深度方向應垂直於 第一膠層120。本實施例中，可沿，著對位標記丨3〇2之邊緣 進行切割，從沿著凹槽區域1114設置之開口 1〇1。當第一 外層線路圖形1301之表面形成有第三膠層及第三外層導 電層時，形成之開口 101應貫穿第一膠層！ 2〇上方之第三 膠層及第三外層導電層。 [0033] 然後，將凹槽區域1114對應之第一膠層120及對位標記 1302去除。由於凹槽區域1114對應之第一膠層ι2〇僅與 保護層115相互接觸’而不與第一内層線路圖形丨丨丨丨接觸 099119796 表單編號A0I01 第11頁/共25頁 0992035016-0 201201650 [0034] [0035] [0036] [0037] [0038] 。凹槽區域1114對應之第一膠層12〇去除並不會損傷凹槽 區域1114對應之第一内層線路圖形1111。第一膠層120 去除可採用人工進行將其去除。 最後將保°隻層115去除，從而得到具有凹槽1〇2之電路 板 10 0 〇 當採用顯影型油墨形成保護層115時，可採用藥水剝膜之 方法將保濩層11 5去除。即將保護層】丨5與顯影型油墨對 應之去膜藥水發生化學反應，使得保護層115溶解或者從 内層防焊層114及連揍墊1113之表面脱離。 .... ... .. 當採用可剝型油墨形成之保護層115層時，其具有良好之 可剝離性能’可直接將其從内層防焊層U4及連接墊1113 之表面剝離。 本實施例提供之電路板製作方法，於凹槽結構底部之内 層導電線路表面形成保護層，可有效避免後績進行壓合 過程中膠層與上述之内層導電線路接觸，從而可保護凹 槽結構之底部之導電線路於形成凹槽結構之過程中受到 損壞。並且，由於設置有保護層’從而於膠層中與凹槽 結構對應之區域之膠層中無須開設開口’從而可簡化電 路板之製作流程，亦可有效之避免於膠層中形成開口而 導致壓合過程中產生褶皱。 綜上所述’本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士援依本發明之精神所作之等效修飾或變化 099119796 表單編號A0101 第12頁/共25頁 0992035016-0 201201650 ，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0039] 圖1係本技術方案實施例提供之内層基板之剖面示意圖。 [0040] 圖2係本技術方案實施例提供之内層基板形成第一内層線 路圖形及第二内層線路圖形後之示意圖。 [0041] 圖3係本技術方案實施例提供之第一内層線路圖形表面形 成内層防焊層後之示意圖。 [0042] 圖4係本技術方案實施例提供之内層防焊層及連接墊表面 形成保護層後之示意圖。 [0043] 圖5係本技術方案實施例提供之壓合第一膠層、第一外層 導電層、第二膠層及第二外層導電層後之示意圖。 [0044] 圖6係本技術方案實施例提供之第一外層導電層及第二外 層導電層形成線路圖形後之示意圖。 [0045] 圖7係本技術方案實施例提供之對第一膠層進行切割形成 開口後之之示意圖。 [0046] 圖8係本技術方案實施例製得之具有凹槽之電路板之示意 圖。 【主要元件符號說明】 [0047] 電路板：100 [0048] 開口 ： 1 0 1 [0049] 凹槽：102 [0050] 内層基板：110 099119796 表單編號A0101 第13頁/共25頁 0992035016-0 201201650 [0051] 第一内層導電層： 111 [0052] 第一内層線路圖形 ：1111 [0053] 第一導電線路：111 2 [0054] 連接墊：1113 [0055] 凹槽區域：1114 [0056] 非凹槽區域：111 5 [0057] 第二内層導電層： 112 [0058] 第二内層線路圖形 ：1121 [0059] 絕緣層：113 [0060] 通孔：1131 [0061] 内層防焊層：114 [0062] 保護層：115 [0063] 第一膠層：120 [0064] 第一外層導電層： 130 [0065] 第一外層線路圖形 ：1301 [0066] 對位標記：130 2 [0067] 第二膠層：140 [0068] 第二外層導電層： 150 [0069] 第二外層線路圖形 ：1501 099119796 表單編號A0101 第14頁/共25頁 0992035016-0A second outer layer pattern 15〇1 is formed. In order to make the second inner layer pattern 丨丨21 and the exposed first conductive line 1112 and the county which is subsequently pressed thereto have good bonding force, the strong fixing force can be maintained. Before performing the ink bonding of the first adhesive layer 120, the first outer conductive layer 130, the second adhesive layer 14〇, and the second outer conductive layer 15〇, the second inner layer wiring pattern U2i and the exposed surface 115 may be exposed. The first conductive line 1112 is subjected to a roughening process to increase the coarse rotation of the surface of the second inner layer wiring pattern 1121 and the exposed first conductive line 1112. The roughening treatment may be blackening or browning, that is, the copper of the surface of the second inner layer pattern 1121 and the exposed first conductive line 1112 is oxidized, so that part of the copper is oxidized to monovalent copper or divalent copper. The inner layer circuit pattern 1121 and the exposed first conductive line HI are roughened. In this embodiment, the first adhesive layer 12 and the first outer conductive layer 130 are formed by heating and pressing to form a surface of the first inner layer trace pattern 1111 corresponding to the non-groove region 1115 and a surface of the protective layer 115. The second adhesive layer 14A and the second outer conductive layer 150 are formed on the surface of the remaining inner layer wiring pattern 2121. The first adhesive layer 120 and the second adhesive layer 140 may be prepreg. The first outer conductive layer 13 and the second outer conductive layer 15 〇 may be copper splay. In the present embodiment, the first outer layer wiring pattern and the second outer layer wiring pattern 1501 are formed in the same manner as the first inner layer wiring pattern 11n and the second inner layer wiring pattern 1121. The first outer layer pattern 13〇1 corresponds to the non-groove area 1115 to prevent subsequent formation of the groove structure from damaging the first 099119796 outer line pattern 1301. In order to facilitate the subsequent formation of the groove structure, a groove is formed in the first outer conductive layer 13〇 of the region corresponding to the region 1114 in the groove form number A0101 笫9 1 / 25 pages 9 page / 25 pages 0992035016-0 201201650 Mark 1 302. In this embodiment, the first outer conductive layer 130 corresponding to the corresponding portion of the alignment mark 13〇2 is not removed, and the shape of the alignment mark 13〇2 corresponds to the shape of the groove region 1114, and the alignment mark 13〇2 and the first The outer layer patterns 1301 are separated from each other, and may be aligned along the edges of the alignment marks 1 302 when the groove structure is subsequently formed. [0028] 099119796 before forming the first outer layer pattern 1301 and the second outer layer pattern 15〇1, further comprising forming a conductive structure in the first adhesive layer 12〇 and the second adhesive layer 14〇, The subsequently formed first outer layer pattern 13〇1 and the first inner layer line pattern 1 1 1 1 and the second inner layer line pattern 丨丨2 i and the second outer layer line pattern 1501 are electrically connected to each other. The conductive structure can be formed by first opening a hole in the adhesive layer and the corresponding outer conductive layer, and then forming a conductive hole on the inner wall of the hole by electroplating to form a via hole, thereby forming the outer conductive layer and the inner layer substrate. The line patterns on both sides of n〇 are correspondingly turned on. When the outer layer conductive pattern forms the outer layer pattern, the outer layer pattern and the inner layer pattern are electrically conducted through the corresponding via holes. Of course, the holes can also be filled in the formed holes. In the manner of the conductive material, the outer conductive layer is electrically connected to the inner layer circuit pattern on both sides of the inner substrate 11Q. When more circuit boards are formed, the first outer circuit pattern 1301 and the second outer circuit pattern 15〇1 can also be used. The surface continues to press the third adhesive layer and the third outer conductive layer ' and form a third outer conductive layer to form a third outer circuit pattern, thereby obtaining more layers of the circuit board. For the sixth step, please refer to FIG. 7 together. And FIG. 8, the first outer layer conductive layer m and the first adhesive layer m are cut along the edge of the groove region 1114 to form 0992035016-0. Form No. A0101 Page 10 of 25 [0029] 201201650 The opening 101 removes the first outer conductive layer 13A, the first adhesive layer 120, and the protective layer 115 corresponding to the recessed region 1114, thereby obtaining a circuit board 1 having the recess 102. [0030] Before the cutting, an outer solder mask layer may be formed on the surfaces of the first outer layer wiring pattern 13〇1 and the second outer layer wiring pattern 105, to form the first outer layer wiring pattern 1301 and the second outer layer wiring pattern 15〇1. The area coverage of the protection A is performed. The outer solder mask layer is formed by printing the solder resist ink, and the opening is formed corresponding to the area of the first outer layer pattern 13〇1 and the second outer layer pattern 〇1501 that needs to communicate with the outside. Thus, the outer solder mask covers the first outer layer pattern 1301 and the second outer layer pattern opens > 15 01 requires external insulation isolation, so that the area that needs to be electrically connected to the outside is exposed. [0031] The formation of 102 can adopt the following method: [0032] First, a method of misalignment cutting or mechanical deep cutting is used to form a first outer guiding layer 13 along the boundary of the groove region 1114. The opening of the adhesive layer 1201〇1 »the depth of the first opening ι〇1 should be perpendicular to the first adhesive layer 120. In this embodiment, the edge of the alignment mark 丨3〇2 can be cut along the edge. The opening 1〇 is provided in the recessed area 1114. When the third outer layer and the third outer conductive layer are formed on the surface of the first outer layer pattern 1301, the formed opening 101 should penetrate the first adhesive layer! The third adhesive layer and the third outer conductive layer. [0033] Then, the first adhesive layer 120 and the alignment mark 1302 corresponding to the groove region 1114 are removed. Since the first adhesive layer ι2 corresponding to the concave region 1114 is only The protective layers 115 are in contact with each other' without being in contact with the first inner layer wiring pattern. 099119796 Form No. A0I01 Page 11/Total 25 Page 0992035016-0 201201650 [0034] [0036] [0038] [0038] The first adhesive layer 12〇 corresponding to the recessed area 1114 is removed without damaging the first inner layer trace pattern 1111 corresponding to the recessed area 1114. The first glue layer 120 can be removed by manual removal. Finally, the protective layer 115 is removed to obtain a circuit board having a recess 1 〇 2 〇 When the protective layer 115 is formed by developing ink, the protective layer 11 5 can be removed by a method of blasting the film. That is, the protective layer 丨5 chemically reacts with the removing syrup corresponding to the developing ink, so that the protective layer 115 is dissolved or detached from the surfaces of the inner solder resist layer 114 and the lining pad 1113. When the protective layer 115 formed of the peelable ink is used, it has good peelability. It can be directly peeled off from the surface of the inner solder resist U4 and the connection pad 1113. In the circuit board manufacturing method provided in this embodiment, a protective layer is formed on the inner conductive circuit surface at the bottom of the groove structure, which can effectively avoid the contact between the adhesive layer and the inner conductive line in the pressing process, thereby protecting the groove structure. The conductive traces at the bottom are damaged during the formation of the recess structure. Moreover, since the protective layer is provided, the opening of the adhesive layer in the region corresponding to the groove structure in the adhesive layer is not required, thereby simplifying the manufacturing process of the circuit board, and effectively avoiding the formation of the opening in the adhesive layer. Wrinkles are generated during the pressing process. In summary, the present invention has indeed met the requirements of the invention patent and has filed a patent application in accordance with the law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by those skilled in the art in light of the spirit of the invention. 099119796 Form No. A0101 Page 12 of 25 0992035016-0 201201650 shall be covered by the following patents. BRIEF DESCRIPTION OF THE DRAWINGS [0039] FIG. 1 is a schematic cross-sectional view of an inner substrate provided by an embodiment of the present technical solution. 2 is a schematic view showing the inner layer substrate and the second inner layer circuit pattern formed by the inner layer substrate provided by the embodiment of the present technical solution. 3 is a schematic view showing the surface of the first inner layer wiring pattern provided by the embodiment of the present technical solution after forming the inner layer solder resist layer. 4 is a schematic view of the inner layer solder resist layer and the surface of the connection pad formed after the protective layer is provided in the embodiment of the present technical solution. 5 is a schematic view of the first adhesive layer, the first outer conductive layer, the second adhesive layer, and the second outer conductive layer provided by the embodiment of the present invention. FIG. 6 is a schematic diagram of the first outer conductive layer and the second outer conductive layer formed by the embodiment of the present invention. 7 is a schematic view of the first adhesive layer after cutting to form an opening provided by an embodiment of the present technical solution. 8 is a schematic view of a circuit board having a recess made by an embodiment of the present technical solution. [Main component symbol description] [0047] Circuit board: 100 [0048] Opening: 1 0 1 [0049] Groove: 102 [0050] Inner substrate: 110 099119796 Form number A0101 Page 13 of 25 0992035016-0 201201650 First inner conductive layer: 111 [0052] first inner layer wiring pattern: 1111 [0053] first conductive line: 111 2 [0054] connection pad: 1113 [0055] groove area: 1114 [0056] non-recessed Slot area: 111 5 [0057] Second inner conductive layer: 112 [0058] Second inner layer wiring pattern: 1121 [0059] Insulation layer: 113 [0060] Through hole: 1131 [0061] Inner layer solder resist layer: 114 [0062] Protective layer: 115 [0063] First adhesive layer: 120 [0064] First outer conductive layer: 130 [0065] First outer layer pattern: 1301 [0066] Alignment mark: 130 2 [0067] Second adhesive layer :140 [0068] Second outer conductive layer: 150 [0069] Second outer circuit pattern: 1501 099119796 Form No. A0101 Page 14 / Total 25 Page 0992035016-0