TW201200868A - Method for inspecting defects of power layer and ground layer of PCB - Google Patents

Method for inspecting defects of power layer and ground layer of PCB Download PDF

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Publication number
TW201200868A
TW201200868A TW099119812A TW99119812A TW201200868A TW 201200868 A TW201200868 A TW 201200868A TW 099119812 A TW099119812 A TW 099119812A TW 99119812 A TW99119812 A TW 99119812A TW 201200868 A TW201200868 A TW 201200868A
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Taiwan
Prior art keywords
layer
circuit board
ground layer
defect
power
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TW099119812A
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Chinese (zh)
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TWI401430B (en
Inventor
Guang-Shiah Wang
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Machvision Inc
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Priority to TW099119812A priority Critical patent/TWI401430B/en
Priority to KR1020110013672A priority patent/KR101195694B1/en
Publication of TW201200868A publication Critical patent/TW201200868A/en
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Publication of TWI401430B publication Critical patent/TWI401430B/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/24—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • G01R31/309—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of printed or hybrid circuits or circuit substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/08—Monitoring manufacture of assemblages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
    • G01N2021/8887—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges based on image processing techniques
    • G01N2021/8893—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges based on image processing techniques providing a video image and a processed signal for helping visual decision
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects
    • G01N2021/95638—Inspecting patterns on the surface of objects for PCB's

Abstract

The present invention discloses a method for inspecting the defects existing in a power layer and a ground layer of a printed circuit board (PCB). The drilling hole data of the PCB are received, and the pattern of at least one power layer or at least one ground layer of the PCB is scanned to have an image file. The image file and the drilling hole data are compared with each other to obtain the relation between the positions of some drilling holes of the drilling hole data and the contours of the pattern of the power layer or the ground layer, wherein the power layer or the ground layer is disposed on an insulating layer and the drilling holes are in the insulating layer.

Description

201200868 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種電路板之電源層及接地層之缺陷檢 測方法’特別係關於一種藉由自動化機器視覺檢測電路板 之電源層及接地層中存在缺陷之方法。 【先前技術】 由於印刷電路板為電子產品之重要零組件 電路板發生異$則使該產品無法正常運作甚至毀壞，例如 :醫療設備、保全系統與通訊器材等。而產品品質在於設 計階段便可決定，此時設計重點環繞於性能與結構上，但 又。十會衫響製造的難易度及良率。故電路板製造時除了依 循各種規格外，不同的客戶會對其產品訂定個別之規格， 因此從供應商管制為起點，材料選購與生產線操作到最後 的成品出貨須訂定各階段有效的品檢方法。 產品檢驗可以分為全數檢驗與抽樣檢驗，全數檢驗是 -種：分之百的檢驗方法可在生產完成時逐項剔除不合格 之缺陷品’生產卫廠無不希望能做到全數檢驗以減少產品 瑕疲所可能帶來之售後維修與商譽上的損失。早期數位影 像科技尚未普及的年代，生產廠商由人工輔以放大鏡與燈 備檢驗電路板之缺陷，此法之檢測人員常受到個人 =!境影響使得誤判的機會大增。也因此必需藉由自 =:視覺設備來取代人工能力的有限與不足，同時提 阿了產°口品質與降低誤檢率的發生。 目則自動化機器視覺設備之功能都是針對檢測印刷電 201200868 路板中線路層之佈線圖型而設計，圖1係一印刷電路板中線 路層之佈線圖型之示意圖。圖中線路層之佈線圖型包含許 多有待被檢測出之缺陷，茲將各缺陷標號及簡單說明列表 於下：201200868 VI. Description of the Invention: [Technical Field] The present invention relates to a method for detecting a defect in a power supply layer and a ground layer of a circuit board, particularly in a power supply layer and a ground layer for detecting a circuit board by an automated machine vision A method of flaws. [Prior Art] Since the printed circuit board is an important component of the electronic product, the board is not able to operate normally or even be destroyed, for example, medical equipment, security systems, and communication equipment. The quality of the product is determined by the design phase, where the design focus is on performance and structure, but again. The difficulty and yield of the production of the ten-party shirt. Therefore, in addition to following various specifications, different customers will set individual specifications for their products. Therefore, starting from supplier control, material selection and production line operation to final product shipment must be effective at all stages. The quality inspection method. Product inspection can be divided into full inspection and sampling inspection. The full inspection is a kind: one hundred of the inspection methods can eliminate the unqualified defects item by item when the production is completed. The production factory has no hope to do the full inspection to reduce The loss of after-sales maintenance and goodwill that may result from product fatigue. In the era when early digital image technology was not popular, manufacturers were supplemented by manual magnifiers and lamps to verify the defects of the circuit board. The testers of this method were often affected by personal influences, which greatly increased the chance of misjudgment. Therefore, it is necessary to replace the limitations and deficiencies of the human ability by the =: visual equipment, and at the same time raise the quality of the mouth and reduce the incidence of false detection. The function of the automated machine vision equipment is designed to detect the wiring pattern of the circuit layer in the printed circuit board 201200868. Figure 1 is a schematic diagram of the wiring pattern of the wiring layer in the printed circuit board. The wiring pattern of the circuit layer in the figure contains many defects to be detected. The defect numbers and simple descriptions are listed below:

標號 缺陷說明 1 孔位偏移（Breakout) 2 針孔（PinHole) 3 開路（Open Circuit) 4 1虫刻不足（Underetch) 5 缺角（Mousebite) 6 電路漏印（Missing Conductor ) 7 突出點（Spur) 8 短路（Short) 9 孔徑錯（Wrong Size Hole ) 10 間距不足（Conductors too close ) 11 銅渣（Spurious Copper ) 12 重複短路（Excessive Short) 13 缺孔（MissingHole) 14 侵姓過量（Overetch) 為能檢出上述該等缺陷，需要藉由建立標準圖型、影 像處理（例如：二值化處理）、精確對位、區塊分析、區 域檢測、缺陷彙集整理及缺陷分析結果輸出【請確認描述 是否正確】。然而，電路板之電源層及接地層之圖型與前 開線路層之圖型相差甚鉅，亦即各電源層或各接地層多包 5 201200868 含複數個大面積之銅猪區域，而非許多細小且複雜之繞線 (trace)及接塾（pad)。 目前自動化機器視覺設備業者仍以檢測線路層之程式 及步驟同樣來檢測電源層及接地層，因此顯然忽略兩者圖 型及缺陷種類之不同’故造成電源層及接地層之缺陷檢測 費時而降低印刷電路板之整個生產效益。 【發明内容】 本發明係供一種電路板之電源層及接地層之缺陷檢 測方法，其係針對電源層及接地層之圖型特性及及可能發 生之缺陷種類而設計之方法，因此可以大幅減少檢測所花 費之時間’並且仍維持高缺陷辨識率。 本發明係提供一種能應用於快速量產之缺陷檢測方法 ，其不需要精確之對位及繁複之圖型確認【請確認描述是 否正確】’就能擷取待檢之電源層或接地層之影像，故可 以採連續輸送之方式進行缺陷檢測，從而提昇印刷電路板 之整個生產效益。 綜上所述，本發明揭示一種電路板之電源層及接地層 之缺陷檢測方法。該方法要接受一電路板之鑽孔資料並 掃描該電路板中至少一電源層或至少一接地層之圖型為一 影像檔。比較該影像檔及該鑽孔資料，從而得到該電源層 或該接地層之圖型輪廓與該鑽孔資料中之一些鑽孔之位置 關係，其中該電源層或該接地層係位於一絕緣層上，且該 些鑽孔係設於該絕緣層中。 本發明之一範例係該電路板之鑽孔資料為一電路板佈 6 201200868 局之设計數據檔或鑽孔機用之程式檔。 下一待檢之電路板 本發明之一範例係另包含連續輸送 至被掃描處之步驟。 上文已經概略地敍述本揭露之技術特徵及優點，俾使 下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之 申請專利範圍標的之其它技術特徵及優點將描述於下文。 本揭露所屬技術領域中具有通常知識者應可瞭解，下文揭 示之概念與特定實施例可作為基礎而相當輕易地予以修改 或設計其它結構或製程而實現與本揭露相同之目的。本揭 露所屬技術領域中具有通常知識者亦應可瞭解，這類等效 的建構並無法脫離後附之申請專利範圍所提出之本揭露的 精神和範圍。 【實施方式】Label Defect Description 1 Hole Off (PinHole) 3 Open Circuit 4 1 Underetch 5 Mousebite 6 Missing Conductor 7 Highlights (Spur) 8 Short (Short) 9 Wrong Size Hole 10 Conductors too close 11 Spurious Copper 12 Excessive Short 13 MissingHole 14 Overetch is The above-mentioned defects can be detected by establishing standard pattern, image processing (for example: binarization processing), precise alignment, block analysis, area detection, defect collection and defect analysis result output [please confirm description is it right or not】. However, the pattern of the power layer and the ground plane of the circuit board is quite different from the pattern of the front open circuit layer, that is, each power layer or each ground layer is multi-packed 5 201200868, including a plurality of large-area copper pig areas, rather than many Small and complex traces and pads. At present, the automated machine vision equipment industry still detects the power layer and the ground layer by detecting the circuit layer's procedures and steps. Therefore, it is obvious that the difference between the two types of patterns and the types of defects is neglected, so that the defect detection of the power layer and the ground layer is time-consuming and reduced. The overall production benefit of printed circuit boards. SUMMARY OF THE INVENTION The present invention is directed to a method for detecting a defect in a power supply layer and a ground layer of a circuit board, which is designed for a pattern characteristic of a power supply layer and a ground layer and a type of defect that may occur, thereby being substantially reduced The time taken for the detection' and still maintain a high defect recognition rate. The invention provides a defect detecting method which can be applied to rapid mass production, which does not require accurate alignment and complicated pattern confirmation [please confirm whether the description is correct], and can obtain the power layer or the ground layer to be inspected. The image can be used for continuous defect detection to improve the overall production efficiency of the printed circuit board. In summary, the present invention discloses a method for detecting defects in a power supply layer and a ground layer of a circuit board. The method is to receive a drilling data of a circuit board and scan a pattern of at least one power layer or at least one ground layer of the circuit board as an image file. Comparing the image file and the drilling data to obtain a positional relationship between a pattern outline of the power layer or the ground layer and some of the holes in the drilling data, wherein the power layer or the ground layer is located in an insulating layer And the holes are provided in the insulating layer. An example of the present invention is that the drilling material of the circuit board is a circuit board cloth 6 201200868 design data file or a program file for the drilling machine. Next Circuit Board to Be Examined An example of the present invention further includes the step of continuously transporting to the scanned portion. The technical features and advantages of the present disclosure are summarized above, and the detailed description of the present disclosure will be better understood. Other technical features and advantages of the subject matter of the claims will be described below. It is to be understood by those of ordinary skill in the art that the present invention may be practiced as the basis of the invention. It is to be understood by those of ordinary skill in the art that this invention is not limited to the spirit and scope of the present disclosure as set forth in the appended claims. [Embodiment]

圖2係本發明一實施例之電路板之電源層或接地層之 示思圖。電路板2 0包含多個線路層（圖未示）、至少一電源層 及至少一接地層’圖中標號2 1及22分別為一電源層或一接 地層之第一導體區域（conductor region)及第二導體區域 (conductor region)。該第一導體區域21及該第二導體區域 22均為大面積之金屬層覆蓋區域，例如：銅箔，因此和線 路層之繞線及接墊之圖型（參見圖1)很明顯不同。 該第一導體區域21及該第二導體區域22係設於一絕緣 層26上’該絕緣層26包含複數個鑽孔24。若某些鑽孔24位 於該第一導體區域21及該第二導體區域22之範圍内，則該 第一導體區域21及該第二導體區域22會設計複數個開孔 201200868 23 1〜233以避開和該等鑽孔24重疊或過於靠近。因為該等 鑽孔24内會填銅作為積層（muhilayer)間垂直導通之部分， 所以遠第一導體區域21及該第二導體區域22之輪廓或開孔 23 1〜233之孔壁需要和該等鑽孔24有適當之距離以避面短 路之發生。 開孔231係一單純之圓形孔；開孔232係多個圓弧組合 在一起之封閉孔；開孔233係位於該第一導體區域21之邊界 之開放孔；又開孔234及235係兩多邊形之封閉孔。由於該 開孔234及235内並無任何鑽孔存在，故於此一實施例中可 以忽略該兩開孔234及235局部之影像，亦即不列為和鑽孔 資料比較分析之特定部分。 圖3係本發明一實施例之導體區域存在突出缺陷之示 思圖。一導體區域31中開孔33係環繞一鑽孔34，又該開孔 33有一突出部（spur〇rpr〇trusi〇n)35與該鑽孔34鄰接，因此 會造成短路之問題。本發明藉由擷取電源層或接地層之影 像，並和預先輸入之鑽孔資料比對後，就能正確挑出此類 突出缺陷，以避免短路之發生。 圖4係本發明一實施例之電源層或接地層之缺陷檢測 方法之流程圖。如步驟S41所示，該方法要接受一電路板之 鑽孔資料。該鑽孔資料可以是一電路板佈局之設計數據檔 ，例如：Gerber格式及0DB++格式之數據檔’或鑽孔機用 之程式檔，例如：CNC加工機之鑽孔程式檔及以“丨丨⑽格式 之鑽孔程式檔。或者，也可以取一視為標準之製作正確之 電路板，掃描後存為比對標準之影像檔，該影像檔中亦包 201200868 含該鑽孔資料，例如：鑽孔位置及孔徑。 如步驟S42所示，掃描該電路板中至少一電源層或至少 一接地層之圖型為一影像檔，其可以利用一般攝影機擷取 該電源層或該接地層之影像。藉由選擇適當照明光線之顏 色，可以使該電源層或該接地層之導體區域之影像亮度較 高，亦即高於之絕緣層或鑽孔之影像亮度。 如步驟S43所示，比較該影像檔及該鑽孔資料，例如： 該鑽孔資料中相關鑽孔位置和該影像檔重疊比較，從而得 到s亥電源層或該接地層之圖型輪廓與該鑽孔資料中之一些 鑽孔之位置關係，其中該電源層或該接地層係位於一絕緣 層上，且該些鑽孔係設於該絕緣層中。最後，自上述位置 關係中找出可能存在之缺陷，並彙整及輸出，如步驟S44 所示。 本發明之一範例係另包含連續輸送下一待檢之電路板 至被掃描處之步驟，亦即可利用輸送帶依序將複數個電路 板送至攝影機處，各該電源層或各該接地層會被--操取 影像並分析是否有缺陷存在。 本揭露之技術内容及技術特點已揭示如上，然而熟悉 本項技術之人士仍可能基於本揭露之教示及揭示而作種種 不背離本揭露精神之替換及修飾。因此，本揭露之保護範 圍應不限於實施例所揭示者，而應包括各種不背離本揭露 之替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1係一印刷電路板中線路層之佈線圖型之示意圖； 201200868 圖2係本發明一實施例之電路板之電源層或接地層之 示意圖； 圖3係本發明一實施例之導體區域存在突出缺陷之示 意圖；以及 圖4係本發明一實施例之電源層或接地層之缺陷檢測 方法之流程圖。 【主要元件符號說明】 1〜14缺陷 20 電路板 21 第一導體區域 22 第二導體區域 24 鑽孔 26 絕緣層 31 導體區域 33 開孔 34 鑽孔 35 突出部 231〜235開孔 10Fig. 2 is a view showing a power supply layer or a ground layer of a circuit board according to an embodiment of the present invention. The circuit board 20 includes a plurality of circuit layers (not shown), at least one power supply layer, and at least one ground layer. The reference numerals 2 1 and 22 in the figure are respectively a power supply layer or a first conductor region of a ground layer. And a second conductor region. The first conductor region 21 and the second conductor region 22 are both large-area metal layer covering regions, such as copper foil, and thus are distinct from the wiring pattern of the wiring layer and the pattern of the pads (see Fig. 1). The first conductor region 21 and the second conductor region 22 are disposed on an insulating layer 26. The insulating layer 26 includes a plurality of holes 24. If the plurality of holes 24 are located in the range of the first conductor region 21 and the second conductor region 22, the first conductor region 21 and the second conductor region 22 are designed with a plurality of openings 201200868 23 1 233 233. Avoid overlapping or too close to the bores 24. Since the holes 24 are filled with copper as a portion of the vertical conduction between the muhilayers, the contours of the first and second conductor regions 21 and 22 or the walls of the openings 23 1 to 233 need to be Wait for the borehole 24 to have an appropriate distance to avoid a short circuit. The opening 231 is a simple circular hole; the opening 232 is a closed hole in which a plurality of circular arcs are combined; the opening 233 is an open hole at a boundary of the first conductor region 21; and the opening 234 and 235 are Closed holes in two polygons. Since no holes are present in the openings 234 and 235, the image of the two openings 234 and 235 can be ignored in this embodiment, that is, it is not listed as a specific part of the comparative analysis with the drilling data. Fig. 3 is a view showing a prominent defect in a conductor region according to an embodiment of the present invention. The opening 33 in a conductor region 31 surrounds a bore 34, and the opening 33 has a projection 35 adjacent to the bore 34, thereby causing a short circuit problem. By extracting the image of the power layer or the ground layer and comparing it with the previously entered drilling data, the present invention can correctly pick out such protruding defects to avoid the occurrence of a short circuit. Fig. 4 is a flow chart showing a method of detecting a defect of a power supply layer or a ground layer according to an embodiment of the present invention. As shown in step S41, the method accepts drilling data from a board. The drilling data can be a design data file of a circuit board layout, for example, a data file of Gerber format and 0DB++ format or a program file for a drilling machine, for example, a drilling program file of a CNC machining machine and a "丨丨" (10) The drilling program file of the format. Alternatively, a circuit board that is regarded as a standard and manufactured correctly may be taken. After scanning, it is saved as a comparison image file. The image file also contains 201200868 containing the drilling data, for example: The drilling position and the aperture are as shown in step S42, and scanning at least one power layer or at least one ground layer in the circuit board is an image file, which can capture the image of the power layer or the ground layer by using a general camera. By selecting the color of the appropriate illumination light, the image brightness of the power layer or the conductor region of the ground layer can be made higher, that is, higher than the image brightness of the insulating layer or the hole. As shown in step S43, the comparison is performed. The image file and the drilling data, for example: the relevant drilling position in the drilling data and the image file overlap and comparison, thereby obtaining the pattern outline of the shai power layer or the ground layer and the drilling data a positional relationship of the holes, wherein the power layer or the ground layer is on an insulating layer, and the holes are disposed in the insulating layer. Finally, the possible defects are found from the positional relationship, and The integration and output are as shown in step S44. An example of the present invention further comprises the steps of continuously transporting the next circuit board to be inspected to the scanned portion, or sequentially feeding the plurality of circuit boards to the camera by using the conveyor belt. Wherein, each of the power layers or each of the ground planes will be imaged and analyzed for defects. The technical content and technical features of the disclosure have been disclosed above, but those skilled in the art may still be based on the disclosure. The present invention is not limited to the embodiment disclosed, and the scope of the present disclosure should not be limited to the embodiments disclosed herein. [Brief Description of the Drawings] FIG. 1 is a schematic diagram of a wiring pattern of a circuit layer in a printed circuit board; 201200868 FIG. 2 is an embodiment of the present invention. FIG. 3 is a schematic view showing a protruding defect of a conductor region according to an embodiment of the present invention; and FIG. 4 is a flowchart of a method for detecting a defect of a power supply layer or a ground layer according to an embodiment of the present invention; [Main component symbol description] 1 to 14 defect 20 circuit board 21 first conductor region 22 second conductor region 24 drilled hole 26 insulating layer 31 conductor region 33 opening hole 34 drilled hole 35 protruding portion 231 to 235 opening 10

Claims (1)

201200868 七、申請專利範圍： 1. 種電路板之電源層及接地層之缺陷檢測方法，包含下列 步驟： 接受一電路板之鑽孔資料； 掃描該電路板中至少一電源層或至少一接地層之圖钽 為一影像播； 比較該影像檔及該鑽孔資料’從而得到該電源層或該 接地層之圖型輪廓與該鑽孔資料中之一些鑽孔之位置關 係。 2·根據請求項1所述之電路板之電源層及接地層之缺陷檢測 方法’其中該電源層或該接地層係位於一絕緣層上，且該 些鑽孔係設於該絕緣層中。 3. 根據請求項1所述之電路板之電源層及接地層之缺陷檢測 方法’其另包含根據該位置關係判段出可能存在缺陷之步 驟。 4. 根據請求項3所述之電路板之電源層及接地層之缺陷檢測 方法，其另包含彙整該等缺陷而輸出之步驟。 5·根據請求項1所述之電路板之電源層及接地層之缺陷檢測 方法’其中該電路板之鑽孔資料為一電路板佈局之設計數 據檔或鑽孔機用之程式檔。 6. 根據請求項5所述之電路板之電源層及接地層之缺陷檢測 方法’其中該電路板佈局之設計數據檔係Gerber格式或 ODB++格式之數據槽。 7. 根據請求項5所述之電路板之電源層及接地層之缺陷檢測 方法，其中該鑽孔機用之程式檔係CNC加工機之鑽孔程式 檔或Excellon格式之鑽孔程式檔。 201200868 8. 根據請求項3所述之電路板之電源層及接地層之缺陷檢測 方法’其中該缺陷係該電源層或該接地層之圖型輪廓上之 一突出部’且該突出部與一鑽孔鄰接。 9. 根據請求項1所述之電路板之電源層及接地層之缺陷檢測 方法，其中該電源層或該接地層包含至少一個導體區域。 1 0.根據叫求項9所述之電路板之電源層及接地層之缺陷檢測 方法’其中該導體區域包含複數個開孔，部分該複數個開 孔内設有至少一鑽孔，又該部分個開孔之影像係選擇為比 較之對象。201200868 VII. Patent application scope: 1. The defect detection method of the power layer and the ground layer of the circuit board includes the following steps: accepting drilling data of a circuit board; scanning at least one power supply layer or at least one grounding layer in the circuit board The image is an image broadcast; the image file and the drill data are compared to obtain a positional relationship between the pattern profile of the power layer or the ground layer and some of the holes in the borehole data. The defect detecting method of the power supply layer and the ground layer of the circuit board according to claim 1, wherein the power supply layer or the ground layer is on an insulating layer, and the holes are provided in the insulating layer. 3. The defect detection method of the power supply layer and the ground layer of the circuit board according to claim 1 further includes the step of judging that there may be a defect based on the positional relationship. 4. The method for detecting a defect of a power supply layer and a ground layer of a circuit board according to claim 3, further comprising the step of outputting the defects and outputting. 5. The defect detection method of the power supply layer and the ground layer of the circuit board according to claim 1, wherein the drilling data of the circuit board is a design data file of a circuit board layout or a program file for the drilling machine. 6. The defect detection method of the power supply layer and the ground layer of the circuit board according to claim 5, wherein the design data file of the circuit board layout is a data slot of a Gerber format or an ODB++ format. 7. The defect detection method of the power layer and the ground layer of the circuit board according to claim 5, wherein the program file of the drilling machine is a drilling program file of a CNC processing machine or a drilling program file of an Excellon format. 201200868 8. The method for detecting a defect of a power layer and a ground layer of a circuit board according to claim 3, wherein the defect is a protrusion of the power layer or a pattern outline of the ground layer, and the protrusion and the protrusion The holes are adjacent. 9. The method of detecting a defect of a power supply layer and a ground layer of a circuit board according to claim 1, wherein the power supply layer or the ground layer comprises at least one conductor region. The method for detecting a defect of a power layer and a ground layer of a circuit board according to claim 9, wherein the conductor region includes a plurality of openings, and at least one of the plurality of openings is provided with at least one hole. Part of the image of the opening is selected as the object of comparison. 1212
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