TW201143412A - Solid-state imaging device and method of reading signals from the pixel array of solid-state imaging device - Google Patents

Abstract

Disclosed is a solid-state imaging device capable of reducing the column fixed pattern noise without being affected by electron diffusion or light leakage from the pixel array. A column signal processing circuit of a column signal processing unit in the solid-state imaging device generates an image signal and a reference signal from a pixel signal from the pixels and from a false signal from the reference circuit, respectively. The pixel signal and the false signal contain column fixed pattern noise of said column signal processing circuit. Because the signal processing unit performs difference processing on the image signal using the reference signal, said column fixed pattern noise decreases in the read signal. Because the false signal source does not contain photoelectric conversion elements, processing for decreasing the column fixed pattern noise is not affected by electron diffusion or light leakage from the pixel array.

Description

201143412 VI. Description of the Invention: [Technical Field] The present invention relates to a solid-state imaging device and a method of reading a signal from a pixel array of a solid-state imaging device. [Prior Art] Patent Document 1 describes a C Μ 0 S image sensor. In the c Μ 0 S image sensor, the imaging unit has an effective pixel portion and an invalid pixel portion. The effective pixel portion and the invalid pixel portion contain the same pixel circuit. An optical dark portion for fixing modal noise correction is provided in a part of the ineffective pixel portion. The amount of signal of each pixel obtained from the optical dark portion is measured, and the amount of the signal of the pixel of the optical dark portion is subtracted from the signal amount of the effective pixel portion. The subtraction is obtained by averaging processing to obtain the average pixel signal amount in the optical dark portion by the average 値, and subtracting the average 値 from the signal amount of each pixel of the effective pixel portion. [PRIOR ART DOCUMENT] [Patent Document 1] [Patent Document 1] JP-A-2008-236787 SUMMARY OF INVENTION [Problems to be Solved by the Invention] In the CMOS image sensor described in Patent Document 1, generation is performed. An optical dark portion is provided around the effective pixel portion of the image data. The optical dark part is a photoelectric conversion element, a transmission gate, and a floating diffusion -5 - 201143412, or a pixel including a transmission gate and a floating diffusion. The difference between the signal from the pixels in the optical dark portion and the signal from the pixels in the effective pixel portion is generated, and the fixed modal noise is cancelled. However, the solid-state imaging device of the CMOS image sensor causes the following problems. The pixels in the invalid pixels include a photoelectric conversion element, a transfer gate, and a floating diffusion covered by a light shielding film for shielding light. When the light is incident on the image pickup device, the light is not directly incident on the photoelectric conversion element in the optically dark portion of the invalid pixel, but is directly incident on the photoelectric conversion element in the effective pixel. According to the inventor's knowledge, the optical dark portion is affected by light leakage from the effective pixel portion or carrier diffusion through the substrate of the C Μ S image sensor. As mentioned above, the invalid pixels that are affected by light leakage or diffused electrons change their reference level with incident light, so they cannot assume the correct role of optical darkness. Therefore, optical darkness cannot be used to remove fixed modal noise. The effect of such light leakage on the ineffective pixels is more remarkable as the pixel size is smaller, especially in an image sensor using fine pixels. On the other hand, in fixed modal noise, it can be roughly divided into the following two categories. One is due to the fixed modal noise of the pixel circuit in the pixel (hereinafter referred to as "pixel fixed modal noise"), and the other is the fixed modal noise caused by the column circuit (below) It is called "column fixed modal noise" and is referred to). The pixel fixed modal noise is caused by the dark current of the photoelectric conversion element of the pixel, the enthalpy of the transistor of the pixel circuit, and the like. The column fixed modal noise is caused by a column circuit arranged in a column of the pixel array. The image signal from each column circuit reflects the characteristics of the column circuit used in the reading of the pixel signal corresponding to the signal -6-201143412. The column circuit arranged in the column of the pixel array is characterized by the difference in the electronic components in the column circuit, such as capacitors, transistors, amplifiers, etc., resulting in different characteristics of each column circuit. Therefore, the signal from a certain column circuit will have the noise inherent in the column circuit. For example, when no light is incident on the darkness of the pixel array with no variations, the difference between the read signals of each column circuit is due to the fixed-mode noise of the column. The present invention has been made in view of such circumstances, and an object thereof is to provide a solid-state imaging device capable of reducing vertical fixed-mode noise of a column without being affected by light leakage or diffused electrons from a pixel array, and another object is to provide a solid-state imaging device. A method of reading signals from a pixel array of a solid-state imaging device by reducing column fixed modal noise. [Means for Solving the Problems] One aspect of the present invention relates to a solid-state imaging device. The solid-state imaging device includes: (a) a pixel array including a pixel having a photoelectric conversion element and a pixel circuit for supplying a signal from the photoelectric conversion element; and (b) a reference signal generating unit disposed in the pixel On the outer side of the pre-recorded pixel array, there are one or a plurality of reference circuits 'the reference circuit includes a pseudo-signal source for reducing the fixed-mode noise of the column; and (c) the column signal processing unit includes the column signal processing The circuit 'is respectively used to generate the image signal and the reference signal according to the pixel signal from the pre-recorded pixel array and the pseudo-signal from the previous reference signal generating unit; and (d) the signal processing -7-201143412, which accepts the pre-recording signal and the pre-record Refer to the signal 'and generate a read signal. The pre-recorded pixel array includes a plurality of column arrays; the front column signal processing unit performs reading of the k-times (1 S k ) of the pre-recorded signals for each frame; the pre-recorded reference signal source of the reference circuit does not include The photoelectric conversion element and the floating diffusion unit; the pre-recording signal of the pre-signal processing unit is used to reduce the longitudinal fixed-mode modality caused by the pre-recording signal processing circuit by using the pre-recording reference signal The calculation of the signal is processed and generated. According to the solid-state imaging device, the column signal processing circuit generates the image capturing signal and the reference signal respectively based on the pixel signal and the pseudo-signal. Therefore, the camera signal and the reference signal may contain fixed-mode noise of the column caused by the column signal processing circuit. The signal processing unit performs the above-mentioned calculation of the image signal using the reference signal. Therefore, the column fixed modal noise caused by the column signal processing circuit is reduced in the read signal. Since the pseudo-signal source does not include the photoelectric conversion element and the floating diffusion portion, the reduction processing of the column fixed modal noise is not affected by the light leakage or diffusion electrons from the pixel array. Another aspect of the invention relates to a method of reading a signal from a pixel array of a solid state imaging device including a column signal processing circuit and a reference circuit. The method comprises: (a) reading a pixel signal from a pixel in the pixel array using a front column signal processing circuit to generate an image signal; and (b) using a front column signal processing circuit Performing a readout signal from the pre-recorded pixel array to reduce the readout of the pseudo-signal of the column fixed modal noise to generate a reference signal; and ( -8 - 201143412 C) by using the pre-reference signal And the step of recording the vertical column processing caused by the low-recording column signal processing circuit to generate the read signal. a pre-conversion component, and for providing from the photoelectric conversion circuit; the pre-reference circuit includes a source for generating a pre-signal; the pre-symmetric source includes no opto-electrical portion: the pre-column signal processing circuit is a pre-signal signal, At least one of the related double sampling and A/D conversion operations is performed. According to this method, the same column is used to generate the shots based on the pixel signals and the pseudo-signals. Therefore, the camera signal and the reference signal may contain vertical fixed-mode noise caused by the processing circuit. The camera signal is processed by the above-mentioned calculation, so the fixed-mode noise caused by the column is not reduced in the processing of the source of the analog signal without the photoelectric conversion element and the fixed-mode noise of the floating column. Or the effects of diffusing electrons. In the solids of the above-mentioned side of the present invention, the pre-recorded pixels in each column array are connected to the circuit system and may contain a switch for providing the front column line. The pre-recorded pixel circuit of the pre-recorded pixel is a control mechanism required for the signal of the photoelectric conversion element to be recorded before the pixel. A pixel-based pixel system for reducing fixed-mode noise has: a pixel-like signal of a photoelectric element, a pseudo-like component of a signal, and a floating diffusion pixel signal, and a pre-recorded, amplified, and sample-and-hold signal processing circuit. The signal and reference signals are such that the column signal is reduced by the reference signal and the column signal processing circuit number. Since the diffusing portion is provided, the light is leaked from the pixel array and the vertical line is in the method. For the pre-recording reference, the required signal is used to supply the pseudo-signal from the supply to the front column line. If the side is based on the above, the reference signal is supplied to the column line by means of a switch. Further, the pixel circuit supplies the pixel signal to the column line via the control mechanism. Therefore, the reference circuit can generate a pseudo-signal suitable for reducing the fixed-mode noise of the column. In the solid-state imaging device and method according to the above aspect of the present invention, the 'pre-column signal processing unit includes an array of pre-column signal processing circuits', each of which is connected to the pre-column column. The array 'previous reference signal generation unit includes an array of pre-referenced circuits. Each of the pre-referenced reference circuits is connected to the pre-column signal processing circuit; the pre-signal processing unit includes an arithmetic circuit for performing pre-calculation processing. The signal processing unit performs a process of generating a difference between the pre-recorded reference signal and the pre-recorded image signal for each of the preceding column signal processing circuits as a pre-calculation process, and the pre-recorded signal is generated using a pre-calculation circuit. According to the side of the above, each of the column signal processing circuits is electrically connected to the column array, and each of the reference circuits is electrically connected to the column signal processing circuit. In each column array, a column signal processing circuit and a reference circuit are provided. In this form, the image signal and the reference signal read by each column array contain the column fixed modal noise caused by the column signal processing circuit required for the column array. The signal processing unit can perform the above-mentioned calculation on the image signal by using the reference signal for each column array. In the solid-state imaging device and method according to the above aspect of the present invention, the pre-reference signal generating unit may include an additional reference circuit connected to the processing circuit of the pre-column signal 10.10-2011434. The pre-recording signal generation unit can perform the reading of the pre-symbol signal from the reference circuit and the reference circuit added in the foregoing. According to the above side, the pseudo-signals from the reference circuit and the additional reference circuit can be combined to generate a reference signal. Further, since the position of the reference circuit is different from the position of the additional reference circuit, the variations of these reference circuits can be averaged. The reading of the pseudo-signal from the reference circuit is performed at the same time as the reading of the pseudo-signal from the additional reference circuit, so that the reduction of the random noise is effective. In the solid-state imaging device and method according to the above aspect of the present invention, the 'front column signal processing unit' may include a correlated double sampling (CDS) circuit. The pre-recorded double-sampling circuit reads the pre-recorded pixel signal; the pre-recorded pixel signal contains the first signal level containing the noise component and the second signal level containing the signal component superimposed on the noise component; The pre-recording video signal indicates the difference between the first signal and the second signal. According to the side of the above, the fixed-mode noise caused by the vertical column of the CDS circuit can be reduced. The reset noise in the pixel circuit and the parallax of the transistor can be removed by the CDS circuit. In the solid-state imaging device and method according to the above aspect of the present invention, the pre-column signal processing unit may include an A/D conversion circuit for receiving an output signal from the pre-recorded double-sampling circuit. According to the side of the above, the vertical modal noise caused by the A/D conversion circuit can be reduced. The A/D conversion circuit provides digital reference signals and video signals. In the solid-state imaging device and method according to the above aspect of the present invention, the A/D conversion method in the A/D conversion circuit can be, for example, an integral type conversion, a tour type conversion, or a successive comparison type. Conversion and at least one of the combined conversion methods. According to the side of the above, the solid-state imaging device can be applied to the solid-state imaging device. The solid-state imaging device and method according to the above aspect of the present invention can include: the first and second capacitors. The calculation amplification circuit and the switching circuit required for changing the connection of the first capacitor, the second capacitor, and the preamplifier amplifier circuit. The pre-switching circuit can provide: the first connection is such that the first and second capacitors and the pre-calculated amplification circuit can perform correlated double sampling; and the second connection is used to increase the first and second capacitances and the pre-calculation increase. The circuit can perform a tour type a/D conversion. The pre-column signal processing circuit ’ is capable of performing pre-recorded double-sampling by the first connection, and performing pre-recorded A/D conversion by the second connection. According to the side of the above, the column fixed modal noise caused by the calculation amplification circuit, the first capacitor, the second capacitor, and the switch circuit can be reduced. In the solid-state imaging device and method according to the above aspect of the present invention, the 'previous pixel array, the pre-reference signal generating unit, and the pre-column signal processing unit' can be shrunk in a single semiconductor wafer. According to the side of the above, the signal processing unit is provided outside the semiconductor wafer. The present invention is not limited to the single-conductor wafer, and the signal processing unit can be provided in various forms. In the solid-state imaging device and method according to the above aspect of the present invention, the pre-recorded pixel array and the pre-reference signal generation are performed. Department, pre-column -12- 201143412 The signal processing unit and the signal processing unit' can be contracted in a single-semiconductor wafer. According to the side of the above, the read signal whose column fixed modal noise has been reduced can be supplied from the integrated circuit required for the solid-state imaging device. The above and other objects, features and advantages of the present invention will become more fully understood from [Effect of the Invention] As described above, according to the present invention, it is possible to provide a solid-state imaging device which can reduce the fixed-mode noise of the column without being affected by light leakage or diffused electrons from the pixel array. Further, according to the present invention, a method of reading a signal from a pixel array of a solid-state imaging device can be provided, according to which the vertical fixed-mode noise can be reduced. [Embodiment] The concept of the present invention can be easily understood by referring to the exemplified drawings and considering the following detailed description. Next, an embodiment of the solid-state imaging device of the present invention and a method of reading a signal from a pixel array will be described with reference to the accompanying drawings. Where possible, the same symbol will be indicated for the same part. Next, an amplitude-increasing solid-state imaging device using an amplification circuit in a pixel, and a method of removing the fixed modal noise will be described. The amplitude-amplified solid-state imaging device has a pixel with an amplification function and a scanning circuit disposed around the pixel, and the pixel data is read out from the pixel by the scanning circuit. Amplification type-13-201143412 An example of a solid-state imaging device is an APS (Active Pixel Sensor) consisting of a CMOS (Complementary Metal Oxide Semiconductor) that facilitates integration of pixels with peripheral driving circuits and signal processing circuits. ) Image sensor. An example of a pixel in an APS type image sensor is a 4-crystal type pixel in which high image quality can be obtained. The electro-crystalline system can be, for example, a MIS type or a MOS type. Further, the solid-state imaging device according to the embodiment is applicable to a camera device device. The camera device system includes the solid-state imaging device according to the embodiment. Fig. 1 is a view showing a block configuration of a solid-state imaging device of a so-called two-dimensional image sensor. The solid-state imaging device 1 includes a pixel array 3, a column signal processing unit 5, a reference signal generating unit 7, and a signal processing unit 9. In the solid-state imaging device 1, the pixels 11 are arranged in a matrix to constitute the pixel array 3. Pixels 11 are connected to column signal lines C, which form a column array. A specific line is selected from the rows of the respective pixels by the row decoder circuit 13a. The row driving circuit 14a provides a driving signal to the driving line 12. The drive line 12 represents the transfer transistor drive line, the reset transistor drive line, and the select transistor drive line. The reference signal generating unit 7 is selected by referring to the row selecting circuit 13b. The row driving circuit 14b supplies a driving signal to the driving line 25 to the reference signal generating portion. The drive line 25 indicates the reference row selection transistor drive line. The solid-state imaging device 1 can include a timing generation circuit 10 for generating control signals, clock signals, and the like necessary for controlling the operation timing of the circuits included in the device 1. The pixel array 3 and the array containing the pixels 11. Each of the pixels 1 1 includes a photoelectric conversion element 11a and a pixel circuit 1 1b with reference to FIG. Photoelectric conversion element -14- 201143412 1 1 a system may contain, for example, a photodiode. The photoelectric conversion element 丨丨a converts the received light L' into an electrical signal. The pixel circuit nb amplifies the signal S ( Ph ) from the photo-electric conversion element Π a to provide a pixel signal S ( pixel ). The pixel circuit 1 lb includes: a transmission transistor TR (TF) responsive to the transmission signal, a reset transistor TR (RS) responsive to the reset signal, an amplification transistor TR (AM), and a row selection signal The switching transistor TR (SW) responds. The pixel circuit 1 1 b includes a floating diffusion FD. The transmission transistor TR (TF) is connected to the gate receiving transmission signal and is connected between the photoelectric conversion element 11a and the floating diffusion portion fd. The transfer transistor TR(TF)' controls the transfer of charges from the photoelectric conversion element na to the floating diffusion FD. The reset transistor TR (RS) is connected to the floating diffusion FD' to reset the floating diffusion FD. The amplifying transistor TR (?) receives a signal from the floating diffusion portion fd at the gate, and is connected between the reference potential line Vdd which is the power supply line and the column line C. The switching transistor TR(SW)' is connected in series with the amplifying transistor TR (AM) and is connected between the reference potential line V d d and the column line C. The pixel circuit 1 1 b supplies the pixel signal S ( pixel ) to the column line C. The reference signal generating unit 7 is disposed independently of the pixel array 3. The reference signal generating unit 7 has one or a plurality of reference circuits 7a. Fig. 2 is a view showing the configuration of a reference circuit of the reference voltage generating unit. Referring to FIG. 2( a ), the reference circuit 7 a includes 'a switch for providing a pseudo-signal source PSD required for reducing fixed-mode noise of the column and a pseudo-signal S ( psd ) from the pseudo-signal source PSD'. For example, switching transistor TR (SW0). The pseudo-signal source PSD of the reference circuit 7a does not include the photoelectric conversion element 11a and the floating diffusion FD, and -15-201143412 is constituted by a transistor of a different element from the photoelectric conversion element 11a. The reference circuit 7a is a voltage source including a transistor TR (PSD) corresponding to an amplifying transistor, and a transistor TR (PSD) is connected to a voltage source as a power supply line Vdd, and a transistor TR (PSD) is connected It is between the reference potential line of the power line Vdd and the column line C. The transistor TR (PSD) and the transistor TR (SW0) are connected in series, and the node in which the transistor TR (PSD) and the transistor TR (SW0) are connected in common is biased via the transistor TR (PSD). Each of the transistors TR (SW0) and TR (PSD) can be constructed in the same manner as the transistors TR (SW) and TR (AM) in each of the pixels 11. High-precision column-fixed modal noise removal can be performed by matching the transistor properties such as the size, the shape, or the direction of the corresponding transistors. The vertical column signal processing unit 5 performs, for example, k times (1 $ k) of the pseudo-signal S (psd) for each frame. Referring again to FIG. 1, the column signal processing unit 5 receives the pixel signal S (pixel) sent from the pixel 11 in the pixel array 3 and the pseudo-signal S (psd) sent from the reference signal generating unit 7, and The image pickup signal S (img) and the reference signal S (ref) are respectively generated based on the pixel signal S (pixel) and the pseudo-signal S (psd). Further, the signal on the column line C is introduced to the column signal processing unit 5. The column signal processing unit 5 performs at least one of, for example, correlated double sampling, A/D conversion, amplification, and sample-and-hold operations on the pixel signals S (pixel) and the pseudo-signal S (psd). These processes can be analog or digital signal processing.

The signal processing unit 9 receives the image pickup signal S (img) and the reference signal S-16-201143412 (ref), and generates a read signal S (OUT). The read signal S (OUT) of the signal processing unit 9 is used to reduce the vertical fixed mode modality caused by the vertical column signal processing circuit 15 by using the reference signal S (ref). The calculation of the signal is processed and generated. In a preferred embodiment, the image signal S (img) and the reference signal S (ref) of the column signal processing unit 5 are digital signals formed by a predetermined number of digits. The signals of each of the image pickup signals S (img) and the reference signal S (ref) are supplied to the signal processing unit 9. In an example of the solid-state imaging device 1, the signal for each column is supplied to the horizontal signal line 17, for example, by the column decoder circuit 16, and is outputted to the outside of the semiconductor element or the sensor block. When necessary, the column signal processing unit 5 may include a column decoder circuit 16 and a horizontal signal line 17. According to the solid-state imaging device 1, the column signal processing circuit 15 generates the image pickup signal S(img) and the reference signal S(ref) based on the pixel signal S (pixel) and the pseudo-signal S (psd), respectively. Therefore, the pixel signal S (pixel) and the pseudo-signal S (psd) may be included in the vertical column modal noise caused by the column signal processing circuit 15. The signal processing unit 9 performs the above-described calculation processing on the image pickup signal S (img) using the reference signal S ( ref ). Therefore, the fixed-mode noise of the vertical column is reduced in the read signal S (OUT ). Since the pseudo-signal source PSD does not include the photoelectric conversion element 11a and the floating diffusion FD, no shading is required, and the reduction processing of the column fixed modal noise is not caused by light leakage or diffusion of electrons from the pixel array 3. influences. The description of the strategy is as follows. Assumption: -17- 201143412 Camera signal: s ( img) = S1 + N1 ; Reference signal: S ( ref) = R1 + N1 : Reference signal: S ( ref_OB ) = R_OB + N 1 + N_OB ; The signal S (OUT) is generated by a signal indicating a difference between the image signal S(img) and the reference signal S(ref), and S1 is a portion generated by the column signal processing circuit according to the pixel signal S (pixel); R1: The portion of the column signal processing circuit generated according to the pseudo-signal S (psd): N 1 : the column-fixed modal noise inherent in the column signal processing circuit; Ν1_ΟΒ: noise caused by light leakage or diffusion of electrons. S ( OUT ) = S ( i mg ) - S ( ref) = S 1 - R1 Thus, the column fixed modal noise is removed. When using the reference signal S ( ref_OB ) obtained by optical darkness, S ( OUT ) = S ( img ) -S ( refOB) = S 1 -R OB + N_OB ; thus, although the column fixed modal noise is removed However, it will be heavy noise caused by light leakage or diffused electrons inherent in optical darkness. The reference circuit 7a is not limited to the specific circuit shown in _ 2 ( a ), and may be used to match the transistor characteristics such as the size and pattern of the transistors TR ( SW ) and TR ( AM ) in the pixel 1 1 . Other circuits 7b, 7c. Fig. 2 (b) is an illustration of another example of the reference circuit. Reference circuit 715 -18-201143412 includes a pseudo-signal source PSD required to reduce the fixed-mode noise of the column, and a switching transistor TR (SW0) from the pseudo-signal S (psd) of the pseudo-signal source PSD . The reference circuit 7b uses two transistors 24, TR (PSD) to generate a pseudo-signal S (psd). Each of the transistors TR (SW0), 24, and TR (PSD) can have the same structure as the transistors TR (SW), TR (RS), and TR (AM) in the pixel circuit 1 1 , respectively. It is preferable to make the geometric size and direction uniform in accordance with the current-voltage characteristics of the corresponding transistor. In the circuit 7b, the gate 27 of the transistor 24 is connected to a fixed potential (e.g., Vdd line). The gate of the transistor TR (PSD) is always biased from the turned-on transistor 24. Fig. 2 (c) is a diagram showing still another example of the reference circuit. In the reference circuit 7c, the gate of the transistor TR (PSD) is connected to the voltage source 29. The pseudo-signal source PSD includes a voltage source 29 and a transistor TR (PSD). The voltage source 29 is configurable in the reference circuit 7c. The set potential of the voltage source 29 can individually set the reference voltage level for each reference circuit 7c in accordance with the tendency of noise. Therefore, the reference voltage level can be set to match the characteristics inherent in the vertical column. Figure 3 is a drawing of an array of reference circuits. The reference signal generating unit 7 may include an array 2 1 of reference circuits. The reference circuit 7d contains transistors TR (SWO) and TR (PSD). The gate 33 of the transistor TR (PSD) is connected to a voltage source 32 for supplying a reference voltage in common in the row direction. The voltage source 3 2 can be placed in the solid-state imaging device 1. It may be supplied from the outside of the solid-state imaging device 1 as necessary. The set potential of the voltage source 32 is set by the level of the voltage source on the column line C. References so far 19-201143412 Roads 7a, 7b, 7c, 7d can be configured for each column. Although it is exemplified that the reference circuits 7a to 7d can be arranged for each column, these reference circuit pairs can be arranged for every plurality of rows. Alternatively, a single reference circuit may be provided in the solid-state imaging device 1 to share all of the column signal processing circuits. Further, the physical positions of the reference circuits 7a, 7b, 7c, and 7d are not particularly limited. If necessary, the reference circuits 7a, 7b, 7c, and 7d may be disposed at the inner and outer sides of the column signal processing circuit. The nodes in the reference circuits 7a, 7b, 7c, and 7d may be directly connected by a voltage source, or It is biased by a conducting transistor. The pixels used in the solid-state imaging device 1 according to the present embodiment are not limited to the pixels 11 shown in Fig. 1 . The transmission transistor TR (TF) in the pixel 11 can be omitted, and the photoelectric conversion element 1.1a is directly connected to the gate of the amplification transistor TR (AM). The pixel thus arranged has a three-crystal type pixel configuration. The photoelectric conversion element 11a is composed of, for example, a photodiode, and the optical one-pole system can be fabricated by the same tantalum process as that used for the circuit element in the solid-state imaging device 1. However, in the manufacture of the solid-state imaging device 1, another process (for example, a compound semiconductor such as GaAs) can be applied. Further, the 'photoelectric conversion element 11a can be used, and a-Si or a photoconductive film belonging to an organic film laminated on a pixel readout circuit in a solid-state imaging device can be used. In the three-crystal type pixel, the floating diffusion FD is first set to the reset potential by resetting the transistor. Thereafter, the signal charge 'obtained by photoelectric conversion' is accumulated in the floating diffusion FD. After this accumulation, the potential of the floating diffusion FD is amplified by the amplification transistor TR (AM) and supplied to the column line c as a signal potential via the switch T R (S W ). -20- 201143412 Then, immediately afterwards, the floating diffusion FD is reset by resetting the conduction/non-conduction action of the transistor TR (RS). At the time of this reset, the potential of the floating diffusion FD is amplified by the amplification transistor TR ( AM ) in the same manner as the signal potential, and supplied to the column line C as the reset potential via the switch TR (SW 0 ). . In the pixel of the 4-transistor type and the 3-transistor type, the pixel signal S (pixel) contains the first signal level containing the noise component and the second signal bit containing the signal component overlapping the noise component. quasi. The image sensor according to the present embodiment can be applied to other amplification type pixels such as a 5-transistor type pixel, in addition to the 4-transistor type pixel or the 3-transistor type pixel. Fig. 4 is a view showing an example of a columnar signal processing circuit for a solid-state imaging device according to the present embodiment. The column signal processing circuit 15 may include a related double sampling (referred to as "CDS" and reference) circuit 31. The correlated double sampling circuit 31 reads out the pixel signal S (pixel) and the pseudo-signal S (psd). The pixel signal S (pixel) includes a first signal level S1 containing a noise component and a second signal level S2 containing a signal component superimposed on the noise component. The camera signal S (img) is the difference between the first signal and the second signal. By means of correlated double sampling, it is possible to remove, for example, the reset noise of the pixel circuit or the enthalpy of the transistor. The correlated double sampling circuit 31 includes switches 33a and 33b, capacitors 35a and 35b, and a calculation amplifier circuit 37. An input (negative input) 37a of the arithmetic amplification circuit 37 receives a signal from the input VIN via the serially connected switch 33a and the capacitor 35a, and the other input (positive input) 37b of the arithmetic amplification circuit 37 is shared. Reference signal (VC0M). Between the input 37a of the arithmetic amplification circuit 37 and the output 37c of the arithmetic amplification circuit 37, a switch 33b and a capacitor 35b are connected. The output VOUT receives the signal from the output 37c of the calculation amplifier circuit 37. The switch 33a controls the input operation of the signal, and the switch 33b controls the reset operation. When the reset potential is output from the pixel 11, the switches 33a, 33b are set to be closed, and the reset level S1 is taken up in the capacitor 35a. Next, the switch 33a is held in a closed circuit to open the switch 33b, and the signal level S2 from the pixel 11 is extracted in the capacitor 35a. Since the switch 33b is turned off, a difference (e.g., S1-S2) between the reset level S1 and the signal level S2, i.e., analog CDS result, is generated at the output 37c of the arithmetic amplification circuit 37. In the solid-state imaging device 1, a CDS circuit 31 arranged in a vertical column may be included for each of the column arrays. Even if the signal sent from each pixel of the column array is constant, in the result of the analog CDS, the characteristics of the capacitors 35a, 35b or the arithmetic amplification circuit 37 may be different, resulting in slight differences in each column. It became a fixed modal noise in the column. According to this embodiment, the column-fixed modal noise resulting from the analog CDS circuit can be reduced. Fig. 5 is a view showing another example of the column signal processing circuit for the solid-state imaging device according to the embodiment. The column signal processing circuit 15 can include a CDS circuit 31 and an A/D conversion circuit 41. The A/D conversion circuit 41 receives the signal from the CDS circuit 31. The A/D conversion circuit 41 performs A/D conversion on the analog CDS result to generate a first digital signal (digital video signal) S (ADC 1). After the analog signals are generated by the signals SI and S2 from the pixel 11, the selection switch TR (SW) of the pixel 1 1 is turned off, and the column array of the pixel array 3 is cut away from the column line C. Thereafter, the selection switches TR (SWO) in the reference circuits -22-201143412 7a to 7d in Figs. 2 and 3 are turned on, and the reference circuits 7a to 7d are connected to the column line C. The CDS circuit 31 sets the switches 33a, 33b to be closed, and the pseudo-signal S (psd) is captured in the capacitor 35a. Thereafter, the holding switch 33a is closed and the switch 33b is turned off. Thereby, the CDS circuit 31 generates a signal required to establish a reference signal S (ref) associated with the pseudo-signal S (psd). The A/D conversion circuit 41 receives the pseudo-signal S (psd) via the CDS circuit 31. When the CDS circuit 31 reads the pseudo-signal S (psd), the A/D conversion circuit 4 1 extracts the signal on the output 37c of the arithmetic amplification circuit 37 into a pseudo-signal level. The A/D conversion circuit 41 performs A/D conversion on the pseudo-signal level to generate a second digital signal (digital video signal) S (ADC2). When the first and second AD conversion results thus generated are subtracted by the digital processing field in the signal processing unit 9, slight differences in each column are canceled, and it is possible to generate a good modal noise without vertical column. The image signal S (OUT)» The A/D conversion circuit shown in Fig. 5 can be applied to various types such as an integral type, a patrol type, a successive comparison type, and a combination type thereof. Further, in the above, the operation of connecting the reference circuits 7a to 7d to the vertical line C is performed after the analog CDS result is generated, but may be performed before the analog CDS result is generated. According to the above embodiment, the vertical fixed mode modal noise caused by the CDS circuit 31 and the A/D conversion circuit 41 can be reduced. The A/D conversion circuit 41 provides a reference signal and an image signal in digital form. Further, the column signal processing circuit 15 may not include the CDS circuit 31, but may include an A/D conversion circuit 41. Specifically, the column signal processing circuit 15 may include an A/D conversion circuit -23-201143412. When an array of A/D conversion circuits is provided in the vertical column of the pixel array 3, for example, a patrol type A/D converter, a more efficient circuit configuration can be provided. The roving A/D converter provides A/D conversion and provides CDS action as needed. Fig. 图 is a view showing still another example of the column signal processing circuit for the solid-state imaging device according to the embodiment. The column signal processing circuit shown in Fig. 6 can be configured as a circuit for performing CDS operation, amplification operation, and A/D conversion operation using a single amplifier. The column signal processing circuit 5 includes a tour type A/D conversion circuit 51. The patrol type A/D conversion circuit 51 may include first and second capacitors 43a and 43b, an arithmetic amplification circuit 45, a switch circuit 47, a D/A conversion circuit 48, and a comparator 49 (49a, 49b). Between an input 45a and an output 45c of the arithmetic amplification circuit 45, a reset switch 238 and a capacitor 43b of the switch circuit 47 are connected. Between an input 45a and an output 45c of the arithmetic amplification circuit 45, a capacitor 43a connected in series and a switch 234 of the switch circuit 47 are connected, and another input 45b of the arithmetic amplification circuit 45 is connected to Common reference signal VC0M. One end of the capacitor 43a is connected to the reference signal VC0M line via the switch 236, and is connected to an input 45a of the arithmetic amplification circuit 45 via the switch 235 of the switch circuit 47. The other end of the capacitor 43a is connected to the D/A conversion circuit 48, is connected to the input VIN line via the switch 232 of the switch circuit 47, and is connected to the arithmetic amplification circuit 45 via the switch 23 of the switch circuit 47. Output 45c. The D/A conversion® circuit 48 system includes switches 240, 241, and 242, and the switches 240, 241, and 242 of the switch circuit 47 are responsive to the signals φ ΜΙ, Φ 〇 1, Φ ρι from the comparator 49, and function as D/A conversion circuits. The voltage signals VRM, VC0M, and VRP are switched. -24- 201143412 Switch circuit 47 (switches 232, 23 4, 23 5, 236, 23 8 ) changes the connection ′ of the first capacitor 43a, the second capacitor 43b, and the arithmetic amplifier circuit 45. The switch circuit 47 can form a first connection in which the connection between the first and second capacitors 43a and 43b and the calculation amplifier circuit 45 can perform a correlated double sampling operation, and the first and second capacitors 43a can be formed. The connection between the 43b and the arithmetic amplification circuit 45 enables the second connection of the patrol A/D conversion circuit. The column signal processing circuit 5 performs correlated double sampling by the first connection and performs a tour type A/D conversion by the second connection. According to this embodiment, the column-fixed modal noise caused by the first capacitor 43a, the second capacitor 43b, the arithmetic amplification circuit, and the switch circuit 47 can be reduced. The CDS operation in the circuit shown in Fig. 6 can be performed by the switch circuit 47 forming the same component connection as the C D S circuit of Fig. 4. The connection method required for the CDS operation in the switch circuit 47 is specifically as follows. When the reset potential level S1 is output from the pixel 11, 'the switches 23 2, 23 5, 238 are set to be closed, and the reset level is extracted in the capacitor 43a. Next, the switches 23 2, 23 5 are kept closed, the switch 23 8 is turned off, and the signal potential level S2 is extracted from the pixel 11 in the capacitor 43a, whereby on the output 45c of the arithmetic amplification circuit 45, The difference between the reset level S1 and the signal level S2 can be obtained, that is, the analog CDS result. However, during this action, the switches 234, 263 must always remain open. For the signal on the output 45c of the arithmetic amplification circuit 45, 1.5-bit A/D conversion (sub A/D conversion) is performed with two comparators 49a '49b. Use the result to perform the calculations required for the next digit A/D conversion. For this calculation, the switches 234, 236 are set to be closed so that the capacitor 43a (C1) is connected to the output 45c of the amplification circuit 45, and all other switches are turned off. Thereafter, the switches 2 34, 23 6 are turned off to connect one end of the capacitor 43a ( C1 ) to the D/A conversion circuit 48, and the other end of the capacitor 43a (Cl) is connected to the calculation via the switch 23 5 . When the input 45a of the amplifying circuit 45 is turned on, the switches 240, 241, and 242 are all turned ON to generate a 1.5-bit A/D-converted residual signal. The residual signal is stored in capacitors 43a, 43b. For the residual signal, perform the calculation required for the next digit A/D conversion. Repetitive residual generation and A/D conversion are repeated until the required number of times. By using the A/D conversion circuit 51 shown in FIG. 6 in the column signal processing circuit 15, the CDS circuit can be integrated with the A/D converter, and can be operated equivalently to the circuit shown in FIG. In addition, in the A/D conversion operation, the relationship of capacitance (C1=C2) is obtained. On the other hand, the column signal processing circuit 5 provides an amplification function together with the CDS function in accordance with the ratio of capacitance (C1/C2) at the time of the CDS operation performed before the A/D conversion. In the solid-state imaging device 1, the pixel array 3, the column signal processing unit 5, and the reference signal generating unit 7 can be shrunk to a single semiconductor wafer. At this time, since the signal processing unit 9 is provided outside the semiconductor wafer, the signal processing unit can be provided in various forms without being contracted in a single semiconductor wafer branch line. Alternatively, in the solid-state imaging device 1, the pixel array 3, the column signal processing unit 5, the reference signal generating unit 7, and the signal processing unit 9 can be contracted to a single semiconductor wafer. At this time, the read signal in which the column fixed modal noise has been lowered can be provided from the integrated circuit required for the solid-state imaging device. A few examples of the driving method of the solid-state imaging device will be described with reference to Figs. 7 and 8 . In these examples, the signal processing unit 9 accepts the digital -26-201143412 reference signal and the digital video signal. Fig. 7 is a view showing an example of a solid-state imaging device and a reading method thereof. The 1H period of one frame of the pixel array 3 may include the first period 61a and the second period 6 1 b. In the first period 61 1 a, one pixel signal s ( p i X e 1 ) is read out from the pixel 11 of the pixel array 3. In the second period 6丨b, the pseudo-signal S (psd) is read from the reference signal generating unit 7. In each of the 1 Η periods, the pixel signal S (pixel) sent from the pixel 1 一行 of one line of the pixel array 3 is read. Also, during the 1H period, the pseudo-signal S (psd) is read out in all of the column arrays. In a frame of the pixel array 3, the reading of the pixel signal s (p i X e 1 ) of one line and the reading of the pseudo-signal S (psd) are performed interactively. Therefore, the pseudo-signal S (psd) is read every iH period, so the image signal S (img) of each row of the pixel array 3 can be calculated using the pseudo-signal S (psd) updated every 1H period. deal with. Since the random noise of the pseudo-signal S (psd) is different for each line of the image signal S (img), the generation of fixed modal noise due to random noise can be avoided. The pixel signal S (pi X e 1 ) read from the pixel array 3 is stored in the memory circuit as a line memory in the readout of the pseudo-signal S (psd) (circuit 55a of FIG. 9(a)). )in. During the iH period, after the reading of the imaging signal S (img) and the reference signal S (ref) is completed, the imaging signal S (img) is taken from the memory circuit (circuit 55a of FIG. 9) in the signal processing unit 9. The reading 'generates a signal corresponding to the difference between the imaging signal S (img) and the reference signal S (ref). The signal processing unit 9 includes an arithmetic circuit for performing such arithmetic processing (circuit 55b of Fig. 9(a)). Therefore, generating a signal indicating a difference for -27-201143412 uses a memory circuit (e.g., circuit 55a) that is a line memory. Normally, the averaging processing of the reference signal s (ref) is not performed so that the processing can be smoothly performed, but when only one-frame still image shooting or the like is obtained, the averaging processing of the reference signal S (ref) is performed. More ideal. In this form, when the first period 61 a is after the second period 6 lb in the period of 1H, the memory signal 55a stores the pseudo-signal s ( psd ), and the other is the second period during the 1 Η period. The period 6 1 b is after the first period 6 1 a, and the pixel signal s ( pi X e 1 ) is stored in the memory circuit 55 5 a. Therefore, when the pixel signal S (pixel) is treated the same as the pseudo-signal S (psd), the two are equivalent. Further, when the allowable signal amplitude of the pseudo-signal S ( p s d ) can be reduced as compared with the pixel signal S (pixel), the capacity of the former memory circuit 55a (the number of bits at the time of digits) can be reduced. Fig. 8 is a view showing another example of a solid-state imaging device and a reading method. The one or two cells of the pixel array 3 include a plurality of first 1H periods 63a and a single second one 1 period 63b. In the first 1H period 63a, the pixel signal S (pixel) sent from the pixel 11 of the pixel array 3 is read. In the second one of the periods 63b, the pseudo-signal S (psd) sent from the reference circuit 7a is read. The reading of the pseudo-signal S (psd) from the reference circuit 7a is performed in a single 1H period 63b, so that the frame rate can be increased. The averaging processing of the reference signal S (psd) is not performed except when necessary, and the processing can be smoothly performed. Referring to Fig. 8(a), the 2nd 1 period 63b is located at the end of the one frame. The calculation processing of the image signal S (img) of the SI grid can be performed by using the reference signal S ( r e f ) of the previous frame -28 - 201143412. This form is performed using a megapixel circuit (circuit 56a of Fig. 9(b)) which is a line memory. The memory circuit (circuit 56a of FIG. 9(b)) ' stores a common reference signal S ( ref )' and will sequentially input the image signal S (img), using a common reference signal S ( ref ) The processing circuit (the circuit 56b of FIG. 9(b)) performs processing. Alternatively, the calculation processing of the image signal S(img) of a frame can be performed by using the frame reference signal s (ref). . This form is performed using a memory circuit (circuit 5 7 a of Fig. 9 (c)) which is a picture frame. The memory circuit (circuit 57a of FIG. 9(c)) 'stores the image signal S (img) of a pixel array portion read out before, and uses the common reference signal S (ref) read after use, The stored image pickup signals are sequentially processed by an arithmetic circuit (circuit 5 7b of Fig. 9(c)). Referring to Fig. 8(b), the second one is located at the beginning of the one frame. The calculation of the image signal of the picture frame can be performed using the reference signal read out during the first 1 frame period. This form is performed using a memory circuit (circuit 5 5 a of Fig. 9 (a)) which is a line memory. In this embodiment, the reference signal system is not changed in the entire frame, and is a common 値. The memory circuit stores the common reference signal, and the image signals sequentially input are processed by a calculation circuit (circuit 55b of Fig. 9(a)) using a common reference signal. The 2nd Η period may also be located away from the beginning and end of the frame. Except for the special needs, the averaging process of S ( ref ) No. -29-201143412 is not performed, and the processing can be smoothly performed. When necessary, the column signal processing circuit 7 can perform a plurality of readings of the pseudo-signal S (psd) of the reference circuit 7a. According to the side of the above, reading the pseudo-signal S (psd) from the reference circuit 7a at a plurality of times is performed at different timings, so that the reduction of random noise is effective. Further, when necessary, the reference signal generating unit 7 may include an additional reference circuit (referred to as "additional reference circuit 7a") having the same configuration as that of the reference circuit 7a. This additional reference circuit 7a is connected to the column signal processing circuit 5. The reference signal generating unit 7 can read the pseudo-signal S ( psd ) from the complex reference circuit 7a to perform a combination (for example, averaging) of the pseudo-signals S ( psd ) from the reference circuit 7a and the additional reference circuit 7a. The reference signal S ( ref ) is generated. Further, since the position of the reference circuit 7a is different from the position of the additional reference circuit 7a, the variations of these reference circuits 7a can be averaged. The reading of the pseudo-signal S (psd) from the reference circuit 7a is performed at a different timing from the reading of the pseudo-signal S (psd) from the additional reference circuit, so that the reduction of the random noise is effective. Fig. 1 is a view showing still another example of the lanthanum solid-state imaging device and the reading method. In the solid-state imaging device 1 and the reading method, one frame of the pixel array 3 may include m first 1H periods 67a and k second 1H periods 67b. In each of the first one period 67a, the pixel signal S (pixel) sent from the pixel 1 1 of the pixel array 3 is read. In the second 1st period 67b, the readout signals S (psd) and the 1st 1H period 6 7a sent from the reference circuit 7a are successively arranged. The kth 2nd Η period 67b is continuously arranged. The reference signal S (re f ) in the k 2nd 1st 6 period 6 7 b is averaged. • 30- 201143412 The average random noise is reduced to l/sqrt (k). Here, sqrt is the calculation of the square root. The 2nd Η period 6 7b can be arranged continuously at the beginning of the one frame. In this case, the average value of the reference signal S ( ref ) read in the k 1 Η period 67b can be used to calculate the image signal S (img) to calculate the circuit (Fig. 1 1 (a) Circuit 5 8 a) to carry it out. The average 値 generation of the reference signal S ( ref ) can be performed by averaging the 値 circuit (circuit 58b of Fig. 11 (a)). The 2nd Η period 6 7b is arranged continuously at the end of the one frame. In this case, the average 値 of the reference signal S ( ref ) read out in the k 1 Η period 67b in the previous frame can be used to calculate the image signal S ( img ) of the frame. The calculation circuit (circuit 5 8a of Fig. 1 1 (a)) is carried out. The average 値 generation of the reference signal S ( ref ) can be performed by an average 値 circuit (circuit 58b of Fig. 11 (a)). This average 値 is saved across the entire frame. Alternatively, after the image signal S (img) in the frame is stored in the memory circuit of the frame memory (circuit 51 9b of FIG. 11 (b)), k first period periods in the frame are generated. The average 値 of the reference signals read in . Using this average 値', the arithmetic processing of the image pickup signal stored in the circuit (e.g., circuit 5 9 b of Fig. 11 (b)) is performed by an arithmetic circuit (circuit 59a of Fig. 11 (b)). The average 値 generation of the reference signal S (ref) can be performed by an average 値 circuit (circuit c (b) of circuit 59c). When using a circuit that generates an average 値, in the average 値, reference signal -31 - 201143412 The random noise contained in it will be reduced. Further, when the reading number k of the pseudo-signal 3 (1?3 £1) is smaller than the number of rows η, the frame rate can be increased. The reading of k times has the following forms: (a) repeating the same reference circuit; (b) sequentially reading the different reference circuits; and (c) reading the pseudo-signals by the desired combination of these. As described above, in the solid-state imaging device 1 and the reading method, the column signal processing unit 5 can perform pre-recording of the pseudo-signal for each frame (i). <k) song out. The signal processing unit 9 may also include an average chirp generating circuit that performs an averaging process of the reference signal S ( ref ) to generate an average chirp. The read signal S (OUT) is the difference between the average value of the image signal S (img) and the reference signal S (ref). Fig. 12 is a view showing still another example of the solid-state imaging device and the reading method. As shown in FIG. 12, in the solid-state imaging device 1 and the reading method, the signal processing unit 9 may include a digital filter which is a reference signal S(ref) of the full column in the column signal processing unit 5. Each is processed across the m-frame to generate an average 每 for each column. If the digital filter processing is used for averaging, the fixed modal noise of the column can be reduced without damaging the frame rate. In one example of the averaging process, the signal processing unit 9 performs averaging processing over the most recent continuous m-frame before the n-th frame (n>m) to generate an average 値. By averaging across the nearest m-frame, the effects of slow-changing noise can be reduced. When the reference signal S ( ref ) is averaged across the complex frame, the average random noise is reduced by Ι/sqrt ( m ) by referring to the random noise contained in the signal S ( ref ). In the nth frame, the praise signal S (OUT) is generated using the average 値 across the nearest -32-201143412 m frame. Further, in another example of the averaging process, the signal processing unit 9 performs averaging processing across the continuous first m-frame from the first frame to the m-frame to generate an average 値. When the reference signal S ( ref ) is averaged across the complex frame, the average random noise is reduced by 1/sqrt(m) by referring to the random noise contained in the signal S ( ref ). In the nth (n>m + 1) frame, the read signal s(OUT) is generated using a fixed average 値. The averaging process across the complex frames is performed, for example, as follows. Reference signals RF ( 1 ) to RF ( m ) for the first to mth frames, RF ( 1 ) — AV ( 1 ) (AV ( i-1 ) + RF ( i ) ) /2 — AV ( i ) (2 < i ^ m ) This is done. When necessary, the same processing can be performed even after the (m + 1)th. This processing is provided using the signal processing section shown in FIG. Fig. 13 (a) shows an example of a system composed of hardware of a digital filter. The signal processing unit 9 of the solid-state imaging device 1 includes a digital filter 60 suitable for the digital reference signal S ( ref ), and a digital image pickup signal S (img ) using the average 値AV from the digital filter 6〇a. The calculation circuit of the subtraction process 6 〇b. Fig. 1 3 (b) shows an example of the connection of the digital filter circuit. The digital filter circuit adds the filter output yn to the delay signal D, and the output of the calculator ALU is added by the adder ADD1 to generate the next filter output, and the signal yn^ is calculated by the calculator ALU. The input side subtracts the filter from the filter input Xn-33-201143412 The output yn.i (adds the complement of the filter output yn-i to the filter input calculator ADD2), and generates the input signal to the calculator a. At the beginning of the wave calculus calculation, by inputting the appropriate initial X (init) tool MUX to the filter circuit, the calculation speed at which the average 値 is obtained using the filter can be greatly improved. Even if the number of powers of 6 is taken as 2 (for example, 2_δ = 0. 015625), it becomes easy on the hard body, and it is possible to use a coefficient on a hard body such as a parallel translator. Therefore, it is possible to realize a small-sized, high-speed, and compatible hardware. A transfer function indicating the filter characteristics of the digital filter circuit can be used, for example, as follows: H ( z ) = a / (l - (la) χζ · 1) The average 値 can be obtained by applying feedback by a digital filter. . This transmission represents the IIR filter. These are the inputs that are mixed one by one with a ratio a, and Fig. 14 is a diagram of an example of the characteristics of the IIR filter. By using a smaller 値 such as a = 0.01, an average 高精度 of high precision is obtained. The time-normal frame of the LPF caused by the above-mentioned conveyance function is not as follows: r = -1/ln ( 1-a) When a=0.01, the ratio is r = 99, and the filter output is at 100. Will be stable. Figure 15 is a diagram showing the main steps of reading a signal from a pixel array of a solid-state imaging device. In step S1 0 1 , the reading of the pixel signal S (pixel) sent from the pixel array 3 is performed using the vertical X n . The filter passes through the low-pass number a to achieve the change of the H (z)-rich function of the low-pass, for example, the number of pairs, in the subsequent method of the image field signal -34-201143412 processing circuit 15 is performed to generate an image signal S (img). In step S102, the reading of the pseudo-signal S (psd) for reducing the fixed-mode noise of the column is performed by using the column signal processing circuit 15 to generate the reference signal S(ref). In step 1〇3, the calculation process for reducing the fixed-mode noise of the column caused by the column signal processing circuit 15 is performed by using the reference signal S (ref) for the image signal S (img). A read signal S (OUT) is generated. According to this method, the same vertical column signal processing circuit 15 is used to generate the image pickup signal S (img) and the reference signal S (ref) based on the pixel signal S (pixel) and the pseudo-signal S (psd), respectively. Therefore, the image signal S (img) and the reference signal S(ref) are included in the column fixed modal noise caused by the column signal processing circuit 15. The image signal S (img) is subjected to the above-mentioned calculation processing using the reference signal s (ref), so that the column fixed modal noise caused by the column signal processing circuit 15 is to be read in the read signal S (OUT) reduce. Since the pseudo-signal source s (psd) does not contain the photoelectric conversion element, the lowering of the fixed-mode noise of the column is not affected by the light leakage or the diffusion of electrons from the pixel array 3. The signal processing flow in the solid-state imaging device 1 is more specifically, the pixel signal s (pi χ e!) sent from the pixel 11 in the pixel array 3 is read out, and then A/D conversion is performed. The digital image signal s (img), that is, the first digital data s (ADC1). Further, after reading the reference signal s ( pSd ) from the reference circuit 7a, a process of generating the a/d converted digital reference signal S (ref), that is, the second digital data s (ADC2) is performed. The project of directly providing the first digital data S ( a D C 1 ) to the processing circuit 60b of the -35-201143412 is performed. On the other hand, the second digital data S (ADC2) is supplied to the arithmetic processing circuit 60b via the digital filter 60a for averaging processing (for example, S104). In the digital filter 60a, the arithmetic mean is performed for the digital data S (ADC2) of the m-frames input in order for each frame. Carry out the filtered 値 < S (ADC2)> is supplied to the calculation processing circuit 60b. In the calculation processing circuit 60b, 'from the start of the operation to the m-frame, the generation of the representation digital data S(ADC1) and the average 値 are performed. <3 (eight 002) > The signal processing of the difference signal (for example, S 1 0 5 ). By doing this, a good image signal without fixed modal noise can be obtained. Although the principles of the invention have been described in the preferred embodiments, the invention may be modified in the details and details. The present invention is not limited to the specific configuration disclosed in the embodiment. For example, a circuit composed of a fully differential circuit can be used in a circuit constructed using a single-ended circuit. Alternatively, a single-ended circuit can be used in a circuit composed of a circuit composed of fully differential. Therefore, all amendments and changes in the scope of the patent application and its spirit are in the required powers. [Possibility of Industrial Use] According to the present invention, it is possible to provide a solid-state imaging device which can reduce the fixed-mode noise of the column without being affected by light leakage or diffused electrons from the pixel array. Moreover, according to the present invention, a method of reading a signal from a pixel array of a solid-state imaging device can be provided, according to which the vertical fixed mode modal noise can be reduced. -36-201143412 [Simplified description of the drawings] Fig. 1 is a view showing a block configuration of a solid-state imaging device of a two-dimensional image sensor. Fig. 2 is a view showing a configuration of a reference circuit of a reference voltage generating unit. [Fig. 3] Fig. 3 is a drawing of an array of reference circuits. [Fig. 4] Fig. 4 is a view showing an example of a vertical column signal processing circuit for a solid-state imaging device according to the present embodiment. [Fig. 5] Fig. 5 is a view showing another example of a vertical column signal processing circuit for a solid-state imaging device according to the present embodiment. Fig. 6 is a view showing still another example of the vertical column signal processing circuit for the solid-state imaging device according to the embodiment. Fig. 7 is a view showing an example of a solid-state imaging device and a reading method thereof. Fig. 8 is a view showing another example of a solid-state imaging device and a reading method thereof. [Fig. 9] Fig. 9 is a view showing an example of a circuit configuration of a signal processing unit. Fig. 10 is a view showing still another example of a solid-state imaging device and a reading method thereof. Fig. 11 is a view showing an example of a circuit configuration of a signal processing unit. Fig. 12 is a view showing still another example of a solid-state imaging device and a reading method thereof. -37-201143412 [Fig. 13] Fig. 13 is a view showing an example of a circuit configuration of a signal processing unit. Fig. 14 is a view showing an example of an IIR filter characteristic. [Fig. 15] Fig. 15 is a diagram showing the main steps in the method of reading signals from the pixel array of the solid-state imaging device. [Description of main component symbols] 1 : Solid-state imaging device 3 : Pixel array Π : Pixel Π a : Photoelectric conversion element 1 1 b : Pixel circuit S (pixel): Pixel signal C: Column line 7 : Reference signal generating unit 7a 7b, 7c, 7d: reference circuit PSD: pseudo-signal source S (psd): pseudo-signal 5: column signal processing unit 1 5: column signal processing circuit 9: signal processing unit S (ref): reference signal S (img ): Camera signal S ( OUT ): certificate signal -38-

Claims (1)

201143412 VII. Patent application scope: 1. A solid-state imaging device, comprising: a pixel array comprising pixels, wherein the pixel has a photoelectric conversion element and a pixel circuit for providing signals from the photoelectric conversion element; and a reference signal The generating unit is disposed on the outer side of the pre-recorded pixel array, and has one or a plurality of reference circuits including a pseudo-signal source for reducing vertical fixed-mode noise of the column; and a column signal processing unit containing The column signal processing circuit is configured to generate an image capturing signal and a reference signal respectively according to the pixel signal from the pre-recorded pixel array and the pseudo-signal from the preceding reference signal generating unit; and the signal processing unit receives the pre-recording signal and the pre-recording signal. And generating a read signal; the pre-recorded pixel array includes a plurality of column arrays; the front column signal processing unit performs reading of the k-times (1 S k ) of the pre-recorded signal for each frame; The pseudo-signal source system does not contain photoelectric conversion elements and floating diffusion parts; Front note processing unit reads out the signal, line by using the front note with reference to the signal and to remember the imaging signals front embodiment to reduce the former referred Column signal processing circuit arithmetic processing of Columnar fixed modal noise caused, is generated. 2. The solid-state imaging device according to claim 1, wherein the pre-recorded pixels in each column array are connected to the column line; -39- 201143412 The column line provides the switch required for the pre-recorded signal; the pre-recorded pixel circuit of the pre-recorded pixel contains the control means required to provide the signal from the pre-pixel photoelectric conversion element to the pre-column line. 3. The solid-state imaging device according to claim 1 or 2, wherein the pre-column signal processing unit includes an array of pre-column signal processing circuits, each of which is a front-end column signal processing circuit. Connected to the front column array respectively; the pre-reference signal generating unit includes an array of pre-referenced circuits, each of which is connected to the pre-column signal processing circuit I. The pre-signal processing unit is included for performing pre-calculation The processing circuit for processing, the pre-signal processing unit performs a process for generating a difference between the pre-recorded reference signal and the pre-recorded image signal for each of the preceding column signal processing circuits as a pre-calculation process; the pre-recorded signal is a pre-calculation The circuit is generated. 4. The solid-state imaging device according to any one of the preceding claims, wherein the front column signal processing unit performs k times of the pre-recording signal for each frame (1 < 1 The reading of the 讯 ; ; 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 ; 前 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The solid-state imaging device according to any one of the preceding claims, wherein the pre-column signal processing unit includes an associated double sampling circuit; The pre-recorded pixel signal is read; the pre-recorded pixel signal contains the first signal level containing the noise component and the second signal level containing the signal component superimposed on the noise component; the pre-recorded video signal indicates the first note The difference between the signal and the second signal of the foregoing. 6. The solid-state imaging device of claim 5, wherein the front-end column signal processing unit includes A/D conversion a circuit for receiving an output signal from a pre-recorded double-sampling circuit. 7. The solid-state imaging device according to claim 6, wherein the A/D conversion in the A/D conversion circuit is A solid-state imaging device according to any one of the first to fourth aspects of the invention, wherein the solid-state imaging device according to any one of the above-mentioned claims, wherein The pre-column signal processing circuit includes: first and second capacitors, an arithmetic amplification circuit, and a switching circuit for changing the connection of the first capacitor, the second capacitor, and the preamplifier amplification circuit; -41 - 201143412 The pre-switching circuit provides: the first connection, which enables the first and second capacitors and the pre-calculation amplifier circuit to perform the relevant double sampling; and the second connection, which makes the first and second capacitors and the pre-calculation increase. The circuit can perform the patrol type A/D conversion; the pre-column signal processing circuit performs the pre-recording related double sampling by the first connection first, and by the second note The solid-state imaging device according to any one of the first to eighth aspects of the invention, wherein the pre-recorded pixel array, the pre-recorded signal generating unit, and the pre-column column The signal processing unit is condensed in a single semiconductor wafer. 10. The method is a method for outputting a signal from a pixel array of a solid-state imaging device including a vertical column signal processing circuit and a reference circuit, and is characterized in that : reading the pixel signals from the pixels in the pre-recorded pixel array to generate the image pickup signal using the front column signal processing circuit; and performing the reference circuit from the pre-recorded pixel array using the front column signal processing circuit a step of reducing the readout of the pseudo-signal of the fixed-mode noise of the column to generate the reference signal; and using the pre-recorded reference signal to reduce the pre-recorded signal processing circuit The operation of the column modulating the processing of the modal noise to generate the read signal: The pre-recorded pixel system has: photoelectric a replacement component, and a pixel circuit for providing a signal from the -42-201143412 photoelectric conversion component; the w reference circuit system includes a pseudo-signal source for generating a pre-symmetric signal; % ge μ & m @源系不The photoelectric conversion element and the floating diffusion part; the sever column signal circuit is a process for performing at least one of the related pixel sampling, the A/D conversion, the amplification, and the sampling and holding operation on the pre-recorded pixel signal and the pre-recorded signal. -43-