JP4517660B2 - Solid-state imaging device, image input device, and driving method of solid-state imaging device - Google Patents

Description

The present invention includes a solid-state imaging device , an image input device, and a solid-state imaging device that have a photosensor and a readout amplifier transistor in a pixel and amplify and read out a signal corresponding to the pixel charge by controlling the amplifier transistor. It is related with the drive method of.

  Solid-state imaging devices used as devices that convert light into electrical signals and output image signals such as digital still cameras include MOS (metal oxide semiconductor) type image sensors and CCD (charge coupled device) type image sensors. At the beginning of development, the MOS type image sensor had a drawback that the signal to be read was weak and sensitive to noise because the pixel had a structure called a passive type consisting of only a photosensor and a selection switch. .

  However, in recent years, CMOS image sensors that can be manufactured by a process similar to that of a CMOS integrated circuit have been developed, and an active cell structure having an amplifier for each pixel can be easily made by progress of miniaturization technology of the CMOS process. It has become possible to overcome such drawbacks. In addition, the CMOS image sensor has the feature that a drive circuit and a signal processing circuit other than the pixel portion can be integrated on the same chip, which is advantageous for high functionality and low cost. In recent years, more research and development has been made. Yes.

  By the way, noise characteristics, which is one of the performances of solid-state imaging devices, appear directly as images, so it is very important to improve the characteristics of both MOS and CCD types. is there. There are two types of noise: random noise with irregular signal fluctuations over time and fixed pattern noise generated due to spatial variations. Random noise mainly occurs in photosensors, amplification points, other amplification points, etc., such as light shot noise and thermal noise, and easily changes depending on the environmental temperature. On the other hand, fixed pattern noise is often caused by an imbalance in electrical characteristics due to a difference in threshold voltage of amplifier transistors in a pixel and other circuits and wirings.

  In order to improve the S / N ratio in a CMOS image sensor, an active type structure having an amplifier for each pixel is often adopted, and variations in threshold voltage of transistors (amplifier transistors) constituting this amplifier are fixed patterns. It is known that this is one of the factors that generate noise. This fixed pattern noise due to variations in threshold voltage is a fixed pattern noise that has a two-dimensional spatial distribution depending on the pixel position of the screen and is always generated with the same distribution over the entire screen. Since the fixed pattern noise generated on the entire screen is generated both when the reset state is read out and when the pixel signal is actually read out, two data of the reset state signal and the signal from the pixel are obtained for each pixel. Can be suppressed by using a CDS (Correlated Double Sampling) circuit that reads the difference between them and takes the difference between them.

  However, in a CMOS image sensor having a CDS circuit for each column, or a CMOS image sensor that outputs signals from a plurality of lines and performs signal processing in each path, the difference in the CDS capacitor and the threshold value of the transistor that switches the path The output signal varies depending on the column or the output signal path due to the difference. Therefore, vertical streak-like fixed pattern noise (hereinafter referred to as vertical streak noise) is newly generated in the display image.

As described above, in the CMOS image sensor, even if the fixed pattern noise generated on the entire screen can be suppressed, it has been a problem from the past that vertical stripe-shaped fixed pattern noise is likely to occur.
Therefore, in order to remove vertical streak-like fixed pattern noise, a pixel signal (light-shielded pixel signal) that is obtained from the light-shielded pixel portion and has a black level independent of light is recorded in the memory, and the effective pixel is recorded. A method of taking a difference from an obtained signal is known (for example, see Patent Document 1).

Hereinafter, this method will be described in detail.
FIG. 10A shows the structure of the pixel portion, and FIG. 10B shows a schematic waveform of an analog image signal output from the pixel portion.
As shown in FIG. 10A, the pixel portion of the CMOS image sensor shown in Patent Document 1 is a light-shielded pixel portion (hereinafter referred to as an optical black (OB) referred to as “vertical black reference portion” in Patent Document 1. )) Is added to the effective pixel portion (PIXEL). The light-shielding pixel portion (OB) is provided in several lines in the vertical direction of the screen (vertical OB). Although not shown in FIG. 10A, the light-shielding pixel portion (OB) is also provided on both sides of the effective pixel portion (PIXEL) in the horizontal direction. A light-shielding pixel portion (horizontal OB) is provided. Therefore, the pixel portion is configured so that the light-shielding pixel portion (OB) surrounds the effective pixel portion (PIXEL).

  As shown in FIG. 10B, the OB signal indicating the black level from the vertical OB in the vertical blanking period is sequentially output during the horizontal blanking period (HBLK), and then the line including the effective pixel is output. The pixel signal is repeatedly output, and the OB signal is output from the vertical OB of the next line in the next vertical blanking period. It should be noted that since the horizontal OB on both sides in the horizontal direction of the screen is read out even when the line including the effective pixel is read out, the OB signal is also read out during the horizontal blanking period at this time. In FIG. 10B, the waveform at the time of horizontal OB reading is omitted, and the output waveform of the vertical OB signal and effective pixel signal for each line is shown.

FIG. 10C shows an enlarged OB signal after processing by the pixel signal readout circuit. Hereinafter, processing performed by the pixel signal readout circuit on the pixel signal for each pixel column is referred to as “column processing”.
Since the light-shielding pixel portion (OB) is shielded from light, all OB signals should be output as a uniform black level, but the actual OB signal for each line is not uniform. Normally, the random noise described above, and further, the fixed pattern noise generated on the entire screen due to the variation in the threshold value of the amplifier transistor is superimposed on the OB signal, but even when these noise components are small, FIG. As shown in C), the level of the vertical OB signal changes for each pixel column. This variation is caused by a different signal path for each pixel column in the pixel signal readout circuit, and is caused by feedthrough variation of the switch of the pixel signal readout circuit, variation of the CDS circuit, and the like. Generate streaks. Therefore, by calculating the average level of the vertical OB signal for each pixel column and subtracting it from the effective pixel signal, the variation for each pixel column should be offset.

However, the problem here is that the pixel may be defective. That is, since the light-shielding pixel portion (OB) includes the photodiode PD, defective pixels with white spots or black spots may occur with the same probability as the effective pixel portion (PIXEL).
In FIG. 11A, an OB signal read from the light-shielding pixel portion (OB) in which one white spot defect and one black spot defect exist is input to the pixel signal reading circuit 3 and output after processing. The flow of the OB signal is shown. FIG. 11B shows an OB signal after column processing output from the pixel signal readout circuit 3.

  When there is a black spot defect in the light-shielding pixel portion (OB), since the dark current component existing in the normal pixel does not occur in the black spot defect, the OB level becomes abnormally low. When there is a white spot defect, the pixel level always shows a high value. Since these defect levels are not noises, they cannot be removed by the CDS circuit. As shown in FIG. 11B, the signal after column processing is superimposed on the variation due to column processing. In order to obtain fixed pattern noise correction data from the OB signal after column processing, if a defect occurs in the light-shielding pixel portion (OB), vertical stripe noise is generated in a column including the defective pixel.

  In Patent Document 1 described above, in order to make it less susceptible to random noise, an average of a plurality of lines is added to the vertical OB signal for each line and accumulated to generate a reference output, and the reference output is recorded in a memory. Keep it. Then, when reading out the effective pixel portion (PIXEL), the vertical line noise caused by the variation of each column of the pixel signal reading circuit is removed by subtracting the reference value from the effective pixel signal after AD conversion. Patent Document 1 aims at removing random noise, but at the same time, the influence of pixel defects is also reduced.

However, according to the description of Patent Document 1, the lower limit value of the noise level recognized by human eyes on the NTSC display is 3.5 mV, and the vertical OB line necessary for suppressing the noise level below that is 3.5 mV. The number should be at least 8 lines, preferably 16 lines or more.
For this reason, the technique described in Patent Document 1 has a disadvantage that the chip area is large because a large number of vertical OBs are provided and the output signals are averaged for each column to obtain fixed pattern noise correction data. .

  A method of reading the same pixel line several times and averaging the OB signal output at that time is also conceivable. However, this method can suppress random noise, but reads the same pixel line. Therefore, if the line has a pixel defect, the influence of the pixel defect cannot be removed. Therefore, in the method using the light-shielding pixel portion (OB), it is essential to provide a large number of OB pixel lines.

  In addition to the method using the light-shielding pixel portion (OB), a method for obtaining vertical stripe noise correction data using a pixel portion without a photosensor (photodiode) is also conceivable. For example, a dummy line to which a photosensitive pixel capable of photoelectric conversion is not connected is provided in the pixel portion, a signal output from the dummy line is used as noise correction data, and fixed pattern noise is removed using this data. The technique to perform is known (for example, refer patent document 2).

In the pixel portion 100 of the CMOS image sensor shown in FIG. 12, a pixel portion without a photosensor (a dummy line, hereinafter referred to as a dummy pixel portion (DMY)) is added to an effective pixel portion (PIXEL) and a light-shielding pixel portion (OB). Has been.
Since the signal output from the dummy pixel portion (DMY) does not have a photosensor, there is no white point or black point due to a pixel defect. In other words, since there is no dark current component generated by the photosensor, all black spot signals are output. Therefore, it is possible to obtain data for correcting vertical stripe noise from only one line of the dummy pixel portion (DMY). Here, in order to remove random noise included in the correction data, random noise can be suppressed without increasing the number of lines by repeatedly reading the same dummy line and performing averaging.

  By the way, “CDS suppression remaining” is known as another factor of the generation of the vertical muscle. In CDS, the variation in threshold voltage is suppressed with respect to the transistor for amplifying the pixel signal for each pixel. “Remaining CDS suppression” refers to a minute variation that could not be suppressed by CDS.

Although not particularly mentioned in the method of Patent Document 1 that suppresses fixed pattern noise using vertical OB signals for several lines as described above, data for several lines is used simultaneously with the reduction of the influence of random noise and defects. As a result, variations that could not be suppressed by CDS are also averaged and suppressed. Similarly, in the correction using one dummy line, random noise can be suppressed by accessing the line several times, reading the pixel signal each time, and averaging the pixel signal.
However, in Patent Document 2 in which a method using a dummy line is described, there is a description that a noise component that is not affected by a photosensitive pixel is output. However, the configuration of the dummy line is unknown, and the noise component is not changed. It's not clear what it is. The figure shows a line in which nothing else is connected to the vertical register. The variation in the driving capability of the vertical signal line is mainly the variation in the threshold voltage and the variation in the load MOS transistor (current source) of the amplifier transistor of the pixel. In this case, the variation in the load MOS transistor is output. However, since the operating voltage of the vertical signal line is probably at an appropriate potential, it deviates from the voltage at which the amplifier transistor operates, and it is considered that the variation of the load MOS transistor is not accurately estimated. In this case, since correction data is generated ignoring a part of the cause of the vertical stripe noise, this can be a cause of increasing the vertical stripe. Moreover, there is no mention about the CDS suppression remaining, and the effect is also unknown.

  The vertical stripe correction method using the light-shielding pixel portion described in Patent Document 1 and the vertical stripe correction method using the dummy pixel portion (DMY) as in Patent Document 2 have different problems. Hereinafter, this problem will be described.

  In the description so far, correction data is generated using an OB signal or a dummy pixel signal, and the fixed pattern noise is canceled by subtracting the correction data from the pixel signal. Fixed pattern noise that can be canceled by this method is limited to that caused by offset variation. “Variation in offset characteristics” refers to variations in circuits and the like that do not change the amount of noise in accordance with the amount of input signal. For example, in a 1 × circuit that outputs an input signal as it is, if the output signal is 1.5V when the input signal amount is 1V, and the output signal is 2.5V when the input signal is 2V, the offset is included. However, the offset amount 0.5 V does not change according to the input signal amount. Such noise is caused by the variation factor of the offset property, and the noise amount at that time is hereinafter referred to as “offset error amount”.

  As a cause of the vertical streak fixed pattern noise, for example, in addition to the variation of the CDS circuit, the variation of the current source provided for each vertical signal line, and the signal after CDS are discharged to one or a plurality of buses in a dot-sequential manner. There are various factors such as switch variations, but not all of these factors have variations in offset characteristics with respect to the signal amount. For example, if the CDS circuit is constituted by a sample-and-hold (S / H) circuit using a capacitor, the variation in the capacitor becomes a variation in gain characteristics. Here, “variation in gain characteristics” refers to variations in circuits and the like that change the amount of noise in accordance with the amount of input signal. For example, in the above circuit example, if the output signal is 1.5V when the input signal amount is 1V and the output signal is 2.6V when the input signal is 2V, the noise amount ( (Offset amount) has changed. Such noise is caused by gain variation factors, and the noise amount at that time is hereinafter referred to as “gain error amount”.

FIG. 13A shows an Mth column having the largest offset difference (offset error amount) in the pixel portion and the signal processing portion (including the column processing portion) having gain variation and offset variation. An input / output characteristic of the signal processing unit when a signal output from each pixel unit of N columns (M, N: any natural number) is input is shown. In this figure, the Mth column is relatively shown with the Nth column as a reference.
A portion where the input signal is zero indicates a case where a dummy pixel signal is input when the dummy pixel portion (DMY) is read, and a portion where the input signal is slightly larger than zero is when the light-shielded pixel portion (OB) is read. This shows a case where the OB signal is input. Thus, the dummy pixel signal has a dark current component smaller than the OB signal because there is no dark current component generated in the OB pixel or the effective pixel. Further, the signal from the dummy pixel portion (DMY) is zero in the Nth column, but an output signal of a certain value is generated in the Mth column due to the offset variation. The pixel signal from the Nth column and the pixel signal from the Mth column shown in FIG. 13A do not have the same slope of the straight line indicating the input / output relationship by column processing, which causes variations in gain characteristics. It becomes a factor.

  The signal amount “a” shown in FIG. 13A is vertical streak correction data obtained using a signal from the dummy pixel portion (DMY). When vertical line correction is performed using this signal amount “a”, the input / output relationship of the column processing unit can be corrected as shown in FIG. At this time, since there is a difference in the slope of the gain, the input / output relationship does not completely match in the Mth column and the Nth column. In this figure, the difference in gain slope (gain error amount) is shown to be easy to understand. However, since the actual gain error amount is smaller than the offset error amount, it is usually sufficient to eliminate the offset error. is there.

  By the way, non-linear conversion processing such as gamma correction may be performed in image processing, and in this case, the output signal does not have a linear relationship with the input signal. When the image display device is a cathode ray tube, the input / output characteristics of the gamma correction are not linear. Therefore, the input and output of the entire display device are linear by applying a correction opposite to the input / output characteristics to the video signal in advance. It is a process for doing so. In addition to the original gamma processing for correcting the image signal input to the cathode ray tube, nonlinear conversion processing may be intentionally performed for making a picture.

  The gamma correction unit has an input / output relationship as shown in FIG. 13C and normally has an infinite slope with zero input. Although a finite gain is actually applied to the signal input to the gamma correction unit, the largest gain is applied when the input is small. When the input is zero, the signal is a black level, so the OB signal is clamped to zero and gamma correction is performed. At this time, a horizontal OB signal arranged on the same line is used as an OB signal to be clamped to zero.

Since there is a gain error as shown in FIG. 13B, the remaining correction amount “b” occurs when the input is at the black level (OB level). When gamma correction is performed in this state, if the horizontal OB signal level of this line is equal to the N-th column, the gamma correction unit that has input the horizontal OB signal correctly corrects to zero, that is, the N-th column signal. Black level is output. However, when the horizontal OB signal varies and its upper limit is equal to the M-th column, the gamma correction unit to which the horizontal OB signal is input at this time applies a high gain corresponding to the remaining correction amount “b”. An amplified signal as shown by the signal amount “c” shown in FIG. 13C is output. In particular, when the signal level changes from the black level to the vicinity of the gray level, it becomes noticeable as vertical stripes. Therefore, when the input light is constant, it is important that the signal level near the black level does not vary in the pixel array. However, in the conventional vertical stripe correction method using the dummy pixel portion (DMY), when there is a variation in gain characteristics, a level difference occurs in the OB signal level, which is increased by gamma correction or the like. As a result, vertical stripe correction is performed. However, there is a disadvantage that the vertical stripes are conspicuous.
JP 2000-261730 A Japanese Patent Laid-Open No. 06-189200

The first problem to be solved by the present invention is that the vertical stripe correction method using the signal from the light-shielded pixel portion has a threshold value of the amplifier transistor in the light-shielded pixel portion, for example, when the noise removal capability of the CDS circuit is not sufficient. In order to suppress the influence due to the voltage variation, a large number of light-shielding pixel lines are required, and the chip area is increased.
In addition, the second problem to be solved by the present invention is that the vertical stripe correction method using dummy pixels ignores inherently different signal levels according to differences in driving ability of vertical signal lines that differ for each pixel column. In other words, a constant voltage is output (averaged over time), which causes a vertical stripe to be generated.
Furthermore, a third problem to be solved by the present invention is that a vertical stripe correction method using a vertical stripe correction method using a light-shielding pixel portion or a vertical stripe correction method using a dummy pixel is adopted. Then, when there is a gain variation in addition to the offset variation, the correction accuracy near the black level is remarkably lowered.

The solid-state imaging device according to the present invention is a pixel in which pixels including a photosensor for photoelectric conversion and an in-pixel amplifier transistor that amplifies a pixel signal generated by photoelectric conversion are arranged, and a vertical signal line is connected to each pixel column And a pixel signal readout circuit that includes a current source of each vertical signal line and reads a pixel signal from one end of each vertical signal line, and is connected between the other end of each vertical signal line and the voltage supply line. A plurality of out-of-pixel amplifier transistors having a size larger than that of the in-pixel amplifier transistor and a transistor for monitoring the in-pixel amplifier transistor according to an input control signal, and changing the input voltage of the transistor to output the out-of-pixel amplifier transistor A bias circuit that drives each out-of-pixel amplifier transistor, and the bias circuit includes a plurality of pixels. A signal appearing on each vertical signal line when the amplifier transistor is driven is input to the pixel signal readout circuit, and vertical stripe correction data for each pixel column is generated by a signal output from the pixel signal readout circuit. And a vertical streak correction circuit that corrects the vertical streak by subtracting the vertical streak correction data for each pixel column from the effective pixel signal output from the pixel signal read circuit when reading the pixel portion.
In the present invention, preferably, the pixel portion includes a light-shielding pixel portion having the same circuit configuration as that of the effective pixel but having at least one row of light-shielding pixels that are shielded from light, and the bias circuit includes pixels of the light-shielding pixel portion. The output voltages of the inner amplifier transistor and the out-of-pixel amplifier transistor are monitored, and the control input voltage of the out-of-pixel amplifier transistor is adjusted so that the operating points of the two amplifier transistors coincide with each other.

In the present invention, preferably, reads the light-shielded pixels is the same circuit configuration as the effective pixels are shielded from light and a light shielding pixel portion are disposed at least one row, the light-shielded pixel unit without driving the pixel outside the amplifier transistor And a circuit for obtaining a signal level difference between the shaded pixel signal and a dummy pixel signal appearing on each vertical signal line when the out-of-pixel amplifier transistor is driven, and the bias circuit is obtained by the circuit. The input voltage supplied to the transistor that monitors the in-pixel amplifier transistor is controlled in accordance with the signal level difference.

In the image input device according to the present invention, pixels including a solid-state imaging device, a photosensor for photoelectric conversion, and an in-pixel amplifier transistor that amplifies a pixel signal generated by photoelectric conversion are arranged, and a vertical signal line is provided for each pixel column. A pixel signal readout circuit that includes a connected pixel portion, a current source of each vertical signal line, reads a pixel signal from one end of each vertical signal line, and between the other end of each vertical signal line and the voltage supply line And a plurality of out-pixel amplifier transistors each of which is larger than the in-pixel amplifier transistor and a transistor that monitors the in-pixel amplifier transistor according to an input control signal, and changes an input voltage of the transistor. A bias circuit that drives each out-of-pixel amplifier transistor and a bias A signal appearing on each vertical signal line when a path drives a plurality of out-of-pixel amplifier transistors is input to the pixel signal readout circuit, and vertical stripe correction for each pixel column is performed by a signal output from the pixel signal readout circuit. A vertical streak correction circuit that generates and holds data for the vertical streak by subtracting the vertical streak correction data for each pixel column from the effective pixel signal output from the pixel signal read circuit when the pixel unit is read, and And at least the pixel portion, the pixel signal readout circuit, the out-pixel amplifier transistor, and the bias circuit are formed inside the solid-state imaging device.

  According to the present invention, as a configuration replacing the so-called dummy pixel portion, a plurality of out-pixel amplifier transistors for each pixel column and a bias circuit for driving the same are provided. When signals output from these configurations are simultaneously read out to a plurality of vertical signal lines, the signals are processed in parallel by the pixel signal readout circuit.

  A plurality of out-of-pixel amplifier transistors and bias circuits are circuits that output vertical streak correction signals that do not depend on dark current because they do not have a photoelectric conversion function, as in the conventional dummy pixel unit. Since the out-of-pixel amplifier transistors are simply the size of the in-pixel amplifier transistors, the signals output from them take into account variations in the threshold values of the in-pixel amplifier transistors for each pixel column. In addition, it reflects the variation in the driving capability of the vertical signal line. However, since variations in the threshold voltage are suppressed according to the size ratio of the two amplifier transistors, the residual suppression is reduced from a circuit that suppresses these variations (for example, a CDS circuit in the pixel signal readout circuit). Signal is output.

  When the signal is input to the vertical stripe correction circuit via the pixel signal readout circuit, the vertical stripe correction circuit generates and holds vertical stripe correction data for each pixel column based on the signal. The vertical streak correction circuit receives the effective pixel signal output from the pixel signal readout circuit when reading out the pixel portion, and subtracts the vertical streak correction data for each pixel column from the input effective pixel signal. To perform vertical stripe correction.

Further, since the bias circuit is provided, the operating point of the out-of-pixel amplifier transistor can be arbitrarily set and changed.
For example, a circuit for obtaining a signal level difference between a light-shielded pixel signal read from a light-shielded pixel unit without driving an out-of-pixel amplifier transistor and a dummy pixel signal appearing on each vertical signal line when the out-of-pixel amplifier transistor is driven. In the configuration, the bias circuit controls the input voltage supplied to the transistor that monitors the intra-pixel amplifier transistor according to the signal level difference obtained by the circuit. Therefore, it is possible to control so that the variation center value of the signal level output from the out-of-pixel amplifier transistor is aligned with the variation center of the light-shielded pixel signal level. In this case, the signal output from the out-of-pixel amplifier transistor is shielded from the effective pixel signal. There is no difference between the signal level and offset.

In the solid-state imaging device and the image input device according to the present invention, a signal that is not affected by a dark current or a defective pixel is output from an out-of-pixel amplifier transistor as in the case of vertical stripe correction using a conventional dummy pixel unit, and the signal is output. In order to obtain the vertical stripe correction data, it is not necessary to provide several shade pixel lines as in the conventional method of obtaining the vertical stripe correction data using the shade pixel signal, and there is an advantage that the area penalty for the vertical stripe correction is small. is there.
In addition to this, the signal output from the out-of-pixel amplifier transistor is not a voltage that becomes constant when time averaged, but considers the threshold voltage of the in-pixel amplifier transistor, and the difference in the drive capability variation of the vertical signal line Since this is a signal reflecting the above, this does not cause the vertical stripe noise to be enhanced. In addition, since the level of variation itself is reduced according to the size ratio of the two amplifier transistors, the spatial noise removal effect is improved by processing performed by a CDS circuit or the like.
Further, since the operating point of the out-of-pixel amplifier transistor can be arbitrarily set by the bias circuit, it is possible to prevent the vertical stripe correction accuracy from being lowered due to the variation in gain characteristics.

  The present invention can be widely applied to a so-called XY address type solid-state imaging device that reads out a pixel signal to a vertical signal line. A typical example of such a solid-state imaging device is a CMOS image sensor. Hereinafter, a CMOS image sensor will be described as an example.

[First Embodiment]
FIG. 1 is a block diagram of a CMOS image sensor, FIG. 2 is a diagram showing a configuration of a pixel portion and a pixel signal readout circuit, and FIG. 3 is a diagram showing a configuration of the pixel portion and a correction signal output circuit.
The CMOS image sensor shown in FIG. 1 has a pixel portion 1 in which pixels are arranged in a matrix. The pixel unit 1 includes an effective pixel unit (PIXEL) and a light shielding pixel unit (OB). Although only three pixels 10 belonging to the same row are shown in FIG. 2 for the sake of simplicity, the actual effective pixel portion (PIXEL) has a configuration in which a large number of pixels 10 having the same configuration are arranged in a matrix. In the case of the three-transistor type shown in FIG. 2, each pixel 10 configuring the effective pixel portion (PIXEL) includes a photosensor PD that photoelectrically converts input light and three transistors 11 to 13. The three transistors switch the node ND from the floating state to the connection state to the power supply line 15, charge the power supply voltage to the node ND, and reset the charge amount, and then the floating state again after the reset. A transfer transistor 12 for transferring the stored charge (usually electrons) of the photosensor PD to the node ND, an amplifier transistor 13 for amplifying a pixel signal corresponding to the stored charge transferred to the node ND and outputting it to the vertical signal line 14; Consists of.

A reset control line 16 common to the pixels in the same row is connected to the gate of the reset transistor 11. A transfer control line 17 common to the pixels in the same row is connected to the gate of the transfer transistor 12.
A vertical drive circuit 2 that supplies various signals to each of the control lines 16 and 17 and the power supply line 15 is connected. In addition, a pixel signal readout circuit 3 and a horizontal shift register 4 are provided which perform parallel processing on pixel signals read simultaneously to the vertical signal line 14 to remove noise and convert the signals into time-series signals. These vertical drive circuit 2, pixel signal readout circuit 3, and horizontal shift register 4 operate under the control of the timing control circuit 5 shown in FIG.

As shown in FIG. 3, the light-shielding pixel portion (OB) is arranged on one side in the column direction of the effective pixel portion (PIXEL). The shading pixel portion (OB) shares all the vertical signal lines 14 with the effective pixel portion (PIXEL). For this reason, the signal read from the light-shielding pixel portion (OB) is affected by variations (fixed pattern noise) inherent in the pixel signal readout circuit 3 as in the case of the effective pixel signal.
In the arrangement example shown in FIG. 3, the light-shielding pixel portion (OB) is arranged above the effective pixel portion (PIXEL). However, it may be arranged below the effective pixel portion (PIXEL). The number of dots (number of pixels in the row direction) of one line of the light-shielding pixel portion (OB) is determined according to the effective pixel portion (PIXEL), but the number of lines (number of pixels in the column direction) is arbitrary. However, in the present embodiment, it is sufficient that at least one line of light-shielding pixel portions (OB) exists.
Each pixel of the light-shielding pixel portion (OB) has the same configuration as the pixel of the effective pixel portion (PIXEL) as shown in FIG. 3, but its surface is covered with the light-shielding layer 1A to prevent the influence of external light. . However, even when there is no external light input, dark current is generated and its influence cannot be avoided.

  As shown in FIG. 2, the pixel signal readout circuit 3 includes a current source 31, a CDS circuit 32, and a sampling switch 33 provided for each vertical signal line 14. The current source 31 is provided to supply a constant current to the amplifier transistor 13. Further, the CDS circuit 32 samples and holds the pixel signal of the effective pixel portion (PIXEL) or the light-shielding pixel portion (OB) at the black signal level and the pixel signal level corresponding to the accumulated charge. This is a circuit that takes a difference from a voltage and cancels a noise component superimposed on both voltages. The pixel signal level after this noise removal is held at the output of the CDS circuit 32, and is further sampled dot-sequentially by a sampling switch 33 that is sequentially turned on by a pulse supplied from the horizontal shift register 4.

  For example, in the configuration shown in FIG. 2, if the same amount of light is incident on the two-dimensionally arranged pixels 10 during the reading of the pixel signals, the amount of charge generated in each pixel 10 is the same. The output signal should be constant. However, the variation of the current source 31 shown in FIG. 2, the variation of the capacitance in the CDS circuit 32, the variation of the feedthrough of the sampling switch 33, the coupling capacity between the wiring of the pulse signal output from the horizontal shift register 4 and the output bus Due to various factors such as variations in pixel values, pixel signals are output with variations depending on the columns. The noise resulting from this variation is not random noise, but is fixed pattern noise that is always generated for each column by the same amount, and appears as vertical stripes in the image. This fixed pattern noise is similarly generated regardless of whether the signal is generated in the effective pixel portion (PIXEL) or the light-shielding pixel portion (OB).

  The pixel signal readout circuit 3 shown in FIG. 2 employs a configuration in which pixel signals after dot-sequential sampling are supplied to a plurality of buses and converted into one time series signal (output signal) by a built-in multiplexer 34. Yes. As another configuration, a pixel signal after dot sequential sampling may be supplied to one signal line and output as it is as a time-series output signal.

  As shown in FIG. 1, the time series output signal is input to an analog signal processing circuit 6 called an analog front end (AFE). Since the input time-series signal has a signal level lower than the reference level of no signal, the signal is inverted in the analog signal processing circuit 6 and output after the gain adjustment and the removal of high frequency components are performed as necessary. Is done. The analog signal output from the analog signal processing circuit 6 is digitized by an AD converter (ADC) 7 at the next stage, and further processed by the output processing circuit 8 to be output.

The CMOS image sensor according to the present embodiment is provided with a correction signal output circuit 9 as shown in FIG. 1 as means for suppressing streaky fixed pattern noise (vertical stripe noise).
As shown in FIG. 3, the correction signal output circuit 9 includes a transistor 91 provided for each pixel column and a bias circuit 92 that controls a DC bias of the transistor.

The transistor 91 is turned on by the bias circuit 92 when acquiring correction data for removing vertical stripe noise, and operates in a pair with the amplifier transistor 13 of the pixel 10 selected in the corresponding column. The transistor 91 added for vertical stripe correction has its source connected to the corresponding vertical signal line 14 and its drain connected to the voltage supply line 18. The voltage applied to the voltage supply line 18 may be the same as the power supply voltage Vdd applied to the power supply line 15 or may be a positive voltage different from the power supply voltage Vdd.
However, the gate length and gate width of the transistor 91 added for vertical stripe correction are made as large as possible within a range that can be accommodated in the pixel pitch in the horizontal direction, and thereby the size of the transistor 91 added at the time of vertical stripe correction is made effective pixels. It is desirable to make it sufficiently larger than the size of the amplifier transistor 13 used in FIG. The bias circuit 92 is a circuit for setting a bias condition so that the operating points of the two transistors 13 and 92 are the same when acquiring correction data. Therefore, when viewed from the vertical signal line 14, it is equivalent to an apparent increase in the size of the amplifier transistor 13 of the effective pixel 10. Hereinafter, the transistor 91 added for vertical stripe correction is referred to as an “out-pixel amplifier transistor” and is distinguished from the amplifier transistor 13 in the pixel.

In general, if the gate length of a certain transistor is L and the gate width is W, the variation in threshold voltage of two adjacent pair transistors is proportional to (1 / LW) ^1/2 . For this reason, when the threshold voltage of the in-pixel amplifier transistor 13 has a variation of 10 mV with a standard deviation σ, for example, the pixel is set such that the gate length L and the gate width W are each 10 times that of the in-pixel amplifier transistor 13. When the external amplifier transistor 91 is designed, the variation in threshold voltage of the external pixel transistor 91 is reduced to a standard deviation σ of about 1 mV. Therefore, in this case, by using the out-of-pixel amplifier transistor 91 at the time of vertical stripe correction, the variation in threshold voltage of the amplifier transistor can be reduced to 1/10.

  When the out-of-pixel amplifier transistor 91 having a size different from that of the in-pixel amplifier transistor 13 is used as described above, it is desirable to align the operating points of the two transistors 13 and 91 by the bias circuit 92. In many cases, simply using the out-pixel amplifier transistor 91 in which the gate length L and the gate width W are changed from those of the in-pixel amplifier transistor 13, the operating point of the source follower of the in-pixel amplifier transistor 13 and the correction signal output circuit. The operating points of the nine out-of-pixel amplifier transistors 91 are shifted. In this case, the variation of the load MOS transistor (current source 31) constituting the amplifier transistor and the source follower cannot be accurately estimated. In order to prevent this, it is necessary to adjust the gate bias voltage of the out-of-pixel amplifier transistor 91 to a value different from the gate voltage (OB signal voltage) of the in-pixel amplifier transistor 13 according to the threshold difference.

  The bias circuit 92 shown in FIG. 3 is a circuit provided for this purpose, and includes two transistors 93 and 94, an amplifier 95 as a comparator, two current sources 96 and 97, and a capacitor 98. Note that the capacitor 98 is for suppressing the voltage fluctuation of the signal line, and can be omitted if it is not necessary.

  As the transistor 93, a transistor having the same operating point at the OB signal level as the intra-pixel amplifier transistor 13 in the effective pixel portion (PIXEL) and the light-shielding pixel portion (OB) is used. In order to make the operating point the same, the transistor 93 having the same size (the gate length L and the gate width W) as the in-pixel amplifier transistor 13 and formed in a lump under the same process conditions is used. It is desirable to have characteristics. When voltage drop during operation of the reset transistor 11 in the pixel is negligible, the same voltage as the power supply line 15, for example, the power supply voltage Vdd is applied to the drain and gate of the transistor 93. Therefore, the drain and gate of the transistor 93 are held at the same voltage as the in-pixel amplifier transistor 13. A current source 96 is connected between the source of the transistor 93 and the ground potential, and the source of the transistor 93 is connected to the non-inverting input “+” of the amplifier 95. The current source 96 has the capability of flowing the same current as the current flowing through the vertical signal line 14 during vertical stripe correction. For this reason, the potential V1 at the midpoint of connection between the current source 96 and the transistor 93 (the non-inverting input potential of the amplifier 95). Becomes substantially equal to the potential of the source operating point of the amplifier transistor 13 in the pixel.

  Similarly, the transistor 94 having the same operating point at the OB signal level as the out-pixel amplifier transistor 91 is used as the other transistor 94. In order to make the operating point the same, the transistor 94 having the same size (gate length L and gate width W) as the out-of-pixel amplifier transistor 91 and formed in a lump under the same process conditions is used. It is desirable to do. The same voltage as the drain of the out-of-pixel amplifier transistor 91, for example, the power supply voltage Vdd is applied to the drain of the transistor 94, and the current source 97 also has the ability to flow the same current as the current flowing through the vertical signal line 14 during vertical stripe correction. Yes. Therefore, the potential V2 at the midpoint of connection between the transistor 94 and the current source 97 is substantially equal to the potential at the source operating point of the out-of-pixel amplifier transistor 91.

  The midpoint of connection between the transistor 94 and the current source 97 is connected to the inverting input “−” of the amplifier 95. The gate voltages of the transistor 94 and the out-of-pixel amplifier transistor 91 are driven by the output of the amplifier 95. For this reason, the amplifier 95 controls the potential V2 at the connection midpoint to be equal to the potential V1 at the same connection midpoint as the source operating point of the in-pixel amplifier transistor 13. As a result of this control, when the threshold voltage of the transistor 94 is Vtho, the amplifier output potential V3 at that time is (V1 + Vtho). The amplifier output potential V3 (= V1 + Vtho) is supplied to the gate of the out-of-pixel amplifier transistor 91, and the potential (V1) lowered by the threshold Vth from there becomes the source drive point potential of the out-of-pixel amplifier transistor 91. Therefore, the source drive point potentials of the two amplifier transistors 13 and 91 inside and outside the pixel are both made equal to (V1).

By aligning the source drive points, the reference of the OB signal output from the light-shielded pixel portion (OB) portion and the signal output from the out-of-pixel amplifier transistor 91 (hereinafter referred to as DMY signal) are substantially the same. However, the DMY signal has a wider range than the OB signal because it is not affected by the dark current.
The DMY signal is subjected to column processing through the pixel signal readout circuit 3, and is further input to the output processing circuit 8 through the analog signal processing circuit 6 and the ADC 7 shown in FIG. A vertical stripe correction circuit is provided in the output processing circuit 8. The configuration of the vertical streak correction circuit is not particularly shown. For example, when a plurality of DMY signals are output, a circuit that removes random noise by taking the average of the DMY signals, and holds the average value as correction data. A line memory and a subtraction circuit that reads correction data from the line memory and subtracts the correction data from the input effective pixel signal for each line when reading the effective pixel signal.
As a result, the effective pixel signal after vertical stripe correction is output from the subtraction circuit.

  In the present embodiment, signal variation due to the threshold voltage of the amplifier transistors is suppressed according to the size ratio of the two amplifier transistors 13 and 91 as compared with the case where the light-shielding pixel portion does not have a photosensor. As a result, the amount of residual CDS suppression is reduced by the amount of variation in the input signal of the CDS circuit shown in FIG. The degree of suppression of this signal variation can be adjusted by changing the size ratio of the amplifier transistors 13 and 91. In other words, when the variation of the current source 31 is relatively large, if the transistor size ratio is excessively increased, the variation of the current source becomes difficult to be reflected in the CDS input signal, and is reflected when the actual effective pixel signal is read out. The influence of the current source that is to be reduced is reduced in the DMY signal. In such a case, a part of the cause of the fixed pattern noise is ignored, and the vertical stripe may be enlarged. In the present embodiment, by optimizing the size ratio of the amplifier transistors 13 and 91 at the time of design, signal variation caused by the amplifier transistors is suppressed as much as possible without causing an increase in vertical streak noise caused by the current source, and CDS suppression remains. The benefit is that it can be minimized.

  Note that it is not essential to provide the light-shielding pixel portion (OB) as long as this embodiment is limited. Even in the case of providing, the light-shielding pixel portion (OB) is sufficient for one line, and the arrangement region of the extra-pixel amplifier transistor 91 is sufficient for one line of normal pixels. Note that the area occupied by the bias circuit 92 can usually be smaller than one pixel line. As a result, there is an advantage that the area area of the circuit relating to the vertical stripe correction can be greatly reduced as compared with the case where the shaded pixels are provided with 8 lines or 16 lines by the method of obtaining the vertical stripe correction data only from the shaded pixel signal.

[Second Embodiment]
FIG. 4 is a diagram illustrating a configuration of a pixel unit, a correction signal output circuit, and the like according to the second embodiment. The configuration shown in FIGS. 1 and 2 is common to the present embodiment.
In the configuration shown in FIG. 4, a vertical signal line short circuit 20 is added to one side in the column direction (vertical direction) of the pixel portion as compared with the first embodiment shown in FIG. The vertical signal line short circuit 20 includes a plurality of shunt transistors 21 provided for each vertical signal line 14, each source connected to the corresponding vertical signal line 14 and drain commonly connected. The gate of the shunt transistor 21 is connected to the common control line 22 and is controlled by the vertical drive circuit 2. When all the shunt transistors 21 are turned on under the control of the vertical drive circuit 2, the potentials of all the vertical signal lines 14 are equalized.

  As explained so far, the cause of the vertical stripes can be considered as shown in FIG. At this time, when the influence of the variation of the current source 31 shown in FIG. 2 on the vertical stripe is so small that other factors are dominant, the out-pixel amplifier transistor 91 is connected by connecting the vertical signal lines 14 in parallel. Parallelize. The out-of-pixel amplifier transistor 91 originally has a relatively large size, so the variation in characteristics is small. However, when the out-of-pixel amplifier transistor 91 is parallel, the out-of-pixel amplifier transistor 91 is averaged to contribute to the variation in characteristics. As a result, it is possible to more accurately extract the factor causing the vertical stripe by preventing the CDS suppression residue.

[Third Embodiment]
In the third embodiment, in addition to the reduction of the CDS suppression residue in the first and second embodiments, the offset amount of the signal level is further reduced during nonlinear conversion processing such as gamma correction due to the aforementioned variation in gain characteristics. The means to solve the problem of deviation is presented. In this embodiment, it is essential that the pixel portion 1 includes the light-shielding pixel portion (OB) shown in FIG. Hereinafter, a signal output from the light-shielding pixel portion (OB) at the time of vertical stripe correction is referred to as an OB signal, and a signal output from the correction signal output circuit 9 is referred to as a DMY signal.

FIG. 5 shows a bias circuit according to the third embodiment.
3 and 4, the bias circuit 92 includes two transistors 93 and 94 for monitoring, an amplifier 95 as a comparator, and two current sources 96 and 97 (and a capacitor 98: optional). Two switches SW1 and SW2 for switching the input voltage of the out-of-pixel amplifier transistor 91 are added.
The switch SW1 is turned on when the input voltage of the out-of-pixel amplifier transistor 91 is set to the reference voltage Vp at the time of reset reading (P phase). The switch SW2 is turned on when the input voltage of the out-of-pixel amplifier transistor 91 is to be set to the reference voltage Vd at the time of signal readout (D phase).
Further, the vertical stripe correction feedback circuit 40 is connected to the gate terminal of the transistor 93 via a DA converter (DAC) 41 and an amplifier 42. The output of the AD converter (ADC) 7 shown in FIG. 1 is connected to the input of the vertical stripe correction feedback circuit 40. The capacitor 49 connected to the output path of the amplifier is provided for stabilizing the signal line potential, but can be omitted when it is not necessary.

FIG. 6 shows a configuration example of the vertical stripe correction feedback circuit 40.
The vertical stripe correction feedback circuit 40 is a circuit for obtaining a voltage V <b> 4 (hereinafter referred to as feedback amount) V <b> 4 applied to the gate terminal of the transistor 93. The vertical stripe correction feedback circuit 40 includes an addition average circuit 43 that adds and averages DMY signals or OB signals output from the AD converter (ADC) 7 during vertical stripe correction, and an OB average value holding circuit that holds an average value of the OB signals ( (First holding circuit) 44, DMY average value holding circuit (second holding circuit) 45 for holding the average value of the DMY signal, the OB average value and the DMY average value are read from the two holding circuits 44 and 45, and the difference is obtained. A subtractor 46 to be operated, a feedback amount control circuit 47 for obtaining a feedback amount V4 when the difference between the subtractors 46 is zero, and an OR gate 48 are provided.
An OB data calculation instruction can be input to the OB average value holding circuit 44 from the timing control circuit 5 shown in FIG. Similarly, a DMY data calculation instruction can be input from the timing control circuit 5 to the DMY average value holding circuit 45. The OB average value holding circuit 44 and the DMY average value holding circuit 45 reset the held data according to the input of the corresponding calculation instruction. The OR gate 48 generates a permission signal in the addition averaging circuit 43 in response to an input of any calculation instruction, and starts addition averaging.

When the DMY signal and the OB signal are input to the averaging circuit 43, they are averaged, and here, random noise such as thermal noise, which is temporal variation, is sufficiently suppressed. At that time, for example, even if one black point OB data whose black level is abnormally low due to a black point is present in one line (for example, 1000 pixels), the average value is averaged and contributes 1/1000. Has little effect. The same applies to the white dots. The OB average value (average value of the black level of the OB signal) output from the addition average circuit 43 is held by the OB average value holding circuit 44, and the DMY average value (DMY signal average value) output from the addition average circuit 43. Is held in the DMY average value holding circuit 45.
For example, when the OB average value and DMY average value for one line are held in the corresponding holding circuits 44 and 45, they are read to the subtractor 46, where the difference value between the OB average value and the DMY average value is read. (Signal level difference) is determined.
The feedback amount control circuit 47 inputs the difference value, sets the feedback amount V4 according to the value, and outputs it to the DA converter (DAC) 41. The feedback amount V4 converted into an analog value by the DAC 41 is applied to the gate of the transistor 93 that monitors the intra-pixel amplifier transistor through the amplifier 42 shown in FIG.

As described above, the bias driving circuit 92 aligns the source drive point potentials of the two amplifier transistors 13 and 91 inside and outside the pixel at (V1). Therefore, at the time of signal reading (D phase), a constant voltage that is lower than the voltage Vd applied to the gate of the transistor 94 by the threshold voltage is output to the vertical signal line 14.
On the other hand, in the reset operation (P phase), the switch SW2 is turned off and the switch SW1 is turned on. Therefore, the threshold voltage of the transistor 94 is set to the vertical signal line 14 from the reference voltage Vp (> Vd) during the reset operation. A constant voltage is output. The reference voltage Vp during the reset operation is a high positive voltage and may be the power supply voltage Vdd. In any case, at the time of signal reading, the DMY signal (correction signal) having a level lower than the reference voltage Vp by (Vp−Vd) is discharged from the correction signal output circuit 9 to the vertical signal line 14. As described above, since all the pixel signals are inverted and amplified by the analog signal processing circuit 6 (FIG. 1), the DMY signal has a positive offset of (Vp−Vd) compared to the OB signal and the effective pixel signal. Signal.

FIG. 7 shows examples of waveforms of the DMY signal and the OB signal that vary in the column direction. FIG. 7A shows a case where no offset is applied, and FIG. 7B shows a case where an offset is applied.
When the offset cannot be applied, as shown in FIG. 7A, the center level of the DMY signal (usually coincides with the DMY average value) is the center level of the OB signal (usually coincides with the OB average value). The signal level is always reduced by the dark current. Although the column variation is basically the same for the DMY signal and the OB signal, there may be white spot defects or black spot defects in the OB signal as shown in the figure.

In contrast, when an offset is applied using the circuits shown in FIGS. 5 and 6 in this embodiment, the DMY signal read from the vertical signal line 14 is based on the clamp voltage as shown in FIG. 7B. The signal has an offset of (Vp−Vd). FIG. 7B shows a case where an extremely large offset is applied. At this time, in the circuit shown in FIG. 6, since the DMY average value is higher than the OB average value, the output of the subtractor 46 does not become zero and is positive. Indicates the value of. Therefore, the feedback amount control circuit 47 applies feedback to obtain the feedback amount V4 at which the output of the subtractor 46 becomes zero. The relationship between the output of the subtractor 46 and the feedback amount V4 is output from the feedback amount control circuit 47 to the DAC 41 by multiplying the difference value by the feedback coefficient. The feedback coefficient may be stored in a table or may be obtained by calculation. Alternatively, the value of the DAC 41 and the gain of the amplifier 42 may be controlled. This control has good convergence, and usually a desired feedback amount V4 can be set by a single control after the difference between the average values is detected.
As a result, in FIG. 7B, the OB center level matches the DMY center level, and vertical stripe correction data (DMY signal) in the same state as the OB level can be obtained.

FIGS. 8A to 8C show input / output characteristics of a signal processing unit having variations in gain characteristics and variations in offset characteristics. These figures correspond to FIGS. 13A to 13C before application of the present invention.
When the offset error amount “a” that causes a vertical streak at the DMY signal level is estimated as shown in FIG. 13A, if the vertical streak correction is performed so that the difference is zero at the DMY signal level, FIG. As shown in FIG. 5B, a correction residue of “b” occurs at the OB signal level, which is amplified in nonlinear conversion processing (for example, gamma correction) using the OB signal level as a base point, and a vertical stripe is newly generated. There was a problem.

  In the present embodiment, the DMY signal is offset so that there is no black point defect or white point defect by offsetting the DMY signal so that the difference between the OB signal level and the DMY signal level is eliminated, so that the accuracy of the correction data can be increased. Thus, when the vertical stripe correction amount “a” is estimated, the vertical stripe correction amount is equivalent to that estimated by the OB signal level as shown in FIG. Accordingly, as shown in FIG. 8B, the residual correction amount becomes zero at the OB signal level, and when the gamma correction as shown in FIG. 8C is performed, the signal near the OB level shown in FIG. It is possible to prevent a problem that the conversion accuracy of the gamma correction is greatly lowered at the level.

Incidentally, since a solid-state imaging device normally performs signal processing based on the black level, a clamp system for detecting the black level and feeding back the value to the signal processing circuit is mounted. FIG. 9 shows an example of the configuration.
The OB signal output from the pixel is taken into the clamp circuit 50, the OB average value is calculated and held in the clamp circuit 50 through the digital filter, and the clamp level is set to the analog signal processing circuit (AFE) 6 through the DA converter 51. Control. At this time, the margin is adjusted so that the black level of the pixel signal passing through the AFE 6 falls within the input range of the AD converter (ADC) 7 based on the OB average value.
Here, since the DMY signal has no dark current component, it is smaller than the OB signal by the dark current. Therefore, in order to be able to take in the DMY signal, it is necessary to perform clamping using the DMY signal instead of the OB signal so that the signal enters the input range of the AD converter.

  However, in general, the system is configured to clamp the OB signal and follow the dark current to enter the ADC 7 input range. Therefore, when clamping by the DMY signal, the pixel dark current component and the ADC 7 input range are used. Will be damaged. Therefore, in a solid-state imaging device equipped with a clamp system, when vertical stripe correction is performed using DMY signals, vertical stripes are generated in a signal sequence that cannot be captured unless clamping is performed so that DMY signals can also be captured. On the contrary, in order to capture the DMY signal, a problem that the input range of the ADC 7 is lost occurs.

  In the present embodiment, even when the clamp system shown in FIG. 9 is mounted and clamping is performed with a DMY signal, the DMY signal level is offset adjusted in the vicinity of the OB signal level in advance, so that an AD converter (ADC) is used. 7 can be used effectively, and the problem of impairing the input range of the AD converter that occurs when the DMY signal is used for vertical stripe correction can be solved.

  The embodiment of the present invention has been described above with the CMOS image sensor. However, when the CMOS image sensor is mounted on an image input device such as a digital still camera or a digital video camera, a new one is provided in the present embodiment. Of the added circuits, the correction signal output circuit 9 including the transistors that need to be simultaneously formed by the same process at a position close to the transistors in the pixel portion and the vertical signal line short circuit 20 need to be incorporated in the CMOS image sensor. The other circuits can be arbitrarily realized by a circuit mounted on a printed board outside the CMOS image sensor. However, since a CMOS process is used in the CMOS image sensor, it is easy to incorporate a necessary circuit and the characteristics are improved. Therefore, it is desirable to incorporate the necessary circuit in the CMOS image sensor as described above.

It is a block diagram of the CMOS image sensor which concerns on the 1st-3rd embodiment of this invention. It is a figure which shows the structure of a pixel part and a pixel signal read-out circuit. It is a figure which shows the structure of a pixel part and a correction signal output circuit. It is a figure which shows structures, such as a pixel part and correction signal output circuit which concern on 2nd Embodiment. It is a figure which shows the bias circuit which concerns on 3rd Embodiment. It is a block diagram which shows the structural example of a vertical stripe correction feedback circuit. It is a figure which shows the example of a waveform of the DMY signal and OB signal which varied in the column direction, (A) shows the case where an offset is not applied, (B) shows the case where an offset is applied. It is a figure which shows the input-output characteristic of the signal processing part which has the dispersion | variation in a gain property, and the dispersion | variation in offset property, (A) is the time of a vertical stripe correction amount estimation, (B) is after a vertical stripe correction, (C) is a gamma correction. Each process is shown. It is a block diagram of the CMOS image sensor which mounts the clamp system in embodiment of this invention. It is a figure used for explanation of a solution subject, (A) shows the composition of a pixel part, (B) shows a rough waveform of an analog image signal outputted from a pixel part, and (C) shows pixel signal readout. Each of the enlarged OB signals after processing by the circuit is shown. It is a figure used for explanation of a solution subject, (A) shows the flow of the OB signal read from the shading pixel part (OB) in which each one white spot defect and one black spot defect exist, and (B). An OB signal after column processing output from a pixel signal readout circuit is shown. It is a figure used for description of a solution subject, and is a figure which shows the structure of the pixel part which has a pixel part (DMY) without a sensor. It is a figure used for explanation of a solution subject, (A) at the time of estimating the amount of vertical stripe correction, (B) after vertical stripe correction, and (C) shows gamma correction processing, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel part, 2 ... Vertical drive circuit, 3 ... Pixel signal readout circuit, 4 ... Horizontal shift register, 5 ... Control circuit, 6 ... Analog signal processing circuit, 7 ... DA converter, 8 ... Output circuit, 9 ... Correction signal Output circuit, 10 ... pixel, 11 ... reset transistor, 12 ... transfer transistor, 13 ... in-pixel amplifier transistor, 14 ... vertical signal line, 18 ... voltage supply line, 20 ... vertical signal line short circuit, 21 ... shunt transistor, 22 ... Control line 31 ... Current source 32 ... CDS circuit 40 ... Vertical line correction feedback circuit 41 ... DA converter 42 ... Amplifier 43 ... Addition averaging circuit 44 ... OB average value holding circuit 45 ... DMY average value Holding circuit 46 ... Subtractor 47 ... Feedback amount control circuit 48 ... OR gate 91 ... Out-of-pixel amplifier transistor 92 ... Bias circuit 93,94 ... Monitor Transistors, 95 ... amplifier, 96, 97 ... current source, OB ... shaded pixel portion, PIXEL ... effective pixel portion

Claims (10)

A pixel unit in which pixels including a photosensor for photoelectric conversion and an in-pixel amplifier transistor that amplifies a pixel signal generated by photoelectric conversion are arranged, and a vertical signal line is connected to each pixel column;
A pixel signal readout circuit that includes a current source for each vertical signal line, and reads a pixel signal from one end of each vertical signal line ;
A plurality of out-pixel amplifier transistors each connected between the other end of each vertical signal line and the voltage supply line , each having a larger size than the in-pixel amplifier transistors;
Bias that includes a transistor that monitors the in-pixel amplifier transistor in accordance with an input control signal, changes the input voltage of the transistor to change the operating point of the out-of-pixel amplifier transistor, and drives each out-of-pixel amplifier transistor Circuit,
When the bias circuit drives a plurality of out-of-pixel amplifier transistors, a signal appearing on each vertical signal line is input to the pixel signal readout circuit, and a vertical stripe for each pixel column is output by a signal output from the pixel signal readout circuit. A vertical stripe correction circuit that generates and holds correction data and corrects vertical stripes by subtracting vertical stripe correction data for each pixel column from an effective pixel signal output from a pixel signal readout circuit when reading out the pixel unit; ,
A solid-state imaging device. A light-shielded pixel portion having at least one row of light-shielded pixels that have the same circuit configuration as the effective pixels but are shielded from light;
A circuit for obtaining a signal level difference between a light-shielded pixel signal read from the light-shielded pixel unit without driving the out-of-pixel amplifier transistor and a dummy pixel signal appearing on each vertical signal line when the out-of-pixel amplifier transistor is driven; ,
Further comprising
The solid-state imaging device according to claim 1, wherein the bias circuit controls an input voltage supplied to a transistor that monitors the intra-pixel amplifier transistor according to a signal level difference obtained by the circuit. In the block of the circuit for obtaining the signal level difference,
An averaging circuit for averaging the input signals;
A first holding circuit that holds light-shielded pixel correction data after averaging the light-shielded pixel signals read from the light-shielded pixel unit a plurality of times without driving the out-of-pixel amplifier transistor;
A second holding circuit for holding dummy pixel correction data after averaging the dummy pixel signals appearing on each vertical signal line when the out-of-pixel amplifier transistor is driven a plurality of times;
A circuit for obtaining a voltage when the light-shielding pixel correction data and the dummy pixel correction data held in the first and second holding circuits match, and
The solid-state imaging device according to claim 2, wherein the voltage obtained by the circuit is input to a transistor that monitors the intra-pixel amplifier transistor. The bias circuit monitors the output voltage of the in-pixel amplifier transistor of the light-shielded pixel portion and the out-of-pixel amplifier transistor when driving the out-of-pixel amplifier transistor, and the out-of-pixel direction is such that the operating points of the two amplifier transistors coincide with each other. The solid-state imaging device according to claim 2, wherein the control input voltage of the amplifier transistor is adjusted. A light-shielding pixel portion having the same circuit configuration as the effective pixel but having at least one row of light-shielding pixels that are shielded from light is provided in the pixel portion,
The bias circuit monitors the output voltage of the in-pixel amplifier transistor and the out-of-pixel amplifier transistor in the light-shielding pixel portion, and adjusts the control input voltage of the out-of-pixel amplifier transistor so that the operating points of the two amplifier transistors coincide with each other. The solid-state imaging device according to claim 1. The solid-state imaging device according to claim 1-5 having an electrically shorted capable switches a plurality of the vertical signal line. A solid-state image sensor;
A pixel unit in which pixels including a photosensor for photoelectric conversion and an in-pixel amplifier transistor that amplifies a pixel signal generated by photoelectric conversion are arranged, and a vertical signal line is connected to each pixel column;
A pixel signal readout circuit that includes a current source for each vertical signal line, and reads a pixel signal from one end of each vertical signal line ;
A plurality of out-pixel amplifier transistors each connected between the other end of each vertical signal line and the voltage supply line , each having a larger size than the in-pixel amplifier transistors;
Bias that includes a transistor that monitors the in-pixel amplifier transistor in accordance with an input control signal, changes the input voltage of the transistor to change the operating point of the out-of-pixel amplifier transistor, and drives each out-of-pixel amplifier transistor Circuit,
When the bias circuit drives a plurality of out-of-pixel amplifier transistors, a signal appearing on each vertical signal line is input to the pixel signal readout circuit, and a vertical stripe for each pixel column is output by a signal output from the pixel signal readout circuit. A vertical stripe correction circuit that generates and holds correction data and corrects vertical stripes by subtracting vertical stripe correction data for each pixel column from an effective pixel signal output from a pixel signal readout circuit when reading out the pixel unit; ,
Have
An image input apparatus in which at least the pixel unit, the pixel signal readout circuit, the out-pixel amplifier transistor, and the bias circuit are formed inside the solid-state imaging device. Includes a pixel unit in which pixels including the pixel amplifier transistor for amplifying the pixel signal generated by the photosensor and the photoelectric conversion for photoelectric conversion are arranged, the current source of each signal output line, the signal output line in the pixel portion on the other hand with respect to the solid-state imaging device and a pixel signal readout circuit for reading pixel signals from the end, prior to each SL signal output line, size than the pixel amplifier transistor at its other end provided with a large pixel outside the amplifier transistor is input Providing a monitor transistor for monitoring the in-pixel amplifier transistor according to the control signal, and driving the out-of-pixel amplifier transistor so that its operating point can be changed by changing an input voltage of the monitor transistor;
Generating and holding vertical streak correction data from signals appearing for each of the signal lines when driving the out-of-pixel amplifier transistors; and
Subtracting the vertical stripe correction data for each signal output line from the effective pixel signal discharged to the signal output line at the time of reading the pixel unit, and performing vertical stripe correction;
A method for driving a solid-state imaging device including: When driving the out-of-pixel amplifier transistor, the output voltage of the in-pixel amplifier transistor and the out-of-pixel amplifier transistor of a pixel that is shielded from light is monitored, and the operating point of the two amplifier transistors is matched. The method for driving a solid-state imaging device according to claim 8, wherein the control input of the external amplifier transistor is adjusted. And outputting without driving the pixel outer amplifier transistor, a light-shielded pixel signal from said light-shielded by being pixels to the signal output line,
Obtaining a signal level difference between a signal appearing on the signal output line when the out-of-pixel amplifier transistor is driven and the light-shielded pixel signal;
Further including
The solid-state imaging device driving method according to claim 9, wherein an input voltage supplied to a transistor that monitors the out-of-pixel amplifier transistor is controlled according to the signal level difference.

Images