JP2010114487A - Solid-state image pickup apparatus and image pickup apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the influence of characteristic variation of an external amplifier transistor in a CMOS sensor that suppresses vertical stripe noise using the external amplifier transistor. <P>SOLUTION: A test pixel section 310 is formed in a serial circuit of an external amplifier transistor 312 and a pixel selection transistor 314 for test. The external amplifier transistor 312 is disposed on a gate control line 318 side from a reference voltage generating section 320, and the pixel selection transistor 314 for test is disposed on a vertical signal line 19 side. A connection point of them in each column is connected in common by a short circuit line 317 to parallelize the external amplifier transistor 312 and the pixel selection transistor 314, thereby averaging the contribution of the characteristic variation of them. The factors of vertical stripe can be more correctly extracted by preventing remaining noise after CDS than in a case where this configuration is not applied, and vertical stripe noise can be further suppressed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging device. More specifically, the present invention relates to a solid-state imaging device and an imaging device, typically a solid-state imaging device and an image input device including a pixel array unit in which unit pixels having a so-called 4TR configuration are arranged.

  2. Description of the Related Art Physical quantity distribution detection semiconductor devices in which a plurality of unit components (for example, pixels) that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged in a line or matrix form are used in various fields. ing.

  For example, in the field of video equipment, CCD (Charge Coupled Device) type, MOS (Metal Oxide Semiconductor) type or CMOS (Complementary Metal-oxide Semiconductor) type solid-state imaging devices that detect light (an example of electromagnetic waves) in physical quantities are used. It is used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Solid-state imaging devices are widely used as image input devices (imaging devices) of imaging systems (imaging devices). For example, in recent years, CMOS sensors have made use of the advantages of low power consumption and high speed, and various portable terminal devices such as mobile phones, digital still cameras (compact and high-end single-lens reflex cameras), digital video cameras, camcorders, surveillance cameras. It is becoming widely installed in induction devices and the like. In recent years, high-performance, high-quality CMOS sensors that have on-chip functional circuit blocks such as image processing have begun to appear.

  In a so-called XY address type solid-state imaging device, for example, a plurality of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit, and signal charges corresponding to incident light are accumulated for each line (row) or pixel. Is started, and a current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by addressing. Here, in the MOS (including CMOS) type, as an example of address control, a column readout method (column parallel output method) in which one row is accessed simultaneously and a pixel signal is read from the pixel unit in units of rows is often used. ing. The analog pixel signal read from the pixel unit is converted into digital data by an analog-digital converter (AD converter / ADC: Analog Digital Converter) as necessary.

  Incidentally, in a solid-state imaging device (including application of the imaging device to an image input device), noise characteristics become a problem, and various mechanisms for suppressing the noise characteristics have been studied. For example, as a cause of vertical pattern-like fixed pattern noise, CDS (Correlated Double Sampling) circuit variation, current source variation provided for each vertical signal line, a signal after CDS is single or plural Patent Document 1 proposes a mechanism that pays attention to factors such as variations in selection switches transferred by a bus.

  Furthermore, in a solid-state imaging device that performs CDS processing for reducing variations in current sources provided for each vertical signal line, a mechanism for reducing vertical streak-like fixed pattern noise is disclosed in Patent Document 2 (FIG. 3, paragraph). 29-31). In this mechanism, the same potential setting circuit and a switch on each vertical signal line are provided, and when the switch is turned on, the vertical line-shaped fixed pattern noise is reduced by making the potential between the vertical signal lines the same. I try to reduce it.

JP 2005-223860 A JP 2005-311643 A

  In the mechanism described in Patent Document 1, the unit pixel of the pixel array unit is a so-called 3TR configuration having three transistors for charge transfer, reset, and amplification in addition to the light receiving element (photodiode). It is said. In addition to the pixel array unit, an out-pixel amplifier transistor having a larger size than the in-pixel amplifier transistor of the unit pixel of the pixel array unit and a bias circuit for generating a bias voltage for driving the out-pixel amplifier transistor are provided. Yes. A method of suppressing a fixed pattern noise component between pixels by inputting a potential generated from a bias circuit to a gate of an out-of-pixel amplifier transistor, and acquiring a signal output having a variation component of the CDS circuit itself as a correction signal. Is adopted. This correction signal is a signal for correcting the vertical stripe component of the CDS circuit itself in the image during normal imaging.

  Moreover, providing a switch (shunt transistor) that commonly connects (electrically shorts) the vertical signal lines is also disclosed as a preferred embodiment. When all the switches are turned on, the out-pixel amplifier transistors are parallelized, and the potentials of all the vertical signal lines are equalized. By paralleling the out-of-pixel amplifier transistors, the contribution of the characteristic variation can be averaged, and as a result, it is possible to prevent the CDS suppression residue and extract the factor causing the vertical stripe more accurately. Explained.

  The mechanism described in Patent Document 1 has a so-called 4TR configuration in which the unit pixel of the pixel array unit includes transistors for charge transfer, reset, amplification, and vertical selection in addition to the light receiving element (photodiode). It is possible to apply. However, the following points are problematic.

  In a preferable aspect of Patent Document 1, all the switches are turned on to parallelize the out-of-pixel amplifier transistors, and the contribution of the characteristic variation is averaged. However, the on-resistance component of the switch causes the out-of-pixel amplifier. Variations in the threshold voltage of the transistor cannot be sufficiently removed, and a vertical streak component may remain (referred to as a first problem).

  Moreover, in the preferable aspect of patent document 1, the space for arrange | positioning a switch (shunt transistor) is needed. Although it can be considered that the basic configuration of Patent Document 1 is removed by removing the switch, in this case, as a matter of course, the improvement effect due to the arrangement of the switch cannot be obtained. Longitudinal streak components remain than in the preferred embodiment (referred to as a second problem).

  In a preferable mode of Patent Document 2, the same potential is obtained only when the switch on the vertical signal line is turned on, and the same potential is not obtained when the switch is turned off. For this reason, there are a problem that the value after CDS processing varies for each vertical signal line, and a problem that the data for correcting vertical stripes cannot be handled due to variations in gain characteristics (collectively referred to as a third problem). “Gain variation” refers to variations in a circuit that changes the amount of noise in accordance with the amount of input signal (see paragraph 22 of Patent Document 1).

  In recent years, along with the reduction in noise of solid-state imaging devices, minute vertical stripe components may be conspicuous, and therefore it is required to further suppress the vertical stripe components. It can be considered that improving the first and second problems can be a countermeasure.

  Further, when the mechanism of the cited document 1 in the 3TR configuration is simply applied to the 4TR configuration, there is a problem that the number of transistors increases (referred to as a fourth problem).

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to improve at least one of the first to third problems when the pixel array unit is an array of unit pixels having a 4TR configuration. And In other words, in the 4TR configuration, an object is to provide a mechanism that suppresses vertical stripe noise by using an out-of-pixel amplifier transistor and a mechanism that can reduce the influence of characteristic variation of the out-of-pixel amplifier transistor. An object of the present invention is to provide a mechanism (solution for the fourth problem) that preferably realizes them while suppressing an increase in the number of transistors.

  In one embodiment of the present invention, a reference voltage generation unit that generates a reference voltage and supplies the reference voltage to a control line and a unit pixel of the pixel array unit are configured in addition to the pixel array unit, as in the mechanism of Patent Document 1. An out-pixel amplifying transistor (referred to as an out-pixel amplifying transistor) having a larger size than the amplifying transistor is provided.

  In addition, an out-pixel amplifier transistor is disposed on the control line (reference voltage generation unit) side, a selection transistor is provided in series with the column signal line, and in relation to other columns, The connection points of the selection transistors are commonly connected by a short-circuit line.

  As an alternative to the so-called dummy pixel portion, a plurality of out-pixel amplifier transistors for each column signal line and a reference voltage generation portion for driving the same are provided. When signals output from these configurations are simultaneously read out to a plurality of column signal lines, the signals are processed in parallel by the column signal processing unit, and a signal with reduced residual suppression is output. Preferably, a signal in which the residual suppression is reduced is held as a correction signal. In a normal pixel signal reading operation, vertical stripe correction processing is performed based on the signal output from the column signal processing unit and the stored correction signal.

  Since a selection transistor is provided between the column signal line in series with the out-of-pixel amplifier transistor, and the connection points of the out-of-pixel amplifier transistor and the selection transistor in each column are commonly connected by a short-circuit line, characteristics of the out-of-pixel amplifier transistor Variations are absorbed by the short circuit.

  Note that the solid-state imaging device may have a form formed as a single chip, or a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Also good. The present invention is applicable not only to a solid-state imaging device but also to an imaging device. In this case, the same effect as the solid-state imaging device can be obtained as the imaging device. Here, the imaging device indicates, for example, a camera (or camera system) or a portable device having an imaging function. “Imaging” includes not only capturing an image during normal camera shooting, but also includes fingerprint detection in a broad sense.

  According to one embodiment of the present invention, it is possible to reduce the influence of characteristic variation of an out-of-pixel amplifier transistor, compared to the case where the present invention is not applied. As a result, vertical stripes can be more effectively suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When differentiating each functional element according to the embodiment, an uppercase English reference may be added, such as A, B,... Is omitted. The same applies to the drawings.

  In the following, a case where a CMOS type solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. Unless otherwise specified, the CMOS type solid-state imaging device will be described on the assumption that all unit pixels are made of NMOS (n-channel type MOS transistor) and the signal charge is a negative charge (electron). However, this is merely an example, and the target device is not limited to a MOS type solid-state imaging device. The unit pixel may be configured by a PMOS (p-channel type MOS transistor), and the signal charge is a positive charge ( Hole).

  A semiconductor device for physical quantity distribution detection that reads out signals by address control in which a plurality of unit pixels that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form will be described later. Each embodiment to be applied can be similarly applied.

<Solid-state imaging device: basic configuration>
FIG. 1 is a basic configuration diagram of a CMOS type solid-state imaging device (CMOS image sensor) which is an embodiment of a solid-state imaging device. A solid-state imaging device is also an example of a semiconductor device. The solid-state imaging device 1 includes a pixel array unit 10 in which a plurality of unit pixels 3 are arranged in a two-dimensional matrix. The solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter in which, for example, R, G, and B color filters are arranged in a Bayer array.

  The pixel array unit 10 includes an effective pixel unit 10a and a light shielding pixel unit 10b (OB). In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column. As will be described later, the unit pixel 3 includes, for example, three or four transistors for charge transfer, reset, and amplification in addition to a photodiode as a light receiving element (charge generation unit) which is an example of a detection unit. It has an in-pixel amplifier. A pixel signal voltage Vx is output from the unit pixel 3 via a vertical signal line 19 (an example of a column signal line) for each column.

  The pixel signal voltage Vx of the vertical signal line 19 is such that the signal level Ssig appears after the reset level Srst including the noise of the pixel signal as the reference level as a time series. The signal level Ssig is a level obtained by adding the signal component Vsig to the reset level Srst, and the signal component Vsig is obtained by CDS processing with Ssig (= Srst + Vsig) −Srst.

  The solid-state imaging device 1 further includes a pixel signal reading unit 426 in which a column signal processing unit 450 (an example of a column signal processing unit) that performs a CDS processing function, a selection process, and the like is provided in column parallel. “Column parallel” means that a plurality of column signal processing units 450 such as a CDS processing function unit are provided in parallel to a vertical signal line 19 (an example of a column signal line) in a vertical column. Note that, depending on the circuit configuration, a selector (analog switch) that groups the vertical signal lines 19 of a plurality of systems into one system may be interposed between the pixel signal readout unit 426. Has a configuration in which a plurality of column signal processing units 450 are provided in parallel to the vertical signal line 19 and are included in column parallel. Such a reading method is called a column reading method. The solid-state imaging device 1 further includes a drive control unit 7 and a read current source unit 24 that supplies an operation current (read current) for reading a pixel signal to the unit pixel 3. Note that the readout current control unit 24 and the pixel signal readout unit 426 may be collectively treated as a pixel signal readout unit in a broad sense.

  The solid-state imaging device 1 also includes a post-stage signal processing unit 429 at a stage subsequent to the pixel signal reading unit 426. An analog signal processing unit 429a, an AD conversion unit 429b, and an output processing unit 429c are provided. The output side of the pixel signal reading unit 426 is connected to the horizontal signal line 18 (one or a plurality of buses), and the pixel signal from each column signal processing unit 450 is referred to as an analog front end (AFE) in time series. Is input to the analog signal processing unit 429a. Since the time-series pixel signal input to the analog signal processing unit 429a has a signal level lower than the reference level of no signal, the signal level is inverted in the analog signal processing unit 429a, and gain adjustment and high-frequency component removal are performed as necessary. Is supplied to the AD conversion unit 429b. The AD conversion unit 429b converts an analog pixel signal into digital data and supplies the digital data to the output processing unit 429c. The output processing unit 429c supplies various processed data from the output terminal 5c to the subsequent circuit after performing various digital arithmetic processes.

  In addition, the solid-state imaging device 1 according to the present embodiment performs correction as a part of elements constituting a unit that acquires a correction signal (noise correction signal) for suppressing streak-like fixed pattern noise (vertical stripe noise). A signal output unit 9 is provided. Although the details will be described later, the correction signal output unit 9 has a function of generating a reference voltage and supplying it to the control line, and supplying a signal corresponding to this reference voltage to each vertical signal line 19. Correspondingly, the output processing unit 429c includes a noise correction processing unit 429d. The noise correction processing unit 429d uses the vertical signal line based on the signal output from the column signal processing unit 450 for the signal appearing on each vertical signal line 19 when a signal corresponding to the reference voltage is applied to each vertical signal line 19. A noise correction signal is generated and held every 19th. Furthermore, the noise correction processing unit 429d generates noise based on the signal output from the column signal processing unit 450 and the stored noise correction signal when the processing target signal (pixel signal voltage Vx) is read from the unit pixel 3. to correct.

  The drive control unit 7 includes a horizontal scanning unit 12 (column scanning circuit), a vertical scanning unit 14 (row scanning circuit), and a communication / timing control unit for realizing a control circuit function for sequentially reading signals from the pixel array unit 10. 20 is provided.

  The horizontal scanning unit 12 includes a column address, a horizontal address setting unit that controls column scanning, a horizontal drive unit, and the like. The horizontal scanning unit 12 indicates the column position of the pixel signal to be read out during the pixel signal transfer operation. The vertical scanning unit 14 includes a vertical address setting unit and a vertical driving unit that control row addresses and row scanning. The horizontal scanning unit 12 and the vertical scanning unit 14 start the row / column selection operation (scanning) in response to the control signals CN1 and CN2 given from the communication / timing control unit 20.

  The communication / timing control unit 20 supplies a clock (pulse signal) synchronized with the master clock CLK0 input via the terminal 5a to each unit (scanning units 12, 14 and column signal processing unit 450) in the device. A functional block (an example of a read address control device) is provided. Further, the master clock CLK0 supplied from the external main control unit is received via the terminal 5a, and the data for instructing the operation mode supplied from the external main control unit is received via the terminal 5b. A function block of a communication interface that outputs data including information of the device 1 to an external main control unit is provided. For example, the communication / timing control unit 20 includes a clock conversion unit 20a having a function of a clock conversion unit that generates an internal clock, and a system control unit 20b having a communication function and a function of controlling each unit. Based on the master clock CLK0 input via the terminal 5a, the clock conversion unit 20a has a built-in multiplication circuit that generates a pulse having a higher frequency than the master clock CLK0, and generates an internal clock.

  The unit pixel 3 includes a column signal processing unit 450 provided for each vertical column of the vertical scanning unit 14 via the row control line 15 for row selection and the pixel signal reading unit 426 via the vertical signal line 19. Are connected to each other. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. The vertical address setting unit selects not only a row from which a signal is read (reading row: also referred to as a selection row or a signal output row) but also a row for an electronic shutter.

  The elements of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning unit 14 and the elements of the pixel signal reading unit 426 and the subsequent signal processing unit 429 are the same technology as the semiconductor integrated circuit manufacturing technology together with the pixel array unit 10. The solid-state imaging device 1 of the present embodiment is configured as a so-called one-chip device (provided on the same semiconductor substrate) that is integrally formed in a semiconductor region such as single crystal silicon.

  As described above, the solid-state imaging device 1 may be formed as a single chip in which each unit is integrally formed in the semiconductor region. Although not illustrated, the pixel array unit 10, the drive control unit 7, In addition to various signal processing units such as the pixel signal reading unit 426, an imaging function that is packaged together with an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter is provided. It is good also as the modular form which has. Further, all or part of the post-stage signal processing unit 429 may be separated from the semiconductor region in which the pixel array unit 10 or the like is disposed (for example, formed in another semiconductor region).

<Noise suppression function: Comparative example>
FIG. 2 is a diagram showing a solid-state imaging device 1Z of a comparative example, paying attention to each part related to noise suppression. FIG. 2A is a timing chart illustrating a method for driving the out-of-pixel amplifier. FIG. 2B is a diagram illustrating the reference voltage generation unit. The reference voltage generator is not limited to the comparative example and is used in the present embodiment.

  As an example, the unit pixel 3 includes four transistors (a read selection transistor 34, a reset transistor 36, a vertical selection transistor 40, and an amplification transistor 42) having different functions as basic elements in addition to the charge generation unit 32. This is the same for the effective pixel portion 10a as well as the shaded pixel portion 10b shown in the figure. The read selection transistor 34, the reset transistor 36, and the amplification transistor 42 (amplifier transistor) together with the floating diffusion 38 constitute a pixel signal generation unit 5 (signal output unit). The pixel signal generation unit 5 and the vertical selection transistor 40 constitute a signal output unit 6 that generates and outputs a pixel signal voltage Vx corresponding to the signal charge generated by the charge generation unit 32. The transistors 34, 36, 40, and 42 are collectively referred to as pixel transistors.

  The gate of the read selection transistor 34 (transfer transistor / read transistor) constituting the transfer unit is connected to the transfer wiring 54 in common with the gate in the same row, and is driven by the transfer signal TRG. The gate of the reset transistor 36 constituting the initialization unit is connected to the reset wiring 56 in common with the gate in the same row and is driven by the reset signal RST. The gate of the vertical selection transistor 40 (select transistor) is connected to the vertical selection line 58 in common with the gate in the same row, and is driven by the vertical selection signal VSEL. The transfer wiring 54, the reset wiring 56, and the vertical selection line 58 are the row control lines 15 in FIG.

  The transfer signal TRG, the reset signal RST, and the vertical selection signal VSEL generally use binary pulses of active H (high; power supply voltage level) and inactive L (low: reference level). The power supply voltage level is about 3V, for example. The reference level is, for example, 0.4 to 0.7 V or the ground level of 0 V. However, depending on the case, a part or all of the pulses are set to a negative potential of about −1 V.

  The charge generation unit 32, which is an example of a detection unit including a light receiving element DET such as a photodiode PD, has a reference potential Vss (negative potential: about −1V, for example) at which one end (anode side) of the light receiving element DET is a low potential side. The other end (cathode side) is connected to the input end (typically the source) of the read selection transistor 34. Note that the reference potential Vss may be the ground potential GND. The read selection transistor 34 has an output terminal (typically a drain) connected to a connection node to which the reset transistor 36, the floating diffusion 38 and the amplification transistor 42 are connected. The reset transistor 36 has a source connected to the floating diffusion 38 and a drain connected to a reset power supply Vrd (usually shared with the analog pixel power supply Vdd).

  For example, the vertical selection transistor 40 has a drain connected to the source of the amplification transistor 42, a source connected to the pixel line 51, and a gate (particularly referred to as a vertical selection gate SELV) connected to the vertical selection line 58. The pixel line 51 is connected to the vertical signal line 19 in common with the pixel line 51 in the same column. The amplification transistor 42 has a gate connected to the floating diffusion 38, a drain connected to the power source Vdd, a source connected to the pixel line 51 via the vertical selection transistor 40, and further connected to the vertical signal line 19. .

  One end of the vertical signal line 19 extends to the pixel signal readout unit 426 (column signal processing unit 450) side, and the readout current source unit 24 is connected in the path. The read current control unit 24 is not shown in detail, but has a load MOS transistor for each vertical column, and a gate is connected between the reference current source unit and the transistor to form a current mirror circuit. The vertical signal line 19 functions as a current source 24a. A source follower configuration in which a substantially constant operating current (readout current) is supplied to the amplification transistor 42 is adopted.

  As illustrated, the light-shielding pixel portion 10b is arranged on one side of the effective pixel portion 10a in the column direction. The light-shielding pixel portion 10b shares all the vertical signal lines 19 with the effective pixel portion 10a. For this reason, the pixel signal read from the light-shielding pixel unit 10b has a variation (FPN: fixed pattern noise) inherent to the pixel signal reading unit 426, as is the pixel signal (effective pixel signal) read from the effective pixel unit 10a. Will be affected.

  In the arrangement example shown in FIG. 2, the light-shielding pixel unit 10b is arranged below the effective pixel unit 10a (on the pixel signal readout unit 426 side), but this is arranged above the effective pixel unit 10a (pixel signal readout unit). You may arrange | position on the opposite side to 426. The number of dots in one line (number of pixels in the row direction) of the light-shielding pixel portion 10b is determined according to the effective pixel portion 10a, but the number of lines (number of pixels in the column direction) is at least one line of the light-shielding pixel portion 10b. As long as it is, it is optional. In the figure, two lines are shown.

  Each unit pixel 3 of the light-shielding pixel portion 10b has the same configuration as the unit pixel 3 of the effective pixel portion 10a, but its surface is covered with the light-shielding layer 1a to prevent the influence of external light. However, even when there is no external light input, dark current is generated and its influence cannot be avoided.

  The pixel signal reading unit 426 is provided with a column signal processing unit 450 for each vertical signal line 19. The column signal processing unit 450 includes a CDS processing unit 452 and a horizontal selection unit 454 including a sampling switch. The CDS processing unit 452 calculates the difference between the voltage sampled and held at the black level and the voltage sampled and held at the pixel signal level corresponding to the accumulated charge with respect to the pixel signal of the effective pixel unit 10a or the light-shielding pixel unit 10b. Thus, the noise component superimposed on both voltages is canceled. The pixel signal level after this noise removal is held at the output of the CDS processing unit 452, and is further sampled dot-sequentially by a sampling switch that is sequentially turned on by a pulse supplied from the horizontal scanning unit 12 to the horizontal selection unit 454. The

  If the same amount of light enters the unit pixels 3 arranged two-dimensionally in parallel during the readout of the pixel signals, the amount of charge generated in each unit pixel 3 is the same and is output. Should also be constant. However, the variation of the current source 24a of the read current control unit 24, the variation of the capacitance in the CDS processing unit 452, the variation of the feedthrough of the sampling switch of the horizontal selection unit 454, the wiring of the pulse signal output from the horizontal scanning unit 12, and the like. Due to various factors such as variations in coupling capacitance with the horizontal signal line 18 (output bus), pixel signals are output with variations depending on the columns. The noise resulting from this variation is not random noise, but is fixed pattern noise that is always generated for each column by the same amount, and appears as vertical stripes in the image. This fixed pattern noise is similarly generated regardless of whether the signal is generated in the effective pixel portion 10a or the light-shielding pixel portion 10b.

  For this measure, the solid-state imaging device 1Z includes a correction signal output unit 9 as means for suppressing streak-like fixed pattern noise (vertical stripe noise). The correction signal output unit 9 controls the bias voltage of the test pixel unit 310 and the test pixel unit 310 which is the unit pixel 3 for testing provided for each column in addition to the effective pixel unit 10a and the light-shielding pixel unit 10b. A reference voltage generation unit 320 (bias unit) is included. The effective pixel portion 10a and the light-shielding pixel portion 10b are collectively referred to as the inside of the pixel, and the outside thereof is also referred to as the outside of the pixel.

  The solid-state imaging device 1Z further includes a column column common processing unit 340 that functions as a vertical signal line short circuit on one side of the pixel array unit 10 in the column direction (vertical direction). The column column common processing unit 340 is provided for each vertical signal line 19, and functions as a plurality of shunt transistors each having a source connected to the corresponding vertical signal line 19 and a drain commonly connected to the short-circuit line 347. A switch transistor 342 is provided. The gate of the common switch transistor 342 is connected to a common gate control line 348 and is controlled by the vertical scanning unit 14. When all the common switch transistors 342 are turned on under the control of the vertical scanning unit 14, the potentials of all the vertical signal lines 19 are equalized (equalized).

  The test pixel unit 310 includes a series circuit of an out-of-pixel amplifier transistor 312 that is an example of an amplification transistor and a test pixel selection transistor 314 that selects a test pixel. In contrast to the out-of-pixel amplifier transistor 312, the amplifying transistor 42 in the pixel is also referred to as an in-pixel amplifier transistor. Depending on the circuit configuration, there is a case where a selector for combining a plurality of systems of vertical signal lines 19 into one system is interposed between the pixel signal readout unit 426. In such a case, the out-of-pixel amplifier transistor 312 or the test pixel selection is selected. The transistor 314 can take either a configuration arranged on the input (ie, unit pixel 3) side of the selector or a configuration arranged on the output (ie, CDS processing unit 452) side of the selector, but the latter has a smaller number of elements. I'll do it.

  The out-of-pixel amplifier transistor 312 is turned on by the reference voltage generation unit 320 when acquiring correction data for removing vertical stripe noise, and operates in pairs with the amplification transistor 42 of the unit pixel 3 selected in the corresponding column. . The extra-pixel amplifier transistor 312 added for vertical stripe correction has its source connected to the drain of the test pixel selection transistor 314, its drain connected to the voltage supply line 316, and its gate in common with the other columns. Are connected to the gate control line 318. The gate control line 318 is connected to the reference voltage generation unit 320. The voltage applied to the voltage supply line 316 may be the same as the pixel power supply Vdd supplied to the unit pixel 3, or may be a positive voltage different from the pixel power supply Vdd. The gate length L and gate width W of the out-of-pixel amplifier transistor 312 added for vertical stripe correction are made as large as possible within the horizontal pixel pitch, and thus the out-of-pixel amplifier transistor added during vertical stripe correction. It is desirable that the size of 312 be sufficiently larger than the size of the amplification transistor 42 used in the unit pixel 3 (referred to as effective unit pixel 3a) of the effective pixel unit 10a.

  The source of the test pixel selection transistor 314 is connected to the corresponding vertical signal line 19, and each gate is controlled in common by SELDMY from the vertical scanning unit 14 (not shown). As an example of selecting the test pixel selection transistor 314 of the test pixel unit 310, as shown in FIG. 2A, the test pixel unit 310 is continuously selected before the pixel signal is read from the effective pixel unit 10a. There is a method. The reason why the test pixel unit 310 is continuously selected is to compress random noise included in the circuit unit by averaging in the vertical direction inside the correction circuit at the subsequent stage. However, the reading order and the upper and lower positions of the test pixel unit 310 are not limited.

  The reference voltage generation unit 320 is a circuit for setting the bias voltage so that the operation point is the same between the amplification transistor 42 and the out-of-pixel amplifier transistor 312 when the correction data is acquired. Therefore, when viewed from the vertical signal line 19, this is equivalent to an apparent increase in the size of the amplification transistor 42 of the effective unit pixel 3 a. Note that the bias voltage generated by the reference voltage generation unit 320 may be not only a DC level but also a multivalued potential such as a pulse.

  In general, when the gate length of a certain transistor is L and the gate width is W, the variation in threshold voltage between two adjacent pair transistors is proportional to (1 / LW) 1/2. Therefore, when the threshold voltage of the amplifying transistor 42 has a variation of 10 mV with a standard deviation σ, for example, the out-of-pixel amplifier transistor 312 is designed so that the gate length L and the gate width W are each 10 times that of the amplifying transistor 42. Then, the variation in threshold voltage of the out-of-pixel amplifier transistor 312 is reduced to a standard deviation σ of about 1 mV. Therefore, in this case, by using the out-of-pixel amplifier transistor 312 at the time of vertical stripe correction, the variation in the threshold voltage of the amplifier transistor can be reduced to 1/10.

  When the out-of-pixel amplifier transistor 312 having a size different from that of the amplifying transistor 42 is used as described above, it is desirable to align the operating points of the amplifying transistor 42 and the out-of-pixel amplifier transistor 312 by the reference voltage generation unit 320. In many cases, by simply using the out-of-pixel amplifier transistor 312 in which the gate length L and the gate width W are changed from those of the amplifying transistor 42, the operating point of the source follower of the amplifying transistor 42 and the outside of the correction signal output unit 9 are out of the pixel. The operating point of the amplifier transistor 312 is shifted. In this case, the variation of the load MOS transistor (current source 24a) constituting the amplifier transistor and the source follower cannot be accurately estimated. In order to prevent this, it is desirable to adjust the gate bias voltage of the out-of-pixel amplifier transistor 312 to a value different from the gate voltage (OB signal voltage) of the amplification transistor 42 according to the threshold difference.

  The reference voltage generation unit 320 is provided for this purpose, and is configured to switch the output level corresponding to the D phase with a resistance tap. The black level is obtained by always fixing the PHASE pulse to L level.

  Specifically, as illustrated in FIG. 2B (1), the reference voltage generation unit 320 includes a resistance circuit 510, a transistor 520, and switch circuits 530 and 540. The resistor circuit 510 has a configuration in which a plurality (five in the figure) of resistor elements 512 are connected in series, one end (resistor element 512_1 side) is connected to the power supply Vdd, and the other end (resistor element 512_5 side) ) Is connected to a reference potential (eg, ground potential) via the transistor 520. The control signal STBY is supplied to the gate of the transistor 520. When the control signal STBY is at the H level, the transistor 520 is turned on, and a constant current (≈a value obtained by dividing the power supply voltage Vdd by the combined resistance of each resistance element 512) flows through each resistance element 512 of the resistance circuit 510.

  The switch circuit 530 includes a switch 532 that selects and outputs a voltage at a connection point (referred to as a voltage dividing point) of each resistance element 512 of the resistance circuit 510. Each switch 532 is a pair of complementary switches (transfer gate and transmission gate) in which NMOS and PMOS are connected in parallel in a complementary manner. Each switch 532 has one terminal (input end) connected to each voltage dividing point of the resistance circuit 510 and the other terminal (output end) connected in common. Although not shown, each switch 532 receives a control signal for simultaneously turning on and off the NMOS and PMOS in order to switch the output level corresponding to the D phase. Which switch 532 is to be turned on is selected to be suitable for setting the output level corresponding to the D phase.

  The switch circuit 540 includes a switch 542, an inverter 544, and a PMOS 546. The switch 542 is a complementary switch similar to the switch 532. The PMOS 546 has a source terminal connected to the power supply Vdd and a drain terminal connected to the output terminal of the switch 542. A PHASE pulse is input to the input of the inverter 544, the gate of the PMOS 546, and the NMOS gate of the switch 542. The output of the inverter 544 is input to the PMOS gate of the switch 542.

  As shown in FIG. 2B (2), when the PHASE pulse is at the L level, the switch 542 is off, the PMOS 546 is on, and the power supply voltage Vdd is supplied to the gate of the out-of-pixel amplifier transistor 312. When the PHASE pulse is at the H level, the switch 542 is on, the PMOS 546 is off, and the potential at the voltage dividing point selected by the switch circuit 530 is supplied to the gate of the out-of-pixel amplifier transistor 312. The level of the bias voltage FDIN supplied to the gate of the out-of-pixel amplifier transistor 312 can be adjusted depending on which switch 532 of the switch circuit 530 is turned on (that is, by switching the resistance tap).

  Although the reference voltage generation unit 320 is different from the configuration described in Patent Document 1, the basic concept is the same. The bias voltage FDIN is set so that the operating point is the same between the in-pixel amplifier transistor (amplifying transistor 42) and the out-of-pixel amplifier transistor 312 when the correction data is acquired, and the test pixel (test pixel unit) The threshold value, size, etc. of the out-pixel amplifier transistor 312 of 310) are considered to be arranged in the same configuration as the amplification transistor 42 inside the pixel. Similarly, the threshold and size of the test pixel selection transistor 314 are considered to be arranged in the same configuration as the vertical selection transistor 40 inside the pixel.

  For example, by similarly arranging the test pixel unit 310 (the out-pixel amplifier transistor 312 and the test pixel selection transistor 314) at the lower part of the pixel array unit 10, it is possible to share the power supply and well with the pixel, and the layout. There is a merit that placement is superior (easy).

  Based on the bias voltage FDIN supplied to the out-of-pixel amplifier transistor 312, when the test pixel selection transistor 314 is turned on, it is output to the vertical signal line 19 as a DMY signal.

  By aligning the operating points of the amplification transistor 42 and the out-of-pixel amplifier transistor 312, a pixel signal (OB signal) output from the light-shielded pixel unit 10 b and a pixel signal (DMY signal) output from the out-of-pixel amplifier transistor 312 are obtained. The standard is almost the same. However, the DMY signal has a wider range than the OB signal because it is not affected by the dark current.

  The DMY signal is subjected to column processing by the column signal processing unit 450 of the pixel signal reading unit 426, and further input to the output processing unit 429c through the analog signal processing unit 429a and the AD conversion unit 429b shown in FIG. In the output processing unit 429c, a noise correction processing unit 429d (vertical stripe correction circuit) for correcting vertical stripe noise is provided. Although the configuration of the noise correction processing unit 429d is not particularly shown, for example, when a plurality of DMY signals are output, a circuit that removes random noise by taking the average of the DMY signals, and holds the average of the average as correction data And a subtraction circuit that reads correction data from the line memory and subtracts the correction data from the input effective pixel signal for each line when reading the effective pixel signal. As a result, the effective pixel signal after vertical stripe correction is output from the subtraction circuit.

  Compared to the case where the light-shielding pixel unit 10b does not include the charge generation unit 32 (photosensor), the signal variation due to the threshold voltage of the amplifier transistor depends on the size ratio of the amplification transistor 42, the out-pixel amplifier transistor 312 and the test pixel selection transistor 314. Is suppressed. As a result, the amount of residual CDS suppression is reduced as the variation in the input signal of the CDS processing unit 452 becomes smaller.

  The degree of suppression of the signal variation can be adjusted by changing the size ratio of the amplification transistor 42, the out-of-pixel amplifier transistor 312 and the test pixel selection transistor 314. That is, when the variation of the current source 24a is relatively large, if the transistor size ratio is excessively large, the variation of the current source becomes difficult to be reflected in the CDS input signal, and is reflected when the actual effective pixel signal is read out. The influence of the current source that is to be reduced is reduced in the DMY signal. In such a case, a part of the cause of the fixed pattern noise is ignored, and the vertical stripe may be enlarged. By optimizing the size ratio of the amplifying transistor 42, the out-of-pixel amplifier transistor 312 and the test pixel selection transistor 314 at the time of design, the variation in the signal due to the amplifier transistor is suppressed as much as possible within the range in which the vertical line noise due to the current source does not increase. Thus, the CDS suppression residue can be minimized.

  In addition, the solid-state imaging device 1Z of the comparative example includes a column row common processing unit 340 (a common switch transistor 342). As described above, the vertical stripes are caused by the variation in the current source 24a, the variation in the CDS processing unit 452, the variation in the sampling switch in the horizontal selection unit 454, the variation in the horizontal signal line 18 for each bus, and the horizontal signal line. It is considered that the variation of 18 coupling capacities is a factor. At this time, when the influence of the variation of the current source 24a on the vertical stripe is so small that other factors are dominant, the vertical signal line 19 is connected in parallel to connect the out-of-pixel amplifier transistor 312 and the test pixel selection. Transistor 314 is parallelized. The out-of-pixel amplifier transistor 312 originally has a relatively large size, so the variation in characteristics is small. However, when the variation is at a level of concern, by paralleling the out-of-pixel amplifier transistor 312 and the test pixel selection transistor 314, The contribution of the characteristic variation can be averaged, and as a result, the CDS suppression can be prevented and the factor causing the vertical stripe can be extracted more accurately.

  By the way, in the solid-state imaging device 1Z of the comparative example, by inputting the bias potential generated from the reference voltage generation unit 320 to the gate of the out-of-pixel amplifier transistor 312 via the gate control line 318 as shown in FIG. A technique is adopted in which the FPN component between pixels is suppressed and a signal output having a variation component that the CDS processing unit 452 itself has is obtained. This signal output is a correction signal for subtracting the vertical stripe component of the CDS processing unit 452 itself from the image during normal imaging. That is, it is preferable that the signal input to the CDS processing unit 452 does not include a noise component or an offset component in order to extract a variation component included in the CDS processing unit 452 itself. These noise components may be subtracted by the CDS processing unit 452, but these components cannot be completely removed.

  Therefore, by adopting a configuration in which the common switch transistor 342 attached to each column row is turned on, variation components corresponding to the threshold voltage of the amplification transistor 42 and the on-resistance of the vertical selection transistor 40 are suppressed, and the CDS processing unit 452 has The variation component of the input pixel signal is reduced. As a result, since the remaining CDS can be reduced, the vertical stripe component of the CDS processing unit 452 itself can be extracted, and the FPN of the vertical stripe component can be suppressed by performing the correction process.

  However, in the solid-state imaging device 1Z of the comparative example, each column has a variation component of the threshold voltage of the out-of-pixel amplifier transistor 312 and the on-resistance of the test pixel selection transistor 314. The common switch transistor 342 contributes to suppress (referred to as equalize) the variation component, but due to the on-resistance component of the common switch transistor 342, the variation cannot be sufficiently removed. That is, even if equalization is performed by the common switch transistor 342, it cannot be equalized with high accuracy due to the on-resistance component of the common switch transistor 342.

  In order to perform equalization with high accuracy, it is necessary to reduce the input variation (that is, the variation component of the test pixel unit 310) or increase the size so as to reduce the on-resistance component of the common switch transistor 342. However, even if the common switch transistor 342 is turned on, the above-described variation cannot be sufficiently removed when it is not possible to spend a sufficient time for convergence or when the size of the common switch transistor 342 cannot be increased. As a result, a vertical stripe component may remain.

  Further, a space for arranging the common switch transistor 342 is required. In recent years, with the reduction in noise of the solid-state imaging device, a minute vertical stripe component may be conspicuous, and therefore, it is required to further remove the variation component input to the CDS processing unit 452.

  As described above, in the solid-state imaging device 1Z of the comparative example, from the viewpoint of suppression of fixed pattern noise, although a considerable improvement has been made by adopting a mechanism using an out-pixel amplifier transistor, There is room for further improvement in terms of space.

<Noise Suppression Function: First Embodiment>
FIG. 3 is a diagram illustrating the solid-state imaging device 1 </ b> A according to the first embodiment, focusing on each part related to noise suppression. Compared with the solid-state imaging device 1Z of the comparative example shown in FIG. 2, a short-circuit line 317 is provided for commonly connecting (short-circuiting) the terminals (sources) on the vertical signal line 19 side of the out-pixel amplifier transistors 312 of each column. Yes. Other points are the same as those of the solid-state imaging device 1Z of the comparative example. With this configuration, the test pixel selection transistor 314 is connected to the vertical signal line 19 in the same connection relationship as the common switch transistor 342 and is provided for each vertical signal line 19. , Each source can be connected to a corresponding vertical signal line 19, and the drain can function as a shunt transistor commonly connected by a short-circuit line 317. For example, by supplying active H to the gates of all the test pixel selection transistors 314, the potentials of all the vertical signal lines 19 are equalized.

  In addition, the short-circuit line 317 also short-circuits the source of each out-of-pixel amplifier transistor 312, and each vertical line is connected via the test pixel selection transistor 314 in a state where the out-of-pixel amplifier transistor 312 is equivalently connected in parallel. This contributes to the signal line 19. The out-of-pixel amplifier transistor 312 and the test pixel selection transistor 314 are paralleled by the short-circuit line 317, and the potentials of the source terminals of all the out-of-pixel amplifier transistors 312 are equalized (equalized). The source potential is transmitted to the vertical signal line 19 via the test pixel selection transistor 314.

  Not only are all the common switch transistors 342 turned on to connect the vertical signal lines 19 in common, but the connection points of the out-of-pixel amplifier transistors 312 and the test pixel selection transistors 314 are connected in common by the short-circuit line 317 to the outside of the pixels. By paralleling the amplifier transistor 312 and the test pixel selection transistor 314, the contributions of their characteristic variations can be averaged.

  If the source part of the out-of-pixel amplifier transistor 312 is reduced, the threshold variation of the out-of-pixel amplifier transistor 312 will not be short-circuited (assuming that the metal resistance component can be ignored), so only the on-resistance variation component of the test pixel selection transistor 314 As a result, the equalization characteristic is improved.

  As a result, it is possible to extract the cause of the vertical stripes by preventing the CDS suppression remaining more accurately than the solid-state imaging device 1Z of the comparative example, and the vertical stripe noise can be further suppressed. The characteristic variation can be reduced as compared with the case where the present embodiment is not applied, and as a result, the vertical stripe suppression effect is enhanced.

  When attention is paid to each circuit configuration of the unit pixel 3 and the test pixel unit 310 of the present embodiment, the arrangement relationship between the out-of-pixel amplifier transistor 312 and the test pixel selection transistor 314 is the amplification transistor 42 and the vertical selection transistor 40 on the unit pixel 3 side. It is the same as the arrangement relationship. The circuit configuration is matched, and this also has an advantage that contributes to the enhancement effect of the vertical stripe noise.

  By short-circuiting the terminal on the vertical signal line 19 side of the out-of-pixel amplifier transistor 312 in the test pixel unit 310 with the short-circuit line 317, the variation component of the threshold voltage of the out-of-pixel amplifier transistor 312 is short-circuited at the source of the out-of-pixel amplifier transistor 312. Is absorbed by the shorting wire 317. As a result, since the variation component of the pixel signal input to the CDS processing unit 452 can be reduced and the remaining CDS can be reduced as compared with the comparative example, the CDS processing unit 452 itself can be obtained by performing the correction process. Can be obtained. In other words, an image can be obtained in which vertical variation FPN is suppressed. At this time, a DC level or a pulse can be input as a bias voltage to the gate of the out-of-pixel amplifier transistor 312 from the reference voltage generation unit 320, and a signal level in which dark and bright FPN are suppressed can be obtained. .

  Further, in comparison with the mechanism described in Patent Document 2, the following can be said. In the mechanism of Patent Document 2, there is no description or suggestion regarding correcting the noise of the vertical line component of gain as in the present embodiment. The correction signal obtained by the mechanism described in Patent Document 2 is only for the black level.

  In Patent Document 1 (FIG. 4), out-of-pixel amplifier transistors are used to obtain correction data for removing vertical stripe noise (usually equivalent to a white level), and further, a shunt structure is used. In addition, a shunt transistor is used. On the other hand, in Patent Document 2, since only the black level is obtained, the configuration is one transistor per column. For example, in FIG. 3 of Patent Document 2, the potential between the vertical signal lines is merely set to the same potential by inputting the H level to the control pulse P1 in the initial stage of turning on the apparatus power. Correction data for removal cannot be acquired. In other words, Patent Document 2 proposes the structure of only the shunt transistor portion of Patent Document 1 (FIG. 4), and only proposes the case where there is no out-of-pixel amplifier or bias circuit. .

<Noise Suppression Function: Second Embodiment>
FIG. 4 is a diagram illustrating the solid-state imaging device 1B of the second embodiment, focusing on each part related to noise suppression. Compared with the solid-state imaging device 1A of the first embodiment shown in FIG. 3, the column column commonization processing unit 340 (commonization switch transistor 342) is removed. Other points are the same as those of the solid-state imaging device 1A of the first embodiment.

  The source of the test pixel selection transistor 314 is connected to the corresponding vertical signal line 19, and each gate is controlled in common by SELDMY from the vertical scanning unit 14 (not shown). First, the test pixel selection transistor 314 is connected to the vertical signal line 19 in the same connection relationship as the common switch transistor 342, and is provided for each vertical signal line 19, and each source has a corresponding vertical signal. It can function as a shunt transistor connected to the line 19 and having a common drain. For example, by supplying active H to the gates of all the test pixel selection transistors 314, the potentials of all the vertical signal lines 19 are equalized.

  As described above, in the case where the column column common processing unit 340 (the common switch transistor 342) is deleted, if the sizes of the common switch transistor 342 and the test pixel selection transistor 314 are the same, the solid state of the comparative example is obtained. An effect equivalent to that of the imaging device 1Z can be obtained.

  On the pixel array unit 10 side of the CDS processing unit 452, layout restrictions may be large. In that case, the vertical signal line 19 side of the out-of-pixel amplifier transistor 312 is short-circuited by the short-circuit line 317 while removing the column-column common processing unit 340 (common switch transistor 342) as in the mechanism of the second embodiment. In addition, by adopting a configuration in which each is connected to the vertical signal line 19 of each column via the test pixel selection transistor 314, the FPN can be efficiently suppressed within the space allowed in the layout.

  In contrast to the comparative example shown in FIG. 2, the space can be improved by short-circuiting the source of the out-of-pixel amplifier transistor 312 without providing the common switch transistor 342. Incidentally, in order to keep equalizing characteristics equal to or higher, the on-resistance component requires that the test pixel selection transistor 314 be larger than the common switch transistor 342.

  As the solid-state imaging device operates at higher speed, there is a demand for equalization of the variation component input to the CDS processing unit 452 at a high speed. In this regard, in both the first and second embodiments, convergence is achieved. Problems related to the time taken will be improved.

<Noise suppression function: Combination with pixel circuit modification>
FIG. 5 is a diagram for explaining a modification of the first and second embodiments, focusing on each part related to noise suppression. The difference from the first and second embodiments is that the configuration of the unit pixel 3 on the pixel array unit 10 side is different. As an example, the test pixel unit 310 has the configuration of the first embodiment, but the test pixel unit 310 of the second embodiment may be applied.

  The mechanism of the present embodiment only needs to have a configuration in which the source side of the out-of-pixel amplifier transistor 312 is made common as the test pixel and the test pixel selection transistor 314 is interposed for each column. The basic purpose, effect, and operation of the test pixel unit 310 are not affected by the configuration of the pixel array unit 10 on the unit pixel 3 side.

  In the modification shown in FIG. 5, the arrangement of the vertical selection transistor 40 and the amplification transistor 42 in the unit pixel 3 is reversed. That is, the vertical selection transistor 40 has a drain connected to the power supply Vdd, a source connected to the drain of the amplification transistor 42, and a source of the amplification transistor 42 connected to the pixel line 51.

  In such a modification, the connection relationship between the vertical selection transistor 40 and the amplification transistor 42 in the unit pixel 3 is opposite to the connection relationship between the out-of-pixel amplifier transistor 312 and the test pixel selection transistor 314 in the test pixel unit 310. Therefore, in the configuration of the unit pixel 3 in the first and second embodiments, the arrangement of the amplification transistor and the selection transistor in the test pixel unit 310 is matched. The form is more advantageous.

<Noise Suppression Function: Third Embodiment>
FIG. 6 is a diagram illustrating a solid-state imaging device 1 </ b> C according to the third embodiment, focusing on each part related to noise suppression. The solid-state imaging device 1 according to the third embodiment is a modification of the first embodiment, in which the configuration after the pixel signal reading unit 426 is modified to a so-called column AD system, and the test pixel unit 310 and the reference voltage generation unit 320 and the column column sharing processing unit 340 are the same as those in the first embodiment. Although illustration is omitted, it is also possible to adopt a mode in which the column AD system is modified based on the second embodiment that does not include the column column common processing unit 340 (common switch transistor 342).

  In a so-called XY address type solid-state imaging device, for example, a plurality of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit, and signal charges corresponding to incident light are accumulated for each line (row) or pixel. Is started, and a current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by addressing. Here, in the MOS (including CMOS) type, as an example of address control, a column readout method (column parallel output method) in which one row is accessed simultaneously and a pixel signal is read from the pixel unit in units of rows is often used. ing. The analog pixel signal read from the pixel unit is converted into digital data by an analog-digital converter (AD converter / ADC: Analog Digital Converter) as necessary. For this reason, various AD conversion mechanisms have been proposed.

  As an AD conversion method, various methods are considered from the viewpoint of circuit scale, processing speed (high speed), resolution, and the like. As an example, there is a reference signal comparison type AD conversion method. The reference signal comparison type is also referred to as a slope integration type or a ramp signal comparison type. In the reference signal comparison type AD conversion method, a so-called ramp-like reference signal whose ramp value changes gradually (ramp wave: having a predetermined amplitude and inclination: staircase wave) for voltage comparison for conversion into digital data. May be used). Then, the analog unit signal and the reference signal are compared, and the digital data of the unit signal is acquired based on the count value obtained by performing the count process during the count operation effective period based on the comparison process result. By combining a reference signal comparison type AD conversion method and the above-described column readout method (referred to as a column AD method), analog output from pixels can be AD-converted in parallel in a low band and with high image quality. It can be said that it is suitable for an image sensor that achieves both high speeds.

  For example, in recent years, CMOS sensors have been widely installed in mobile phones, digital cameras (compact and high-end single-lens reflex cameras), camcorders, surveillance cameras, and guidance devices, taking advantage of low power consumption and high speed. It has become to. In recent years, high-performance, high-quality CMOS sensors that have on-chip functional circuit blocks such as image processing have begun to appear. It is conceivable to apply a reference signal comparison type AD conversion method to these, and the third embodiment is similar to the first embodiment in the FPN suppression in combination with such a reference signal comparison type AD conversion method. Apply technology.

  A solid-state imaging device 1C according to the third embodiment includes a pixel array unit 10, a horizontal scanning unit 12, a vertical scanning unit 14, a PLL circuit 20x, a system control unit 20y that controls the whole, and a column AD conversion that is an example of a pixel signal reading unit. A reference signal generation unit 27 that generates a reference signal SLP_ADC, a sense amplifier 28a, a signal processing / interface unit 28z, and the like. The horizontal scanning unit 12, the vertical scanning unit 14, the PLL circuit 20x, and the system control unit 20y constitute the drive control unit 7. The signal processing / interface unit 28z has a function of a noise correction processing unit 429d.

  In the pixel array unit 10, the unit pixels 3 are arranged in a two-dimensional matrix. Although not shown in the figure, the pixel array section 10 is provided with an effective pixel section 10a and a light-shielding pixel section 10b as in the first embodiment. The PLL circuit 20x generates an internal clock CKX based on a basic clock CK input from the outside, and supplies the internal clock CKX to the reference signal generation unit 27 and the counter unit 254.

  In the column AD conversion unit 26, an AD conversion unit 250 (an example of a column signal processing unit) having a CDS processing function and a digital conversion function is provided in a column in parallel. The reference signal generator 27 supplies a reference signal SLP_ADC for AD conversion to the column AD converter 26. The horizontal scanning unit 12 indicates the column position of data to be read out during the data transfer operation.

<Column AD method>
Various methods are considered as an AD conversion method in the AD conversion unit 250 from the viewpoint of circuit scale, processing speed (high speed), resolution, and the like. As an example, a reference signal comparison type, a slope integration type, or a ramp An AD conversion method called a signal comparison type is adopted. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel. In the reference signal comparison type AD conversion, the count operation effective period Ten is determined based on the time from the conversion start (comparison process start) to the conversion end (comparison process end) (here, a count enable indicating the period). The signal to be processed is converted into digital data based on the number of clocks in that period.

  When adopting the reference signal comparison type AD conversion method, as a way of thinking, it is conceivable to provide the reference signal generation unit 27 in parallel in each column (for each pixel column). For example, a configuration in which a comparator and a reference signal generator are provided in each pixel column, and the value of the reference signal is sequentially changed by the reference signal generator of the corresponding column based on the comparison result of the comparator in its own column. This is the case. However, this increases the circuit scale and power consumption. Therefore, in the third embodiment, a configuration is adopted in which the reference signal generation unit 27 is used in common for all the columns, and the AD conversion unit 250 for each pixel column uses the reference signal SLP_ADC generated from the reference signal generation unit 27 in common. Make the configuration.

  The AD conversion unit 250 for each vertical column (column) includes a comparison unit 252 and a counter unit 254. As an example, the counter unit 254 has a ripple counter (Ripple Counter) format in which 13 stages of latches LT_00 to LT_12 are connected in series, and has a 13-bit configuration in which up-counting and down-counting are switchably connected.

  Data D0 to D12 output from the counter unit 254 are sent to the sense amplifier 28a via the horizontal signal line 18 at a small amplitude level (for example, several hundred mVp-p). The sense amplifier 28a amplifies the small amplitude level data D0 to D12 to a logic level (for example, 2 to 3 Vp-p) and passes the amplified data to the signal processing / interface unit 28z. The signal processing / interface unit 28z performs predetermined digital signal processing on the 13-bit data D0 to D12, and passes it to the subsequent circuit (not shown) as 12-bit output data Dout (D0 to D11).

  The AD conversion operation is as follows. First, the pixel signal voltage Vx is read from the unit pixel 3 through the vertical signal line 19 to the column AD conversion unit 26 side. The comparison unit 252 compares the pixel signal voltage Vx with the reference signal SLP_ADC from the reference signal generation unit 27, and supplies the comparison result to the first-stage latch LT of the counter unit 254. The latch LT is also supplied with an internal clock CKX from the clock converter 20a. The counter unit 254 performs a counting operation when the comparison result of the counter unit 254 is H, for example. By acquiring the count result as digital data of the pixel signal voltage Vx, AD conversion is realized. In other words, an AD converter is provided for each vertical column, and the pixel signal voltage Vx (analog signal) of each unit pixel 3 is collectively read to each vertical signal line 19 for the selected row, and the reset level and signal of the pixel signal voltage Vx are read. Direct AD conversion is performed for each level.

  By using an up / down counter as the counter unit 254, difference processing of each AD conversion result of the reset level Srst and the signal level Ssig is simultaneously performed in the AD conversion process. By performing reference signal comparison type AD conversion processing for each vertical column, CDS processing is performed in the digital domain. This eliminates the disadvantages of performing CDS processing in the analog domain, and can perform highly accurate noise removal. Since this column AD method is parallel processing for each horizontal line of the screen, it is not necessary to drive at high frequency for horizontal scanning, and AD conversion requires only a low-speed scanning frequency in the vertical direction. And the signal component can be easily separated.

  The applicant of the present invention has proposed various reference signal comparison type AD conversion methods, which can basically be employed in the third embodiment. In any of the processing examples, in principle, the reference signal SLP_ADC is supplied to the comparator (voltage comparator), the analog pixel signal input via the vertical signal line 19 is compared with the reference signal SLP_ADC, and counting is performed. When the operation valid period Ten is entered, counting by the clock signal is started, and AD conversion is performed by counting the number of clocks in the designated count operation valid period Ten.

  Here, when paying attention to the variation of the pixel signal voltage Vx due to the column, when the column AD method is adopted, the CDS processing unit 452 that performs the CDS processing in the analog region is not provided, and therefore the inside of the CDS processing unit 452. Variations in capacitance of the horizontal selection unit 454, feedthrough variation in sampling switch of the horizontal selection unit 454, variation in coupling capacitance between the wiring of the pulse signal output from the horizontal scanning unit 12 and the horizontal signal line 18 (output bus) are eliminated. obtain. However, the variation of the current source 24a of the read current control unit 24 remains, and the variation of the comparison unit 252 included in the AD conversion unit 250 is newly added, so that FPN caused by these variations still appears as vertical stripes in the image. .

  Therefore, in the solid-state imaging device 1C of the third embodiment, the test pixel unit 310, the reference voltage generation unit 320, and the column column commonization processing unit 340 are arranged as in the comparative example, and further, similarly to the first embodiment. A short-circuit line 317 for connecting (short-circuiting) the terminals (sources) on the vertical signal line 19 side of the out-pixel amplifier transistors 312 in each column is provided.

  In this way, not only the common switch transistors 342 are turned on and the vertical signal lines 19 are connected in common, but also the connection point between the out-pixel amplifier transistor 312 and the test pixel selection transistor 314 is shared by the short-circuit line 317. By connecting and connecting the out-of-pixel amplifier transistor 312 and the test pixel selection transistor 314 in parallel, the contribution of their characteristic variations can be averaged, and the same effect as in the first embodiment can be enjoyed.

<Imaging Device: Fourth Embodiment>
FIG. 7 is a diagram illustrating an imaging apparatus according to the fourth embodiment. In the fourth embodiment, the mechanism of vertical stripe noise suppression processing employed in each embodiment of the solid-state imaging device 1 described above is applied to an imaging device that is an example of a physical information acquisition device. FIG. 7 is a schematic configuration diagram of the imaging apparatus 8. The main components are described as follows (excluding the main components are omitted).

  The imaging device 8 includes a photographing lens 802, an optical low-pass filter 804, a color filter group 812, a pixel array unit 10, a drive control unit 7, a column AD conversion unit 26, a reference signal generation unit 27, and a camera signal processing unit 810. . As indicated by a dotted line in the drawing, an infrared light cut filter 805 that reduces an infrared light component can be provided together with the optical low-pass filter 804. The camera signal processing unit 810 provided at the subsequent stage of the column AD conversion unit 26 includes an imaging signal processing unit 820 and a camera control unit 900 that functions as a main control unit that controls the entire imaging apparatus 8. The imaging signal processing unit 820 includes a signal separation unit 822, a color signal processing unit 830, a luminance signal processing unit 840, and an encoder unit 860.

  The solid-state imaging device 1 employs the solid-state imaging device 1C of the third embodiment, and an out-of-pixel amplifier transistor 312 and a test pixel selection transistor 314 that form a test pixel unit 310 (not shown) of the correction signal output unit 9. Are connected by a short-circuit line 317. Incidentally, the signal processing / interface unit 28z is not provided with the function of the noise correction processing unit 429d. Although not shown, the imaging device 8 may be configured based on the solid-state imaging devices 1A and 1B of the first and second embodiments.

  The camera control unit 900 according to this embodiment includes a microprocessor 902, a read only memory (ROM) 904, a RAM 906 (Random Access Memory), and other peripheral members that are not shown. ing. The microprocessor 902 is the same as the one that forms the center of an electronic computer whose representative example is a CPU (Central Processing Unit) that integrates the functions of computation and control performed by a computer into an ultra-small integrated circuit. The RAM 906 is an example of a volatile storage unit that can be written and read at any time. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer.

  The camera control unit 900 controls the entire system. In particular, in relation to the vertical streak noise suppression processing of the present embodiment, correction data acquisition and noise suppression processing (noise correction processing) using the correction data are performed. It has a function to control. In other words, the camera control unit 900 has the function of the noise correction processing unit 429d of the first to third embodiments, and each vertical signal line 19 when a signal corresponding to the reference voltage is given to each vertical signal line 19. The noise correction data is generated and held for each vertical signal line 19 based on the data output from the column AD conversion unit 26 (AD conversion unit 250). Furthermore, the camera control unit 900 having the function of the noise correction processing unit 429d is configured to output data output from the column AD conversion unit 26 (AD conversion unit 250) when reading the processing target signal (pixel signal voltage Vx) from the unit pixel 3. Vertical stripe noise is corrected based on the stored noise correction data. The color signal processing unit 830 and the luminance signal processing unit 840 perform color signal processing and luminance signal processing using data in which vertical stripe noise is corrected. Note that the camera control unit 900 may have only a control function for the vertical stripe noise suppression processing, and a digital calculation unit that performs the function of the noise correction processing unit 429d by digital calculation processing may be provided in the camera signal processing unit 810 separately. . In this way, corrected data can be acquired at high speed.

  The ROM 904 stores a control program for the camera control unit 900. In this example, in particular, the camera control unit 900 stores a program for controlling vertical stripe noise suppression processing. The RAM 906 stores data for the camera control unit 900 to perform various processes.

  The camera control unit 900 is configured such that a recording medium 924 such as a memory card can be inserted and removed, and can be connected to a communication network such as the Internet. For example, the camera control unit 900 includes a memory reading unit 907 and a communication I / F (interface) 908 in addition to the microprocessor 902, the ROM 904, and the RAM 906.

  The recording medium 924 includes, for example, program data for causing the microprocessor 902 to perform software processing, a convergence range of the photometric data DL based on the luminance system signal from the luminance signal processing unit 840, and exposure control processing (including electronic shutter control). It is used for registering various data such as various control information and correction data for vertical stripe noise suppression processing. The memory reading unit 907 stores (installs) the data read from the recording medium 924 in the RAM 906. The communication I / F 908 mediates transfer of communication data with a communication network such as the Internet.

  In the imaging device 8, the drive control unit 7 and the column AD conversion unit 26 are shown as modules separately from the pixel array unit 10, but as described for the solid-state imaging device 1. Needless to say, a one-chip solid-state imaging device 1 in which these are integrally formed on the same semiconductor substrate as the pixel array unit 10 may be used. In the figure, in addition to the pixel array unit 10, the drive control unit 7, the column AD conversion unit 26, the reference signal generation unit 27, and the camera signal processing unit 810, a photographing lens 802, an optical low-pass filter 804, or an infrared light cut filter 805. The image pickup apparatus 8 is shown in a state including an optical system such as the above, and this aspect is suitable for a module-like form having an image pickup function packaged together. Such an imaging device 8 is provided as a portable device having an imaging function, for example, for performing “imaging”. Note that “imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  Also in the imaging device 8 having such a configuration, the connection point between the out-pixel amplifier transistor 312 and the test pixel selection transistor 314 constituting the test pixel unit 310 of the correction signal output unit 9 is connected by the short-circuit line 317, By performing the vertical streak noise suppression process on the signal voltage Vx, the same effects as those of the first and third embodiments can be obtained. At this time, for example, at least the control of the reference voltage generation unit 320 for acquiring correction data and other units, and the control related to the vertical stripe noise suppression processing using the acquired / held correction data, In the external main control unit (camera control unit 900), control instruction information can be arbitrarily designated by data setting for the communication / timing control unit 20.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, the CMOS image sensor has been described as a representative example. However, the CMOS image sensor may be applied to an image input device such as a digital still camera or a digital video camera. The imaging device 8 of 4th Embodiment is the example. Incidentally, it is preferable that the out-of-pixel amplifier transistor 312, the test pixel selection transistor 314, and the short-circuit line 317 provided in the above-described embodiment are built in the same semiconductor region as the pixel array unit 10, such as the post-stage signal processing unit 429. Other circuits can be arbitrarily formed outside the solid-state imaging device 1 as separate integrated circuits, or can be realized by circuits mounted on a printed circuit board or the like. However, since a CMOS process is used in the CMOS image sensor, it is easy to incorporate a necessary circuit and the characteristics are improved. Therefore, it is desirable to incorporate the necessary circuit in the solid-state imaging device 1 (CMOS image sensor). .

1 is a basic configuration diagram of a CMOS type solid-state imaging device. It is the figure which showed the solid-state imaging device of the comparative example paying attention to each part in connection with noise suppression. It is a timing chart explaining the drive method of an amplifier outside a pixel. It is a figure which shows the structural example of a reference voltage production | generation part. It is the figure which showed the solid-state imaging device of 1st Embodiment paying attention to each part in connection with noise suppression. It is the figure which showed the solid-state imaging device of 2nd Embodiment paying attention to each part in connection with noise suppression. It is a figure explaining the modification with respect to 1st, 2nd embodiment. It is the figure which showed the solid-state imaging device of 3rd Embodiment paying attention to each part in connection with noise suppression. It is a figure explaining the imaging device of a 4th embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 1a ... Light-shielding layer, 10 ... Pixel array part, 10b ... Light-shielding pixel part, 10a ... Effective pixel part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 18 ... Horizontal signal line, 19 ... Vertical Signal line 20 ... Communication / timing control unit 3 ... Unit pixel 32 ... Charge generator 34 ... Read selection transistor 36 ... Reset transistor 38 ... Floating diffusion 40 ... Vertical selection transistor 42 ... Amplification transistor (pixel) (Inner amplifier transistor), 310 ... test pixel section, 312 ... out-pixel amplifier transistor, 314 ... test pixel selection transistor, 317 ... short circuit line, 318 ... gate control line, 320 ... reference voltage generation section, 340 ... common to column columns Processing unit, 342... Common switch transistor, 42... Amplification transistor, 426. 429 ... Post-stage signal processing unit, 429d ... Noise correction processing unit, 450 ... Column signal processing unit, 452 ... CDS processing unit, 5 ... Pixel signal generation unit, 7 ... Drive control unit, 8 ... Imaging device, 9 ... Correction signal Output unit, 900 ... camera control unit

Claims (4)

A charge generation unit that generates a signal charge; an amplification transistor that generates and amplifies a signal voltage based on the signal charge generated by the charge generation unit to generate a signal to be processed; and the signal charge generated by the charge generation unit A plurality of unit pixels each including a transfer transistor that transfers to an input terminal of an amplification transistor, a reset transistor that initializes the input terminal of the amplification transistor, and a selection transistor that selects and outputs a processing target signal generated by the amplification transistor. A pixel array portion disposed; and
A plurality of column signal lines for transmitting signals to be processed selected by the selection transistors;
A pixel signal readout unit comprising a plurality of column signal processing units for performing signal processing by reading out a signal to be processed through the column signal lines;
A reference voltage generation unit that generates a reference voltage and supplies the reference line to the control line;
Between the control line and each column signal line, an amplification transistor outside the pixel having a larger size than the amplification transistor of the unit pixel arranged on the control line side and outside the pixel arranged on the column signal line side A series circuit of select transistors,
A short-circuit line commonly connecting a connection point of the amplification transistor outside the pixel and the selection transistor in each of the series circuits;
A solid-state imaging device. The solid-state imaging device according to claim 1, further comprising a switch capable of electrically shorting the plurality of column signal lines. The solid-state imaging device according to claim 1, wherein the unit pixel includes the selection transistor between the amplification transistor and the column signal line. A charge generation unit that generates a signal charge; an amplification transistor that generates and amplifies a signal voltage based on the signal charge generated by the charge generation unit to generate a signal to be processed; and the signal charge generated by the charge generation unit A plurality of unit pixels each including a transfer transistor that transfers to an input terminal of an amplification transistor, a reset transistor that initializes the input terminal of the amplification transistor, and a selection transistor that selects and outputs a processing target signal generated by the amplification transistor. A pixel array portion disposed; and
A plurality of column signal lines for transmitting signals to be processed selected by the selection transistors;
A pixel signal reading unit provided in parallel to the column signal line, and including a plurality of column signal processing units that perform signal processing by reading a signal to be processed from the unit pixel via the column signal line;
A reference voltage generation unit that generates a reference voltage and supplies the reference line to the control line;
Between the control line and each column signal line, the amplification transistor outside the pixel having a larger size than the amplification transistor of the unit pixel arranged on the control line side and the outside of the pixel arranged on the column signal line side A series circuit of select transistors,
A short-circuit line commonly connecting a connection point of the amplification transistor outside the pixel and the selection transistor in each of the series circuits;
A signal that is output from the column signal processing unit with respect to a signal that appears on each column signal line when the amplification transistor outside the pixel is driven by the reference voltage generation unit via the control line and the selection transistor is on. And generating and holding a noise correction signal for each column signal line, and generating noise based on the signal output from the column signal processing unit and the noise correction signal when the processing target signal is read from the unit pixel. A noise correction processing unit to correct,
An imaging apparatus comprising:

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