201135810 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置形成時的熱處理製程中，可抑制 矽基板側的雜質擴散於磊晶層之磊晶晶圓。 【先前技術】 半導體離散元件形成用基板係使用在含高濃度雜質的矽 基板上，具有石夕磊晶層（其係含有較該石夕基板更低濃度雜 質，以下簡稱「磊晶層」）的磊晶晶圓。 此種蠢晶晶圓係在半導體裝置形成時的熱處理製程中，會 發生珍基板中所含的同濃度雜質，擴散於蟲晶層的固態層擴 散現象。 特別係當雜質為填的情況，因為其擴散速度較快於其他雜 質，因而在半導體裝置形成時的熱處理製程中，磊晶層的雜 質濃度（比電阻）在深度方向會出現緩坡斜率，躍遷寬度 (transition width)(在具有不同雜質濃度的矽基板與磊晶層之 邊界附近’雜質濃度進行躍遷區域的寬度：圖2中的Tw) 擴大的現象會明顯發生。 因為此種躍遷寬度的擴大，會對半導體裝置的崩潰電壓等 原本必要的裝置特性造成不良影響，因而期待即便半導體褒 置形成時的熱處理製程後，躍遷寬度仍狹窄，且在石夕基板與 磊晶層間具有急遽電阻分佈的磊晶晶圓。 獲得躍遷寬度較狹窄、且電阻率分佈呈急遽、安定的蠢晶 099145745 3 201135810 晶圓之製造方法，有揭示切單晶上氣相沉積㈣單晶薄膜 構成的保護騎’再將已氣相沉_保護層的⑪單晶收容於 反應容器⑽狀態下’對該反應容⑼施行乾柄刻，再將 該反應容器内施行排淨(purge)，俾使上述所詩單晶層進行 氣相沉積的技術(例如日本專利特開平1〇_5〇616號公報（專 利文獻1))。 再者’有揭示：在晶圓表面上，磊晶成長出電阻率 10〜1500Qcm、且厚0.15〜3.0/zm的第i矽單晶膜再於上 述第1石夕單晶膜上，蟲晶成長出電阻率較小於上述第1石夕單 晶膜的第2矽單晶膜之技術（例如日本專利特開平 2007-81045號公報(專利文獻2))。 然而，该等專利文獻1、2所記載的技術，並非屬於在半 導體裝置形成時的熱處理製程中，抑制矽基板所含的高濃度 雜質擴散於磊晶層之技術。 . 【發明内容】 本發明係為解決上述技術課題而完成，其目的在於提供： 在半導體裝置形成時的熱處理製程中，能抑制^夕基板所含的 高濃度雜質，擴散於磊晶層的磊晶晶圓。 本發明的蠢晶晶圓’其特徵在於：在磷濃度為 l〇i9atoms/cm3級、氧濃度為1.3xl〇18atoms/cm3以下的石夕基 板上，設有磷濃度為l〇16at〇ms/cm3級、膜厚為0.5〜2〇vm 的矽磊晶層。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an epitaxial wafer in which an impurity on a side of a germanium substrate is diffused to an epitaxial layer in a heat treatment process in forming a semiconductor device. [Prior Art] The substrate for forming a semiconductor discrete element is used on a germanium substrate containing a high concentration of impurities, and has a stellite layer (which contains a lower concentration of impurities than the celestial substrate, hereinafter referred to as an "epitaxial layer"). Epitaxial wafer. Such a stray wafer is in a heat treatment process in the formation of a semiconductor device, and the same concentration of impurities contained in the substrate is diffused in the solid layer of the crystal layer. In particular, when the impurity is filled, since the diffusion speed is faster than other impurities, the impurity concentration (specific resistance) of the epitaxial layer exhibits a gentle slope in the depth direction during the heat treatment process in the formation of the semiconductor device, and the transition width (Transition width) (The width of the transition region where the impurity concentration is performed near the boundary between the tantalum substrate and the epitaxial layer having different impurity concentrations: Tw in Fig. 2) The phenomenon of enlargement occurs remarkably. Since the expansion of the transition width adversely affects the originally necessary device characteristics such as the breakdown voltage of the semiconductor device, it is expected that the transition width is narrow even after the heat treatment process at the time of formation of the semiconductor device, and the stone substrate and the lei are Epitaxial wafers with a sharp electrical resistance distribution between the layers. A method for manufacturing a wafer with a narrow transition width and a sharp and stable resistivity distribution is disclosed. The method for manufacturing a wafer is disclosed in which a single crystal is deposited on a single crystal (four) single crystal film to protect the ride. The 11 single crystal of the protective layer is placed in the state of the reaction vessel (10), and the reaction volume (9) is subjected to dry stalking, and then the inside of the reaction vessel is purged, and the above-mentioned single crystal layer is vapor-deposited. (Japanese Patent Laid-Open Publication No. Hei No. Hei-5 No. 616 (Patent Document 1)). Furthermore, it has been revealed that on the surface of the wafer, epitaxial growth of an ir-th crystal film having a resistivity of 10 to 1500 Qcm and a thickness of 0.15 to 3.0/zm is performed on the first singular single crystal film. A technique of growing a second ruthenium single crystal film having a smaller specific resistance than the first singular single crystal film (for example, Japanese Patent Laid-Open Publication No. Hei. No. 2007-81045 (Patent Document 2)). However, the techniques described in Patent Documents 1 and 2 do not belong to the technique of suppressing the diffusion of high-concentration impurities contained in the tantalum substrate into the epitaxial layer during the heat treatment process in the formation of the semiconductor device. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the invention is to provide a high-concentration impurity contained in a substrate and a diffusion of an epitaxial layer in a heat treatment process during formation of a semiconductor device. Crystal wafer. The amorphous wafer of the present invention is characterized in that a phosphorus concentration of l 〇 16 at 〇 ms is provided on a Shi Xi substrate having a phosphorus concentration of l〇i 9 atoms/cm 3 and an oxygen concentration of 1.3×10 ato 18 atoms/cm 3 or less. A tantalum epitaxial layer of cm3 grade and a film thickness of 0.5 to 2 〇vm.
099145745 4 S 201135810 根據本發明，可提供在半導體裝置形成時的熱處理製程 中，能抑制矽基板所含的高濃度雜質，擴散於磊晶層的磊晶 晶圓。 【實施方式】 發明者專確認到遙晶晶圓係含有雜質為鱗、且其濃产為 1 rv 19 atoms/cm3級南濃度雜質的石夕基板，且當在該石夕基板上 設有含有雜質為磷、且雜質濃度較該矽基板低3位數的 1016atoms/cm3級低濃度雜質之磊晶層時，在半導體裝置形 成時的熱處理製程中，會有躍遷寬度大幅變寬的傾向，因此 為解決該等技術課題，經深入鑽研的結果，遂完成本發明。 以下’針對本發明蠢晶晶圓的實施形態，參照所附圖式進 行洋細說明。 圖1所示係本發明實施形態的磊晶晶圓概略圖，圖2所示 係為說明躍遷寬度Tw用的雜質分佈圖。 本發明實施形態的蠢晶晶圓1係如圖1所示，特徵在於： 在矽基板10上設有磊晶層20，上述矽基板10係磷濃度為 1019atoms/cm3 級、氧濃度在 1.3><1018atoms/cm3 以下，蠢晶 層20係構濃度為l〇16atoms/cm3級。 依此當在含有礙濃度為l〇19atoms/cm3級之高濃度雜質的 矽基板10上，設置低3位數雜質濃度之1016atoms/cm3級低 濃度雜質的磊晶層20時’藉由將矽基板10的氧濃度設為 1.3xl018atoms/cm3以下，在半導體裝置形成時的熱處理製程 099145745 5 201135810 中’可大幅抑制矽基板中所含高濃度雜質擴散於磊晶層的情 形。 當上述氧濃度超過1.3><1018atoms/cm3時，因為在半導體 裝置形成時的熱處理製程中，躍遷寬度Tw會大幅變寬，因 而最好避免。 上述氧濃度的下限值較佳係0.5xl018atoms/cm3以上。若 上述氧濃度未滿0.5xl018atoms/cm3時，因為石夕基板10的強 度會降低’因而在磊晶層20形成時，會發生諸如翹曲、錯 位差排荨不良情況’所以最好避免。 上述磊晶層20的膜厚係配合所使用的半導體裝置用途而 適當設計’具體較佳係0.5 em以上且20//m以下。 其次，針對本發明磊晶晶圓之製造方法進行說明。 本發明的磊晶晶圓之製造方法，係包括有：製造磷濃度為 1019atoms/cm3 級、氧濃度為 i.3xi〇18atoms/cm3 以下的矽基 板之步驟；以及在上述矽基板上，形成磷濃度為 1016atoms/cm3級、且膜厚為〇.5〜soym之磊晶層的步驟。 製造上述矽基板的步驟.，具體係依照下述方法實施。首 先’利用柴式長晶法(Czochralski method)，生成填濃度為 10 atoms/cm級、氧濃度為i.3xi〇18at〇ms/cm3以下的石夕早 晶錠(ingot)。 利用柴式長晶法施行的矽單晶錠生成，係依照周知方法實 施。 099145745 6 201135810 具體而言’將多晶矽及既定量的磷填充於石英坩堝中，藉 由加熱石英坩堝，而加熱多晶矽並形成矽融液後，再使從該 矽融液的液面上方接觸晶種結晶，一邊使晶種結晶與石英坩 禍進行旋轉並一邊拉晶，擴徑至所需直徑而生成直筒部。 依此所獲得的矽單晶錠係利用周知方法加工成為矽基板。 具體而言，將矽單晶錠利用内周刀片或線鋸等切片成晶圓 狀之後’經由外周部的倒角、研磨、钱刻、拋光等加工步驟， 便製得至少裝置形成面成為鏡面的石夕基板。另外，此處所記 載的加工步驟僅為例示而已，本發明並不僅侷限於此加工步 驟。 其次，在所製得矽基板的裝置形成面上，形成磷濃度為 lO'toms/cm3級、膜厚為〇 5〜2〇//m的磊晶層。磊晶層的 形成係利用諸如：氣相蟲晶法(CVD法）、有機金屬氣相沉積 法(MOCVD法）或分子束蟲晶法(MBE法）等周知方法便可形 成。 本發明的蟲晶晶圓之製造方法，因為具備上述構成，因而 可製造本發明的蟲晶晶圓。又，因為在發基板H)與羞晶層 20之間’並無必要形成如專散獻2所示的巾間層，因而 亦具有提升生產性的效果。 [實施例] 以下’針對本發明根據實施例進行更具體的說明，惟本發 明並不因下述實施例而限定解釋。 099145745 7 201135810 (實施例及比較例） 準備磷濃度為5xl019atoms/cm3、氧濃度分別為ΐ.Οχίο18、 1.3χ1018、1.8><1018atoms/cm3 之直徑 6 吋（150mm)的矽基板。 接著，該等矽基板上’利用氣相磊晶法(CVD法）分別形成磷 濃度為3xl016atoms/cm3、膜厚為7/zm的磊晶層，便製得3 種蠢晶晶圓。然後，對該等磊晶晶圓在氧1 〇〇〇/〇環境中，依 溫度1050°C施行60分鐘熱處理，然後在同溫度下，從氧 100%環境切換為氮100%環境，更進一步施行270分鐘熱處 理。將該熱處理設為裝置形成熱處理。 然後’針對已施行上述熱處理過的磊晶晶圓，利用二次離 子質譜分析法(SIMS)測定磷濃度的深度方向分佈。又，上述 熱處理前的磊晶晶圓之磷濃度深度方向分佈，亦是利用同一 方法進行測定。 然後’利用所獲得雜質濃度分佈，分別計算出躍遷寬度 Tw。 表1所示係本實施例及比較例的評價結果。According to the present invention, it is possible to provide an epitaxial wafer which can suppress the high-concentration impurities contained in the tantalum substrate and diffuse into the epitaxial layer during the heat treatment process in the formation of the semiconductor device. [Embodiment] The inventors have specifically confirmed that the remote crystal wafer contains a stone-like substrate having impurities as scales and having a concentration of 1 rv 19 atoms/cm3 grade south concentration impurities, and is provided on the stone substrate. When the impurity is phosphorus and the epitaxial layer of the low-concentration impurity of 1016 atoms/cm3 level having a lower impurity concentration than the ruthenium substrate, the transition width greatly increases during the heat treatment process in the formation of the semiconductor device. In order to solve such technical problems, the present invention has been completed through intensive studies. Hereinafter, the embodiment of the amorphous wafer of the present invention will be described in detail with reference to the accompanying drawings. Fig. 1 is a schematic view showing an epitaxial wafer according to an embodiment of the present invention, and Fig. 2 is an impurity distribution diagram for explaining a transition width Tw. As shown in FIG. 1, the amorphous wafer 1 according to the embodiment of the present invention is characterized in that an epitaxial layer 20 is provided on the ruthenium substrate 10, and the ruthenium substrate 10 has a phosphorus concentration of 1019 atoms/cm3 and an oxygen concentration of 1.3 gt. ; <1018atoms/cm3 or less, the stupid layer 20 has a system concentration of l〇16 atoms/cm3. According to this, when the epitaxial layer 20 having a low concentration of impurities of 1016 atoms/cm3 is provided on the tantalum substrate 10 having a high concentration of impurities having a concentration of 10 ato 19 atoms/cm 3 , The oxygen concentration of the substrate 10 is set to 1.3×10 018 atoms/cm 3 or less, and in the heat treatment process at the time of formation of the semiconductor device 099145745 5 201135810, it is possible to greatly suppress the diffusion of high-concentration impurities contained in the ruthenium substrate to the epitaxial layer. When the above oxygen concentration exceeds 1.3 < 1018 atoms/cm3, since the transition width Tw is greatly widened in the heat treatment process at the time of formation of the semiconductor device, it is preferably avoided. The lower limit of the oxygen concentration is preferably 0.5 x 1818 atoms/cm3 or more. If the oxygen concentration is less than 0.5 x 1018 atoms/cm3, the strength of the stone substrate 10 is lowered. Therefore, when the epitaxial layer 20 is formed, such as warpage or misalignment occurs, it is preferable to avoid it. The film thickness of the epitaxial layer 20 is appropriately designed in accordance with the use of the semiconductor device used. Specifically, it is preferably 0.5 em or more and 20 // m or less. Next, a method of manufacturing the epitaxial wafer of the present invention will be described. The method for producing an epitaxial wafer according to the present invention includes the steps of: producing a germanium substrate having a phosphorus concentration of 1019 atoms/cm3 and an oxygen concentration of i.3xi〇18 atoms/cm3 or less; and forming phosphorus on the germanium substrate The step of the epitaxial layer having a concentration of 1016 atoms/cm 3 and a film thickness of 〇.5 to soym. The step of producing the above-mentioned ruthenium substrate is specifically carried out in accordance with the following method. First, the Czochralski method was used to produce an ingot crystal having a concentration of 10 atoms/cm and an oxygen concentration of i.3xi〇18at〇ms/cm3 or less. The formation of a ruthenium single crystal ingot by the Chai-type long crystal method is carried out in accordance with a known method. 099145745 6 201135810 Specifically, 'polycrystalline germanium and a predetermined amount of phosphorus are filled in a quartz crucible, and by heating the quartz crucible to heat the polycrystalline crucible and form a molten solution, the crystal is contacted from above the liquid surface of the molten liquid. Crystallization, while crystallizing the crystal and quartz, and pulling the crystal while expanding, the diameter is increased to a desired diameter to form a straight portion. The tantalum single crystal ingot obtained in this manner is processed into a tantalum substrate by a known method. Specifically, after the tantalum single crystal ingot is sliced into a wafer shape by an inner peripheral blade or a wire saw or the like, the processing surface of the outer peripheral portion is chamfered, polished, burned, polished, etc., so that at least the device forming surface becomes a mirror surface. Shishi substrate. Further, the processing steps recited herein are merely illustrative, and the present invention is not limited to this processing step. Next, an epitaxial layer having a phosphorus concentration of 10 μm/cm3 and a film thickness of 〜 5 to 2 Å/m was formed on the device formation surface of the substrate on which the ruthenium substrate was obtained. The formation of the epitaxial layer can be formed by a known method such as a gas phase crystallization method (CVD method), an organometallic vapor deposition method (MOCVD method) or a molecular beam crystallization method (MBE method). Since the method for producing a silicon wafer of the present invention has the above configuration, the crystal wafer of the present invention can be produced. Further, since it is not necessary to form an inter-sheet layer as shown in Fig. 2 between the substrate H) and the imaginary layer 20, the effect of improving productivity is also obtained. [Examples] Hereinafter, the present invention will be more specifically described based on the examples, but the present invention is not limited by the following examples. 099145745 7 201135810 (Examples and Comparative Examples) A tantalum substrate having a phosphorus concentration of 5xl019 atoms/cm3 and an oxygen concentration of ΐ.Οχίο18, 1.3χ1018, 1.8><1018 atoms/cm3 in diameter of 6 吋 (150 mm) was prepared. Next, on the germanium substrate, an epitaxial layer having a phosphorus concentration of 3x1016 atoms/cm3 and a film thickness of 7/zm was formed by vapor phase epitaxy (CVD) to obtain three kinds of amorphous wafers. Then, the epitaxial wafers are heat treated in an oxygen 1 〇〇〇 / 〇 environment at a temperature of 1050 ° C for 60 minutes, and then switched from an oxygen 100% environment to a nitrogen 100% environment at the same temperature, further Heat treatment was performed for 270 minutes. This heat treatment is used as a device to form a heat treatment. Then, the depth direction distribution of the phosphorus concentration was measured by secondary ion mass spectrometry (SIMS) for the epitaxial wafer subjected to the above heat treatment. Further, the depth distribution of the phosphorus concentration of the epitaxial wafer before the heat treatment is also measured by the same method. Then, using the obtained impurity concentration distribution, the transition width Tw is calculated separately. Table 1 shows the evaluation results of the present examples and comparative examples.
099145745 0 S099145745 0 S
[表1] 碎軍晶基板的氧濃度 ____(atoms/cm3) 裝置形成熱處理前的 躍遷寬度Tw 裝置形成熱處理後的 躍遷寬度Tw 實施例1 Ι.ΟχΙΟ18 0.5 β m 2.6 β m 實施例2 1.3χ1018 ------ 0.5 β m 3.0 β m 比較例1 1.8χ1018 0.6 β m 5.0 β m 由表1得知，當石夕基板的氧濃度在1.3xl〇18atoms/cm3以 下的情況(實施例1、2)，相較於氧濃度為i.gxl〇18atoms/cm3 201135810 的情況（比較例1)，躍遷寬度Tw的擴大被抑制至60%以下。 【圖式簡單說明】 圖1為本發明貫施形悲的蠢晶晶圓概略圖。 圖2為說明躍遷寬度Tw用的雜質分佈圖。 【主要元件符號說明】 1 蠢晶晶圓 10 矽基板 20 蟲晶層 Tw 躍遷寬度 099145745[Table 1] Oxygen concentration of the broken crystal substrate ____ (atoms/cm3) The transition width Tw before the heat treatment of the apparatus was formed. The transition width Tw after the heat treatment of the apparatus was formed. Example 1 Ι.ΟχΙΟ18 0.5 β m 2.6 β m Example 2 1.3 Χ1018 ------ 0.5 β m 3.0 β m Comparative Example 1 1.8χ1018 0.6 β m 5.0 β m It is known from Table 1 that when the oxygen concentration of the Shixi substrate is 1.3×10 ato18 atoms/cm 3 or less (Example) 1, 2), the expansion of the transition width Tw is suppressed to 60% or less as compared with the case where the oxygen concentration is i.gxl 18atoms/cm3 201135810 (Comparative Example 1). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a stray wafer in accordance with the present invention. Fig. 2 is a diagram showing the impurity distribution for the transition width Tw. [Main component symbol description] 1 Stupid wafer 10 矽 substrate 20 Insect layer Tw Transition width 099145745