201131785 六、發明說明： 【發明所屬之技術領域】 本發明是有關於使用在液晶顯示器、半導體、光學零 件等的薄膜電晶體基板以及顯示裝置，特別是，有關於可 以將構成源-汲電極等的Cu合金層直接與薄膜電晶體的半 導體層相連接之新穎的薄膜電晶體基板。 【先前技術】 液晶顯示器等的主動矩陣型液晶顯示裝置，是由TFT 基板、對向基板、以及液晶層所構成；該TFT基板是將薄 膜電晶體（Thin Film Transistor，以下稱作TFT)作爲切 換元件’具備透明畫素電極、柵極配線與源-汲極配線等 的配線部、以及非晶矽（a-Si )與多晶矽（p-Si )等的半 導體層；該對向基板是相對於TFT基板以規定間隔對向配 置，具備共用電極；該液晶層是被塡充在TFT基板和對向 基板之間。 在TFT基板中’栅極配線或是源—汲極配線等的配線 材料至今還是使用鋁（A1)合金膜。但是隨著顯示裝置持 續大型化和高畫質化’配線電阻大導致信號延遲和電力損 失的問題日益明顯。因此，作爲配線材料，比A丨電阻低的 銅（Cu)受到了矚目。 配線材料使用純Cu或Cu合金（以下統稱爲Cu系合金 )時，一般如專利文獻1〜7所述，在Cu系合金配線膜和 TFT的半導體層之間，設置了由Mo、Cr、Ti、w等的高溶 201131785 點金屬構成的阻障金屬層。對此可以主要例舉如下的兩個 理由。 第一’不用介隔著阻障金屬層使Cu系合金配線膜和 TFT的半導體層直接接觸的話，因爲其後的工程（例如， 形成在TFT之上的絕緣膜的成膜工程或燒結或退火等的熱 工程）中的熱過程，導致Cu系合金配線膜中的Cu在半導體 層中擴散、TFT特性下降、或Cu系合金配線膜和半導體層 的接觸電阻增加。 第二，如上所述’在Cu系合金配線膜中的cu在半導體 中擴散形成半導體層和Cu的反應層的話，存在以系合金配 線膜從該反應層的部分剝離的問題。亦即Cu合金膜和半導 體層直接接觸時黏著性下降。 但是’爲了形成這種阻障金屬層，在C u系合金配線膜 形成用的成膜裝置之外’還另外需要阻障金屬形成用的成 膜裝置。具體地說’必須使用額外裝配有阻障金屬層形成 用的成膜腔的成膜裝置（代表性的是多個成膜腔與轉移腔 連接的叢聚式設備（cluster tool))，導致製造成本的上 升和生產性的降低。 在這種背景下，作爲將上述的阻障金屬層省略的技術 ’例如可以例舉本案申請人提出的專利文獻8。在專利文 獻8中’公開了作爲Cu系合金配線膜和半導體層直接接觸 的技術’源-汲電極由含氧層和純Cu或Cu合金薄膜構成， 構成含氧層的氧與半導體層的Si結合，前述純Cu或Cu合金 的薄膜介隔著則述含氧層與半導體層連接的TFT基板。 201131785 專利文獻1 ··(日本）特開平7 — 66423號公報 專利文獻2 :(日本）特開平8 - 8498號公報 專利文獻3:(日本）特開2001— 196371號公報 專利文獻4:(日本）特開2002— 353222號公報 專利文獻5 :(日本）特開2004 — 1 3 3422號公報 專利文獻6 :(日本）特開2004-212940號公報 專利文獻7 :(日本）特開2005 — 1 66757號公報 專利文獻8:(日本）特開2009 - 4518號公報 【發明內容】 〔發明欲解決之課題〕 本發明是著眼於如上所述的情況而開發的，其目的在 於提供一種即使省略通常設置在Cu系合金配線膜和半導體 層之間的阻障金屬層也能發揮優異的低接觸電阻率，並且 ，Cu系合金配線膜和半導體層的黏著性優異的薄膜電晶體 基板。 〔解決課題之手段〕 可以解決上述課題的本發明的薄膜電晶體基板，具有 薄膜電晶體的半導體層和Cu合金層，其要旨在於：在前述 半導體層和前述Cu合金層之間，包含有含氧層；構成前述 含氧層的氧的一部分或全部，是與前述薄膜電晶體的前述 半導體層的Si結合；前述Cu合金層，乃是作爲合金元素含 有合計爲2原子％以上20原子％以下的X ( X是從Mn、Ni、 201131785 zn和Mg中選出至少—種者）：前述Cu合金層，是介隔著 前述含氧層’與前述薄膜電晶體的前述半導體層相連接。 關於本發明’在薄膜電晶體中，具有薄膜電晶體的半 導體層和Cu合金層，其中，在前述半導體層和前述cu合金 層之間’包含有含氧層；構成前述含氧層的氧的一部分或 全部’是與前述薄膜電晶體的前述半導體層的Si結合；前 述Cu合金層是從前述薄膜電晶體的前述半導體層側開始依 順包含有：作爲合金元素含有Χ(Χ是從Mn、Ni、Zn和Mg 中選出的至少一種者）的Cu合金基層（第一層）、和由純 Cu或以Cu爲主成分的Cu合金即比前述第一層電阻率低的 Cu合金構成的層（第二層）的層積結構；前述Cu合金層， 是介隔著前述含氧層，與前述薄膜電晶體的前述半導體層 連接。 在本發明中，前述Cu合金基層（第一層）中的X含量 合計爲2原子％以上20原子％以下者爲佳；另外，Cu合金基 層（第一層）的厚度爲l〇nm以上100nm以下者爲佳。 在本發明中，構成前述含氧層的氧的原子數〔0〕和 Si的原子數〔Si〕的比（〔0〕/〔Si〕）爲0.5以上2.0以 下者爲佳；另外，前述含氧層的膜厚爲1.3nm以上3.3nm以 下者爲佳。更進一步，前述薄膜電晶體的前述半導體層是 氫化非晶矽、非晶矽和多晶矽中的任一種、或組合兩種以 上者爲佳。 於本發明，也包含具備上述任一種的薄膜電晶體基板 的顯示裝置。 -8- 201131785 〔發明效果〕 在本發明中，Cu合金層是介隔著含氧層與薄膜電晶體 的半導體層相連接，因此，能夠抑制Cu原子向半導體層的 擴散，能夠實現和半導體層的高黏著性和低接觸電阻率。 另外，藉由讓Cu合金層形成含有規定量的合金成分χ(χ 是從Μη、Ni、Ζη和Mg中選出的至少一種者）的Cu-X合金 層的單層或和純Cu等的層積的方式，從而能夠實現高度的 和半導體層的高黏著性和低接觸電阻率。 【實施方式】 本發明者們在提出上述專利文獻8的技術後，爲了提 供具備能夠與TFT的半導體層直接連接的。系合金配線材 料的新型薄膜電晶體基板，進行了硏究。作爲其結果，有 如下發現’從而完成了本發明：像專利文獻8那樣，含氧 層半導體層和Cu系合金配線材料電性連接的配線構造中， 使Cu系合金配線材料形成（I)作爲合金元素含有規定量 的X(X是從Mn、Ni、Zn和Mg中選出的至少一種者）的 Cu-X合金的單層構造 '或（π)形成Cu_x合金和純以等的 層積構造’則與專利文獻8相比，能夠進一步改善和半導 體層的黏著性和接觸電阻率，特別是如果形成層積構造， 則Cu系合金配線材料自身的電阻率也會抑制到很低。亦即 ’本發明在專利文獻8的利用含氧層的介隔存在提高和半 導體層的黏著性和降低接觸電阻率的思想的基礎上，將Cu -9 - 201131785 系合金配線材料的構成限定爲含有有助於提高黏著性等的 合金元素的Cu-X合金，並考慮到CU系合金配線材料自身的 電阻率’形成Cu-X合金的單層構造，或Cu-X合金和純（^ 等的層積構造，在這一點上與專利文獻8不同。 以下，舉例說明作爲本發明的Cu合金層的適用例的源 一汲電極，但本發明並不限定於此。 (源一汲電極） 本發明的適用例的源—汲電極28、29，如圖1所示， 由含氧層28a、29a和Cu合金層28b' 29b所構成。含氧層 28a、29a以覆蓋TFT的半導體層33的方式形成，例如含氧 層28a、29a的氧原子（0)的一部分或全部以與半導體層 33的Si結合的狀態存在。構成含氧層28a、29a的〇，與構 成半導體層33的Si相比，跟Cu的黏著性較爲優異，在形成 圖案後不會發生電極剝離。另外，含氧層28a、29a還作爲 用於防止Cu合金層28b、2 9b和TFT的半導體層33的介面中 Cu和Si的相互擴散的阻礙（擴散防止阻礙）而起作用。 根據本發明，如後述的實施例所證實，即使不如現有 技術那樣形成Mo等的阻障金屬層，也能夠實現低接觸電阻 率。另外，含氧層如後述詳細說明，在形成半導體層之後 ，在形成Cu合金層之前，例如能夠透過電漿法等簡便地製 作，因此，不需要如現有技術那樣的阻障金屬層形成用的 特別的成膜裝置。 首先，對本發明所用的含氧層進行說明。含氧層的詳 -10- 201131785 細及其形成方法如上述專利文獻8的記載，在此如下再次 提出。 含氧層的氧原子（0)的一部分或全部與半導體層的 Si結合，主要形成Si氧化物（SiOx ) 。Si氧化物例如透過 使Si半導體層的表面氧化而得到。 上述含氧層（Si氧化物）抑制Cu合金層中的Cu在半導 體層中擴散，並且，和Cu合金層的黏著性優異，其結果是 ，如果使用含有含氧層的Cu合金層，與不具有含氧層的情 況相比，能夠提高和非晶矽層的黏著性。本發明的含氧層 爲滿足以下的必要條件者爲佳。 構成含氧層的氧的原子數〔〇〕和Si的原子數〔Si〕 的比（〔〇〕/〔 Si〕，以下稱爲P値）爲0.5以上2.0以下的 範圍者爲佳。由此，不會提高接觸電阻率，能夠有效地發 揮含氧層的阻礙作用。P値爲0.7以上1.8以下者爲更佳。 P値的較佳下限（0.5 )是出於能夠抑制非晶矽層的表 面氧化導致的擴散的〔〇/Si〕而設定的。另外，P値的優 選上限（2.0)是考慮到Si02B成時的〔〇/Si〕的最大値大 致爲2.0而設定的。 P値在含氧層的形成工程（後述）中，例如可以透過 將電漿照射時間控制在大致1秒到60分鐘的範圍內而進行 調節。另外，P値可以透過XPS法（X-Ray Spectroscopy’ X射線電子分光法）分析含氧層深度方向的元素（〇和“） 而算出。 含氧層的厚度爲1.3nm以上3.3ητη以下的範圍內者爲佳 -11 - 201131785 «含氧層的厚度低於Unm時，不能抑制Cu合金層中的Cu 原子在半導體層中擴散。而含氧層的厚度超過3·3ηπι時， Cu合金層和半導體層之間的接觸電阻率變得過高’發生電 力損失，因此，顯示裝置的顯示畫質下降。含氧層的厚度 爲1.5nm以上3.0nm以下者爲佳。 含氧層的厚度可以透過各種物理分析方法求得。例如 在上述的XPS法之外，還能夠利用RBS法（雷達瞄準後方 散亂分光法）、SIMS (二次離子品質分析）法、GD-OES (高頻輝光放電光分析）法、分光儀器等。 含氧層例如可以透過對半導體層上部進行氧化處理來 形成。但不特別限定於這些處理方法，例如，可以採用（ i)使用電漿的方法，（ii)透過加熱進行的方法等。 上述（i)使用電漿時，例如可以使用氧氣形成含氧 層。用於電漿處理的氧氣可以利用Ar等的惰性氣體稀釋。 從含氧的電漿源供給氧時，也能夠利用使用氧離子的離子 注入法。 另外’上述（ii )進行加熱時，可以在氧氣氣氛中加 熱Si半導體層’由此，能夠得到含氧層。用於加熱處理的 氧氣可以利用Ar等的惰性氣體稀釋。 在上述方法之外，也可以利用例如在源一汲電極的形 成過程中’存在於Si半導體層的表面的氧原子在Cu系薄膜 等中擴散’形成含氧層的這種自然擴散法。 以下’詳細說明上述（i )〜（ii )。 -12- 201131785 (i )電漿氧化法 電漿氧化法利用電漿，具體地說，例如在氧氣氣氛中 施加局頻電發’由此產生的氧自由基和臭氧和試料反應， 從而進行氧化。作爲含氧氣體可以例舉〇2、h2o、n2o等 氣體。它們可以單獨或作爲兩種以上的混合氣體使用。具 體地說，在含氧的電漿源附近設置TFT的半導體層者爲佳 。在此’電漿源和半導體層的距離可以根據電漿的種類和 電漿發生條件（功率（投入電力）、壓力、溫度、照射時 間、氣體組成等）等設定在適當的範圍內，大槪數十0〇1的 範圍者爲佳。在這種等離子附近，存在高能量的氧原子， 由此，能夠在半導體層表面容易地形成期望的含氧層。 在從含氧等離子源等供給氧時，能夠利用離子注入法 。根據離子注入法，由電場加速的離子能夠移動長距離， 因此，能夠任意設定電漿源和半導體層的距離。離子注入 法透過對設置在電漿附近的半導體層施加負的高電壓脈衝 ，向半導體層的表面整體注入離子者爲佳。或者，使用專 用的離子注入裝置進行離子注入。 另外，處理溫度爲300 °C以上者爲佳。處理溫度低於 3 00 °C時，氧化反應的進行緩慢，對於作爲擴散阻礙有效 作用的含氧層的形成需要長時間，難以得到更良好的TFT 特性。但是，溫度過高時，容易導致作爲處理物件的半導 體層的變質和半導體層的損傷，因此，大致爲360 °C以下 者爲佳。 另外，關於壓力在55Pa以上的壓力下進行者爲佳。壓 -13- 201131785 力低於55P a時，氧化反應的進行緩慢，對於 有效作用的含氧層的形成需要長時間。如果 化反應的進行在短時間內進行，能夠減少對 傷，能夠形成顯示良好阻礙性的含氧層，能 電阻率。從上述觀點出發，壓力越高越好， 者爲佳，爲66P a以上者爲更佳。還有，壓力 存於所使用的裝置的性能等，因此，難以唯 從穩定電漿供給的觀點出發，大致400P a以 266Pa以下者爲更佳。 電漿照射時間爲60分鐘以下者爲佳。電 過60分鐘時，不能無視形成於非晶矽層的表 致的電壓下降，TFT特性下降。電漿照射時 下者爲較佳，爲10分鐘以下者爲更佳。關於 的下限，如果在非晶矽層的表面形成一層程 則從充分發揮本發明的效果的觀點出發，可 矽層的表面形成一層程度（SiOx的1原子層 層的時間以上。電漿照射時間1秒以上者爲ί 爲較佳。 另外，投入電力爲50W以上者爲佳。 5 0W時，氧化反應的進行緩慢，難以形成適 s i〕比的含氧層，對於作爲擴散阻礙有效作 形成需要長時間等，TFT特性下降。從上述 入電力越高越好，例如爲60W以上爲較佳， 爲更佳。 作爲擴散阻礙 提高壓力，氧 半導體層的損 夠實現低接觸 例如60Pa以上 的上限由於依 一地決定，但 下者爲佳，爲 漿照射時間超 面的含氧層導 間爲3 0分鐘以 電漿照射時間 度的含氧層， 以至少在非晶 程度）的含氧 I，爲5秒以上 投入電力低於 當的〔〇〕/〔 用的含氧層的 觀點出發，投 爲75W以上者 -14- 201131785 氣體組成可以是上述的含氧氣體（〇2、H2〇 ' N2〇等 )，也可以用Ar等惰性氣體稀釋含氧氣體。 (i i )熱氧化法 熱氧化法由於氧化皮膜的附著優異等的理由而被廣& 使用。具體地說，例如在氧氣氣氛下，在400 °C以下的溫 度加熱者爲佳。加熱溫度高時，對半導體層的損傷變大’ 而加熱溫度低時，不能充分形成希望的含氧層。加熱溫度 控制在2 0 0 °c以上3 8 0 t：以下者較佳，控制在2 5 0 °C以上3 5 0 °C以下者爲更佳。上述的加熱處理可以和上述的電漿氧化 法並用，由此，能夠進一步促進含氧層的形成。 如此，含氧層透過上述的（i)〜（ii)的方法形成者 爲佳，但從進一步簡化製造工程和縮短處理時間的觀點出 發，如下控制含氧層的形成中使用的裝置和腔、溫度和氣 體組成而進行者爲較佳。 首先，爲了簡化製造工程，裝置用與半導體層形成裝 置相同的裝置進行者爲佳。由此，在裝置間或裝置內，處 理物件的工件無需額外地移動。 另外’關於溫度在和半導體層的成膜溫度實質上相同 的溫度進行者爲佳。由此，能夠省略溫度變動所必要的調 節時間。 或者，氣體組成也可以用Ar等惰性氣體稀釋前述含氧 氣體進行使用。 如此在TFT的半導體層上形成含氧層後，例如透過灘 -15- 201131785 射法形成Cu合金層時，能夠得到希望的源一汲電極❶ 本發明的薄膜電晶體基板，在TFT半導體層和Cu合金 層之間以覆蓋TFT的半導體層的方式設置上述含氧層，因 此’例如半導體層的種類不特別限定，在不對TFT特性產 生不良影響的情況下’可以使用通常用於源-汲電極的種 類。爲氫化非晶矽、非晶矽、多晶矽中的任一種或兩種以 上的組合者爲佳。 接著，對本發明的Cu合金層進行說明。 本發明中的Cu合金層（a)可以是作爲合金元素含有 合計爲2原子％以上20原子％以下的X ( X是從Mn、Ni、Zn 和Mg中選出的至少一種）的單層構造，（b)也可以是從 薄膜電晶體的半導體層側順序包括作爲合金元素含有從X (X是從Mn、Ni、Zn和Mg中選出的至少一種）的Cu合金 基層（第一層）和由純Cu或以Cu爲主成分的Cu合金亦即 比所述第一層電阻率低的Cu合金構成的層（第二層）的層 積結構。Cu合金層爲前述層積結構時，Cu合金基層（第一 層）中的X含量合計爲2原子％以上20原子％以下者爲佳。 關於單層結構 單層結構的Cu合金層是作爲合金元素含有X ( X是從 Mn、Ni、Zn和Mg中選出的至少一種者）的Cu-X合金層。 透過形成這種Cu-X合金層，即使不設置阻障金屬層也能夠 提高和半導體層的黏著性，並且，能夠實現和半導體層的 低接觸電阻率。這些X元素作爲雖然固溶於Cu金屬但是不 -16- 201131785 固溶於Cu氧化膜的元素而選出。固溶有這些元素的CU合金 透過成膜過程的熱處理而被氧化時，上述元素擴散後在晶 界或介面濃稠化，由於該濃稠化層而提高和半導體層的黏 著性。另外，這些元素對於使用Cu時的有用性（Cu自身的 低電阻和低接觸電阻率）不會有任何損害，能夠發揮上述 黏著性。 上述X元素中爲佳者是Mn、Ni，較佳者爲Μη。特別是 Μη黏著性優異。Μη是在上述的介面的濃稠化現象非常強 烈出現的元素，透過Cu合金成膜時或成膜後的熱處理（包 括例如形成SiN膜的絕緣膜的工程這類的顯示裝置的製造 過程中的熱過程）從膜內側向外側移動。Μη向介面的移動 ，由於熱處理發生氧化而生成的Μη氧化物成爲驅動力，被 進一步促進。其結果是，提高和半導體層的黏著性。 單層結構的Cu合金層中的X含量爲2原子％以上20原子 %以下。作爲X元素在單獨使用上述元素時，單獨的量滿 足上述範圍即可，在含有2種以上時，合計量滿足上述範 圍即可。X含量低於2原子％時不能充分實現和半導體層的 高的黏著性和低接觸電阻率。而X含量超過20原子％時， Cu合金層全體的電阻變高，其結果是，和半導體層接觸電 阻率變高。X含量其範圍爲4〜18原子％者爲佳，較佳的範 圍是6〜1 5原子％。 單層結構中的Cu合金層的膜厚爲100〜500nm者爲佳 。膜厚低於lOOnm時，Cu配線的電阻變高，而超過500nm 時，不能確保和半導體層的黏著性，容易發生膜剝離。單 -17- 201131785 層結構中的Cu合金層的膜厚爲200〜400nm者爲佳。 關於層積結構 層積結構中的Cu合金基層（第一層）的合金元素與上 述單層結構相同，是作爲合金元素含有X(X是從Mn、Ni 、Zn和Mg中選出的至少一種）的Cu-X合金層。上述χ元素 中爲佳的是Mn、Ni’更佳爲Mn。Cu合金基層（第一層） 中的X含量優選與單層結構時相同，即爲佳的是2原子％以 上20原子％以下。前述範圍的爲佳理由與單層結構相同。 層積結構中的Cu-X合金層（第一層）的膜厚爲10nm 以上100nm以下者佳。膜厚低於10nm時，不能確保和半導 體層的黏著性。而膜厚超過100nm時，Cu合金全體（第一 層+第二層）的電阻變高，來自配線的發熱問題變得深刻 。Cu-X合金層（第一層）的膜厚爲15〜6 Onm者佳。 層積結構中的第二層在第一層之上形成，由純Cu或以 Cu爲主成分的Cu合金即比前述第一層電阻率低的Cu合金 構成。透過設置這種第二層，能夠將Cu合金層全體的電阻 率抑制得很低。在此，所謂比第一層電阻率低的Cu合金是 與由含有X元素的Cu-X合金構成的第一層相比適當地控制 合金元素的種類和/或含量來降低電阻率。電阻率低的元 素（大致與純銅合金相比低的元素）可以參照文獻中記載 的數値等，從公知的元素中容易地選出。但是，即使是電 阻率高的元素如果降低含量（大致0.05〜1原子％左右）也 能夠降低電阻率，因此，第二層可以適用的合金元素並非 • 18 - 201131785 必須限定於電阻率低的元素。具體地說，例如可以使用 〇11-0.5原子 ％Ni、Cu-0.5原子 ％Zn、（^-0.3原子 ％Mn等者爲 佳。另外，作爲可以適用於第二層的合金即使含有氧氣或 氮氣等氣體成分也可，例如可以使用Cu-0或Cu-N等。 層積結構中的Cu合金層全體的厚度（第一層+第二層 )可以根據所要求的TFT特性等適當設定，但大致爲 200nm以上500nm以下者爲佳，爲200〜400nm者較佳。 本發明所用的Cu合金層，單層結構和層積結構的任一 種情況，除上述元素之外的餘量是Cu和不可避免的雜質。 本發明的〇合金層透過濺射法形成者爲佳。特別是形 成層積結構時，在通過濺射法對上述構成第一層的材料進 行成膜後，透過濺射法在其上對上述構成第二層的材料進 行成膜，由此，形成層積結構即可。如此形成Cu合金層積 膜後，進行規定的圖案形成後，從覆蓋截面形狀的觀點出 發，加工成錐形角度45〜60°左右的錐形狀者爲佳。 如果使用濺射法，能夠形成與濺射靶大致相同組成的 Cu合金層。因此，透過調整濺射靶的組成，能夠調整Cu合 金層的組成。濺射靶的組成使用Cu合金靶進行調整即可， 或者在純Cu靶中調節合金元素的金屬進行調整也可。 還有濺射法中，在成膜的Cu合金層的組成和濺射靶的 組成之間會有微小的偏差。但是，該偏差大槪在數原子％ 以內。因此，如果將濺射靶的組成控制在最大± 1 0原子％的 範圍內，就能夠形成希望組成的Cu合金層。 本發明所用的基板沒有特別限定，但例如可以例舉出 -19- 201131785 無鹼玻璃、高應變點玻璃（high strain point glass)、驗 石灰玻璃等。 〔實施例〕 以下，舉實施例更具體地說明本發明，但本發明並不 限定於以下的實施例，本發明可以在上述下述的宗旨的範 圍內進行變更實施，這均包含於本發明的技術範圍內。 實施例1 在本實施例中對Cu合金層（層積結構）和半導體層的 接觸電阻率和黏著性進行討論。 (1 )和半導體層的接觸電阻率的測定 爲了調査Cu合金層和半導體層的接觸電阻率，製作 TLM( Transfer Length Method)元件，根據圖 2、3所示的 TLM法測定接觸電阻率。首先，對TLM元件的製作方法進 行說明。 首先，在玻璃基板上透過電漿CVD法以大約200nm的 厚度形成膜厚約200nm的摻雜雜質（P)的低電阻的非晶矽 膜。接著，在相同的電漿CVD裝置內僅供給氧氣使電漿產 生，透過氧電漿對低電阻非晶矽膜的表面進行30秒處理， 形成含氧層。作爲氧電漿裝置，使用大和（YAM ΑΤΟ )科 學社製的測量裝置（型號：PR41 )，投入電力450W，成 膜溫度爲室溫，氣體壓力爲67Pa。 -20- 201131785 接著’利用濺射法形成Cu合金膜（單層結構。層積結 構）°更詳細地說，單層結構的成膜是形成300nm的由表1 所示組成的純Cvi或cu合金的膜，層積結構的成膜是以表2 〜4所示的條件蒸鍍基層，在其上形成純以膜（Cu合金層 全體的膜厚：大約3 00nm )。濺射溫度爲室溫。利用光蝕 刻對保護層形成圖案後，以保護層爲遮罩，對CuM合金膜 進行蝕刻’由此，形成多個電極。在此，對各電極間的距 離進行各種變化。最後，爲了類比實際的薄膜電晶體的製 造工程’在270°C進行30分鐘的熱處理。 接著’參照圖2和圖3，對利用TLM法進行的接觸電阻 的測定原理進行說明。圖2 ( a )是模式化地顯示根據上述 要領製作的TLM元件的配線結構的截面圖，圖2(b)是該 TLM元件的俯視圖。 首先，在上述圖2 ( a )的配線結構中，測定多個電極 間的電流電壓特性，求出各電極間的電阻値。以如此得到 的各電極間的電阻値爲縱軸，以電極間距離（轉移長度， L )爲橫軸形成座標，得到圖3的曲線圖。在圖3的曲線圖 中，y切片的値相當於接觸電阻R c的2倍的値（2 R c ) ，X切 片的額値相當於實效的接觸長度（LT: transger length ) 。從以上，接觸電阻率pc由下式表示。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a display device used in a liquid crystal display, a semiconductor, an optical component, and the like, and more particularly, can constitute a source-germanium electrode or the like. The Cu alloy layer is directly connected to the novel thin film transistor substrate of the semiconductor layer of the thin film transistor. [Prior Art] An active matrix liquid crystal display device such as a liquid crystal display is composed of a TFT substrate, a counter substrate, and a liquid crystal layer; the TFT substrate is switched by a thin film transistor (hereinafter referred to as TFT). The device ' includes a transparent pixel electrode, a wiring portion such as a gate wiring and a source-drain wiring, and a semiconductor layer such as amorphous germanium (a-Si) and polysilicon (p-Si); the opposite substrate is opposite to the semiconductor layer; The TFT substrate is disposed to face each other at a predetermined interval, and includes a common electrode; the liquid crystal layer is interposed between the TFT substrate and the counter substrate. In the TFT substrate, a wiring material such as a gate wiring or a source-drain wiring is still an aluminum (A1) alloy film. However, as the display device continues to be large and high in quality, the problem of signal delay and power loss is becoming more and more obvious. Therefore, as a wiring material, copper (Cu) having a lower electric resistance than A is attracting attention. When a pure Cu or a Cu alloy (hereinafter collectively referred to as a Cu-based alloy) is used as the wiring material, as described in Patent Documents 1 to 7, generally, Mo, Cr, and Ti are provided between the Cu-based alloy wiring film and the semiconductor layer of the TFT. , w, etc. Highly soluble 201131785 point metal barrier metal layer. This can be exemplified by the following two reasons. The first 'does not directly contact the barrier metal layer to directly contact the Cu-based alloy wiring film and the semiconductor layer of the TFT, because of subsequent engineering (for example, film formation engineering or sintering or annealing of the insulating film formed on the TFT) In the thermal process in the thermal engineering, the Cu in the Cu-based alloy wiring film is diffused in the semiconductor layer, the TFT characteristics are lowered, or the contact resistance between the Cu-based alloy wiring film and the semiconductor layer is increased. When the cu in the Cu-based alloy wiring film is diffused in the semiconductor to form a reaction layer of the semiconductor layer and Cu as described above, there is a problem that the alloy wiring film is peeled off from the portion of the reaction layer. That is, when the Cu alloy film and the semiconductor layer are in direct contact, the adhesion is lowered. However, in order to form such a barrier metal layer, a film forming apparatus for forming a barrier metal is additionally required in addition to the film forming apparatus for forming a Cu-based alloy wiring film. Specifically, it is necessary to use a film forming apparatus (typically a cluster tool in which a plurality of film forming chambers are connected to the transfer chamber) to be additionally equipped with a film forming chamber for forming a barrier metal layer, resulting in manufacturing. The increase in cost and the decrease in productivity. In this case, as a technique for omitting the barrier metal layer described above, for example, Patent Document 8 proposed by the applicant of the present application can be exemplified. Patent Document 8 discloses a technique in which a Cu-based alloy wiring film and a semiconductor layer are in direct contact with each other. The source-germanium electrode is composed of an oxygen-containing layer and a pure Cu or Cu alloy thin film, and constitutes oxygen of the oxygen-containing layer and Si of the semiconductor layer. In combination, the thin film of the pure Cu or Cu alloy interposes the TFT substrate in which the oxygen-containing layer and the semiconductor layer are connected. Japanese Patent Laid-Open No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. Japanese Laid-Open Patent Publication No. 2004- 353222 (Patent Document 5): Japanese Patent Laid-Open No. 2004- 1 3 3 422 Patent Document 6: (Japanese) Laid-Open Patent Publication No. 2004-212940 Patent Document 7: (Japan) Special Opening 2005-1 [Problem to be Solved by the Invention] The present invention has been developed in view of the above circumstances, and it is an object of the present invention to provide an The barrier metal layer provided between the Cu-based alloy wiring film and the semiconductor layer can exhibit an excellent low contact resistivity and a thin film transistor substrate excellent in adhesion between the Cu-based alloy wiring film and the semiconductor layer. [Means for Solving the Problem] The thin film transistor substrate of the present invention which solves the above-described problems includes a semiconductor layer of a thin film transistor and a Cu alloy layer, and is intended to include a semiconductor layer and the Cu alloy layer. The oxygen layer; a part or all of the oxygen constituting the oxygen-containing layer is bonded to Si of the semiconductor layer of the thin film transistor; and the Cu alloy layer is contained in an alloy element in a total amount of 2 atom% or more and 20 atom% or less. X (X is at least one selected from the group consisting of Mn, Ni, 201131785 zn and Mg): the Cu alloy layer is connected to the semiconductor layer of the thin film transistor via the oxygen-containing layer. In the present invention, in the thin film transistor, a semiconductor layer having a thin film transistor and a Cu alloy layer, wherein an oxygen-containing layer is contained between the semiconductor layer and the cu alloy layer; oxygen constituting the oxygen-containing layer a part or all of 'is bonded to Si of the semiconductor layer of the thin film transistor; the Cu alloy layer is contained from the side of the semiconductor layer of the thin film transistor, and contains Χ as an alloy element (Χ is from Mn, a Cu alloy base layer (first layer) selected from at least one of Ni, Zn, and Mg, and a Cu alloy containing pure Cu or Cu as a main component, that is, a layer composed of a Cu alloy having a lower resistivity than the first layer. a laminated structure of (second layer); wherein the Cu alloy layer is connected to the semiconductor layer of the thin film transistor via the oxygen-containing layer. In the present invention, it is preferable that the total content of X in the Cu alloy base layer (first layer) is 2 atom% or more and 20 atom% or less; and the thickness of the Cu alloy base layer (first layer) is l〇nm or more and 100 nm. The following are preferred. In the present invention, the ratio ([0]/[Si]) of the atomic number [0] of oxygen and the atomic number [Si] of the oxygen-containing layer is preferably 0.5 or more and 2.0 or less; The film thickness of the oxygen layer is preferably 1.3 nm or more and 3.3 nm or less. Furthermore, the aforementioned semiconductor layer of the above-mentioned thin film transistor is any one of hydrogenated amorphous germanium, amorphous germanium and polycrystalline germanium, or a combination of two or more. The present invention also includes a display device including the thin film transistor substrate of any of the above. -8-201131785 [Effect of the Invention] In the present invention, since the Cu alloy layer is connected to the semiconductor layer of the thin film transistor via the oxygen-containing layer, diffusion of Cu atoms into the semiconductor layer can be suppressed, and the semiconductor layer can be realized. High adhesion and low contact resistivity. In addition, a single layer of a Cu-X alloy layer containing a predetermined amount of an alloy component χ (χ is selected from at least one of Μη, Ni, Ζη, and Mg) or a layer of pure Cu or the like is formed by forming a Cu alloy layer. The way of producting enables high adhesion to the semiconductor layer and low contact resistivity. [Embodiment] The present inventors have proposed the technique of Patent Document 8 to provide direct connection to a semiconductor layer of a TFT. A new type of thin film transistor substrate, which is an alloy wiring material, has been studied. As a result of the present invention, the present invention has been completed. In the wiring structure in which the oxygen-containing layer semiconductor layer and the Cu-based alloy wiring material are electrically connected as in Patent Document 8, the Cu-based alloy wiring material is formed (I) as The alloy element contains a predetermined amount of X (X is a single layer structure of Cu-X alloy selected from at least one of Mn, Ni, Zn, and Mg) or (π) forms a Cu_x alloy and a purely laminated structure. In comparison with Patent Document 8, the adhesion to the semiconductor layer and the contact resistivity can be further improved. In particular, if a laminated structure is formed, the resistivity of the Cu-based alloy wiring material itself is also suppressed to be low. In other words, in the present invention, the interlayer of the oxygen-containing layer of Patent Document 8 has the effect of improving the adhesion to the semiconductor layer and lowering the contact resistivity, and the configuration of the Cu -9 - 201131785 alloy wiring material is limited to A Cu-X alloy containing an alloying element which contributes to adhesion and the like, and a single layer structure of a Cu-X alloy formed by considering the specific resistance of the CU-based alloy wiring material itself, or a Cu-X alloy and a pure (^, etc.) The laminated structure is different from Patent Document 8. In the following, a source-electrode electrode which is an application example of the Cu alloy layer of the present invention will be described as an example, but the present invention is not limited thereto. The source-germanium electrodes 28, 29 of the application of the present invention are composed of an oxygen-containing layer 28a, 29a and a Cu alloy layer 28b' 29b as shown in Fig. 1. The oxygen-containing layers 28a, 29a cover the semiconductor layer 33 of the TFT. In a manner of forming, for example, a part or all of the oxygen atoms (0) of the oxygen-containing layers 28a and 29a are present in a state of being bonded to Si of the semiconductor layer 33. The germanium constituting the oxygen-containing layers 28a and 29a and the Si constituting the semiconductor layer 33 are formed. Compared with Cu, it has excellent adhesion and is in shape. The electrode is not peeled off after the pattern. The oxygen-containing layers 28a and 29a also serve as a barrier against diffusion between Cu and Si in the interface of the semiconductor layer 33 of the Cu alloy layers 28b and 29b and the TFT (diffusion prevention). According to the present invention, as described later, it is confirmed that a low contact resistivity can be achieved even if a barrier metal layer such as Mo is not formed as in the prior art. Further, the oxygen-containing layer is formed as described later in detail. After the semiconductor layer is formed, for example, by a plasma method or the like before the formation of the Cu alloy layer, a special film forming apparatus for forming a barrier metal layer as in the prior art is not required. First, the film forming apparatus used in the present invention is used. The oxygen-containing layer will be described in detail. The detailed description of the oxygen-containing layer is described in the above-mentioned Patent Document 8, and is again proposed as follows. A part or all of the oxygen atom (0) of the oxygen-containing layer and the semiconductor layer The Si bond mainly forms Si oxide (SiOx). The Si oxide is obtained, for example, by oxidizing the surface of the Si semiconductor layer. The above oxygen-containing layer (Si oxide) suppresses Cu in the Cu alloy layer diffuses in the semiconductor layer and is excellent in adhesion to the Cu alloy layer. As a result, if a Cu alloy layer containing an oxygen-containing layer is used, compared with the case where the oxygen-containing layer is not provided, The adhesion to the amorphous ruthenium layer is improved. The oxygen-containing layer of the present invention is preferably a member satisfying the following requirements: The ratio of the atomic number of oxygen constituting the oxygen-containing layer to the atomic number of Si [Si] ([ 〇]/[Si], hereinafter referred to as P値) is preferably in the range of 0.5 or more and 2.0 or less. Therefore, the contact resistivity is not increased, and the barrier effect of the oxygen-containing layer can be effectively exhibited. P値 is 0.7 or more. 1.8 or less is better. The preferred lower limit (0.5) of P is set for [〇/Si] which is capable of suppressing diffusion due to surface oxidation of the amorphous germanium layer. Further, the upper limit (2.0) of P値 is set in consideration of the maximum 〇(Si/Si) of SiO 2B being 2.0. In the formation of an oxygen-containing layer (described later), P値 can be adjusted by, for example, controlling the plasma irradiation time to a range of approximately 1 second to 60 minutes. Further, P値 can be calculated by analyzing the elements (〇 and “) in the depth direction of the oxygen-containing layer by the XPS method (X-Ray Spectroscopy 'X-ray electron spectroscopy method. The thickness of the oxygen-containing layer is 1.3 nm or more and 3.3 ητη or less. The inner one is better - 201131785 «The thickness of the oxygen-containing layer is lower than Unm, and the Cu atoms in the Cu alloy layer cannot be inhibited from diffusing in the semiconductor layer. When the thickness of the oxygen-containing layer exceeds 3·3ηπι, the Cu alloy layer and Since the contact resistivity between the semiconductor layers is too high, power loss occurs, and the display quality of the display device is lowered. The thickness of the oxygen-containing layer is preferably 1.5 nm or more and 3.0 nm or less. The thickness of the oxygen-containing layer can be transmitted. Various physical analysis methods can be obtained. For example, in addition to the above-described XPS method, RBS method (radar aiming rear scattered spectrometry), SIMS (secondary ion quality analysis) method, GD-OES (high-frequency glow discharge light) can be used. The analysis method, the spectroscopic apparatus, etc. The oxygen-containing layer can be formed, for example, by oxidizing the upper portion of the semiconductor layer. However, it is not particularly limited to these treatment methods, and for example, (i) a method using plasma can be employed. Ii) A method of performing heat treatment, etc. When (i) plasma is used, for example, oxygen can be used to form an oxygen-containing layer. Oxygen used for plasma treatment can be diluted with an inert gas such as Ar. From an oxygen-containing plasma source When oxygen is supplied, an ion implantation method using oxygen ions can also be used. Further, when the above (ii) is heated, the Si semiconductor layer can be heated in an oxygen atmosphere, whereby an oxygen-containing layer can be obtained. It may be diluted with an inert gas such as Ar. In addition to the above method, for example, oxygen atoms present on the surface of the Si semiconductor layer may be diffused in a Cu-based film or the like during formation of a source-electrode electrode to form an oxygen-containing gas. This natural diffusion method of the layer. The above (i) to (ii) are described in detail. -12- 201131785 (i) Plasma Oxidation Plasma oxidation method utilizes plasma, specifically, for example, in an oxygen atmosphere. The local frequency electric hair 'the resulting oxygen radical reacts with the ozone and the sample to perform oxidation. As the oxygen-containing gas, gases such as 〇2, h2o, and n2o may be exemplified. They may be used alone or as two. More than one type of mixed gas is used. Specifically, it is preferable to provide a semiconductor layer of a TFT in the vicinity of an oxygen-containing plasma source. Here, the distance between the plasma source and the semiconductor layer can be determined according to the type of plasma and the plasma generation condition. (Power (input power), pressure, temperature, irradiation time, gas composition, etc.) are set in an appropriate range, and it is preferable to have a range of several tens of 〇1. In the vicinity of such a plasma, there is a high-energy oxygen. By atom, it is possible to easily form a desired oxygen-containing layer on the surface of the semiconductor layer. When oxygen is supplied from an oxygen-containing plasma source or the like, an ion implantation method can be used. According to the ion implantation method, ions accelerated by an electric field can be moved by a long distance. Therefore, the distance between the plasma source and the semiconductor layer can be arbitrarily set. The ion implantation method preferably applies a negative high voltage pulse to a semiconductor layer provided in the vicinity of the plasma to inject ions into the entire surface of the semiconductor layer. Alternatively, ion implantation can be performed using a dedicated ion implantation apparatus. In addition, it is preferred that the treatment temperature is 300 ° C or higher. When the treatment temperature is lower than 300 °C, the progress of the oxidation reaction is slow, and it takes a long time to form an oxygen-containing layer which is effective as a diffusion barrier, and it is difficult to obtain better TFT characteristics. However, when the temperature is too high, the deterioration of the semiconductor layer as the workpiece and the damage of the semiconductor layer are liable to occur. Therefore, it is preferably at most 360 °C. In addition, it is preferable that the pressure is performed at a pressure of 55 Pa or more. When the pressure is lower than 55 Pa, the progress of the oxidation reaction is slow, and it takes a long time for the formation of the effective oxygen-containing layer. When the progress of the chemical reaction proceeds in a short period of time, it is possible to reduce the damage and form an oxygen-containing layer exhibiting good hindrance and an electrical resistivity. From the above point of view, the higher the pressure, the better, preferably better than 66P a. Further, since the pressure is stored in the performance of the apparatus to be used, etc., it is difficult to obtain a maximum of 400 P a of 266 Pa or less from the viewpoint of stabilizing the plasma supply. It is preferred that the plasma irradiation time is 60 minutes or less. When the electricity was applied for 60 minutes, the voltage drop formed in the amorphous germanium layer could not be ignored, and the TFT characteristics were lowered. When the plasma is irradiated, the latter is preferable, and those of 10 minutes or less are more preferable. When the upper limit is formed on the surface of the amorphous ruthenium layer, the surface of the ruthenium layer is formed to a certain extent (the time of the SiOx one atomic layer is more than the time from the viewpoint of sufficiently exerting the effect of the present invention. It is preferable that the electric power is 50 W or more. In the case of 50 W, the oxidation reaction proceeds slowly, and it is difficult to form an oxygen-containing layer having a suitable Si ratio, which is effective for forming a diffusion barrier. The TFT characteristics are degraded from a long period of time, and the higher the electric power is, for example, 60 W or more is preferable, and it is more preferable. As a diffusion barrier, the pressure is increased, and the loss of the oxygen semiconductor layer is sufficient to achieve a low contact, for example, an upper limit of 60 Pa or more. According to one place, but the latter is better, for the plasma irradiation time, the oxygen-containing layer of the super-surface is 30 minutes, and the oxygen-containing layer is irradiated with plasma for a period of time, at least in an amorphous state, with oxygen I, For the electric power of 5 seconds or more, the oxygen-containing gas is the above-mentioned oxygen gas (〇2, H2〇' from the viewpoint of the [〇]/[the oxygen-containing layer used, and the investment is 75W or more. N2〇, etc., it is also possible to dilute the oxygen-containing gas with an inert gas such as Ar. (i i ) Thermal Oxidation Method The thermal oxidation method is widely used for reasons such as excellent adhesion of an oxide film. Specifically, for example, in an oxygen atmosphere, it is preferred to heat at a temperature of 400 ° C or lower. When the heating temperature is high, the damage to the semiconductor layer becomes large. When the heating temperature is low, the desired oxygen-containing layer cannot be sufficiently formed. The heating temperature is controlled to be 200 ° C or more and 3 8 0 t: the following is preferable, and it is more preferable to control the temperature below 250 ° C to 3 50 ° C. The above heat treatment can be used in combination with the above-described plasma oxidation method, whereby the formation of the oxygen-containing layer can be further promoted. In this manner, it is preferable that the oxygen-containing layer is formed by the above methods (i) to (ii), but from the viewpoint of further simplifying the manufacturing process and shortening the processing time, the apparatus and the cavity used for the formation of the oxygen-containing layer are controlled as follows, Temperature and gas composition are preferred. First, in order to simplify the manufacturing process, it is preferred that the device be carried out using the same device as the semiconductor layer forming device. Thus, the workpiece handling the article does not need to be moved between the devices or within the device. Further, it is preferable that the temperature is substantially the same as the temperature at which the film formation temperature of the semiconductor layer is the same. Thereby, the adjustment time necessary for the temperature fluctuation can be omitted. Alternatively, the gas composition may be used by diluting the oxygen-containing gas with an inert gas such as Ar. When an oxygen-containing layer is formed on the semiconductor layer of the TFT, for example, when a Cu alloy layer is formed by a beach -15-201131785, a desired source-electrode electrode can be obtained. The thin film transistor substrate of the present invention, in the TFT semiconductor layer and The oxygen-containing layer is provided between the Cu alloy layers so as to cover the semiconductor layer of the TFT. Therefore, for example, the type of the semiconductor layer is not particularly limited, and it is generally used for the source-rhenium electrode without adversely affecting TFT characteristics. kind of. Any one or a combination of two or more of hydrogenated amorphous germanium, amorphous germanium, and polycrystalline germanium is preferred. Next, the Cu alloy layer of the present invention will be described. The Cu alloy layer (a) in the present invention may have a single-layer structure in which X (X is at least one selected from the group consisting of Mn, Ni, Zn, and Mg) in a total amount of 2 atom% or more and 20 atom% or less as an alloy element. (b) may also include, in order from the semiconductor layer side of the thin film transistor, a Cu alloy base layer (first layer) containing, as an alloying element, X (X is at least one selected from the group consisting of Mn, Ni, Zn, and Mg) and A pure Cu or a Cu alloy containing Cu as a main component, that is, a layered structure of a layer (second layer) composed of a Cu alloy having a lower specific resistance than the first layer. When the Cu alloy layer has the above laminated structure, the total content of X in the Cu alloy base layer (first layer) is preferably 2 atom% or more and 20 atom% or less. Regarding the single-layer structure The Cu alloy layer of the single-layer structure is a Cu-X alloy layer containing X (X is at least one selected from Mn, Ni, Zn, and Mg) as an alloying element. By forming such a Cu-X alloy layer, adhesion to the semiconductor layer can be improved without providing a barrier metal layer, and a low contact resistivity with the semiconductor layer can be achieved. These X elements are selected as elements which are solid-solubilized in Cu metal but not dissolved in the Cu oxide film. When the CU alloy in which these elements are solid-solved is oxidized by heat treatment in the film formation process, the element is diffused and thickened at the grain boundary or the interface, and the adhesion to the semiconductor layer is improved by the thickened layer. Further, these elements do not cause any damage to the usefulness of Cu (the low resistance of Cu itself and the low contact resistivity), and the above adhesion can be exhibited. Among the above X elements, Mn and Ni are preferred, and η is preferred. In particular, Μη is excellent in adhesion. Μη is an element which is very strongly present in the thickening phenomenon of the above-mentioned interface, in the process of manufacturing a display device such as a process of forming a film by a Cu alloy or after film formation, including, for example, an insulating film forming a SiN film. The thermal process) moves from the inside to the outside of the film. The movement of Μη to the interface is further promoted by the driving force of the Μη oxide generated by the oxidation of the heat treatment. As a result, the adhesion to the semiconductor layer is improved. The content of X in the Cu alloy layer of the single layer structure is 2 atom% or more and 20 atom% or less. When the above-mentioned elements are used alone as the X element, the individual amount may be sufficient to satisfy the above range. When two or more types are contained, the total amount may satisfy the above range. When the X content is less than 2 atom%, high adhesion to the semiconductor layer and low contact resistivity are not sufficiently achieved. On the other hand, when the X content exceeds 20 at%, the electric resistance of the entire Cu alloy layer becomes high, and as a result, the contact resistivity with the semiconductor layer becomes high. The X content is preferably in the range of 4 to 18% by atom, and preferably in the range of 6 to 15% by atom. The film thickness of the Cu alloy layer in the single layer structure is preferably from 100 to 500 nm. When the film thickness is less than 100 nm, the electric resistance of the Cu wiring becomes high, and when it exceeds 500 nm, the adhesion to the semiconductor layer cannot be ensured, and film peeling easily occurs. Single -17- 201131785 The thickness of the Cu alloy layer in the layer structure is preferably 200 to 400 nm. The alloying element of the Cu alloy base layer (first layer) in the laminated structure of the laminated structure is the same as the above-described single layer structure, and contains X as an alloying element (X is at least one selected from the group consisting of Mn, Ni, Zn, and Mg) Cu-X alloy layer. It is preferable that Mn or Ni' is more preferably Mn. The content of X in the Cu alloy base layer (first layer) is preferably the same as that in the case of the single layer structure, that is, preferably 2 atom% or more and 20 atom% or less. The reason for the foregoing range is the same as that of the single layer structure. The film thickness of the Cu-X alloy layer (first layer) in the laminated structure is preferably 10 nm or more and 100 nm or less. When the film thickness is less than 10 nm, the adhesion to the semiconductor layer cannot be ensured. On the other hand, when the film thickness exceeds 100 nm, the electric resistance of the entire Cu alloy (first layer + second layer) becomes high, and the problem of heat generation from the wiring becomes deep. The film thickness of the Cu-X alloy layer (first layer) is preferably 15 to 6 Onm. The second layer in the laminated structure is formed on the first layer, and is composed of pure Cu or a Cu alloy containing Cu as a main component, that is, a Cu alloy having a lower specific resistance than the first layer. By providing such a second layer, the electrical resistivity of the entire Cu alloy layer can be suppressed to be low. Here, the Cu alloy having a lower specific resistance than the first layer is appropriately controlled in terms of the type and/or content of the alloying element as compared with the first layer composed of the Cu-X alloy containing the X element to lower the specific resistance. An element having a low specific resistance (an element which is substantially lower than a pure copper alloy) can be easily selected from known elements by referring to a number of ruthenium or the like described in the literature. However, even if the element having a high resistivity is reduced in content (about 0.05 to 1 atom%), the resistivity can be lowered. Therefore, the alloy element to which the second layer can be applied is not. 18 - 201131785 It must be limited to an element having a low specific resistance. . Specifically, for example, 〇11-0.5 at% Ni, Cu-0.5 at% Zn, (^-0.3 at% Mn, etc. may be used. Further, as an alloy which can be applied to the second layer, even if it contains oxygen or nitrogen For example, Cu-0, Cu-N, etc. may be used. The thickness of the entire Cu alloy layer in the laminated structure (first layer + second layer) may be appropriately set according to the required TFT characteristics or the like, but It is preferably 200 nm or more and 500 nm or less, and more preferably 200 to 400 nm. In any case of the Cu alloy layer used in the present invention, a single layer structure and a laminated structure, the balance other than the above elements is Cu and not Impurity to be avoided. The tantalum alloy layer of the present invention is preferably formed by a sputtering method. In particular, when a laminated structure is formed, the material constituting the first layer is formed by sputtering, and then sputtered. The material constituting the second layer is formed thereon to form a laminated structure. After the Cu alloy laminated film is formed as described above, after a predetermined pattern is formed, it is processed from the viewpoint of covering the cross-sectional shape. Cone angle 45~60° left It is preferable that the right tapered shape is used. If a sputtering method is used, a Cu alloy layer having substantially the same composition as that of the sputtering target can be formed. Therefore, by adjusting the composition of the sputtering target, the composition of the Cu alloy layer can be adjusted. The composition may be adjusted by using a Cu alloy target, or the metal of the alloy element may be adjusted in a pure Cu target. Further, in the sputtering method, between the composition of the formed Cu alloy layer and the composition of the sputtering target. There is a slight deviation. However, the deviation is within a few atomic %. Therefore, if the composition of the sputtering target is controlled within a range of ±1 atomic % at maximum, a Cu alloy layer of a desired composition can be formed. The substrate to be used in the invention is not particularly limited, and examples thereof include -19-201131785 alkali-free glass, high strain point glass, limestone glass, and the like. [Embodiment] Hereinafter, the embodiment will be more specifically described. The present invention is not limited to the following embodiments, and the present invention can be modified and implemented within the scope of the following gist of the present invention, which are all included in the technical scope of the present invention. Embodiment 1 In this embodiment, the contact resistivity and adhesion of a Cu alloy layer (laminated structure) and a semiconductor layer are discussed. (1) Measurement of contact resistivity with a semiconductor layer In order to investigate a Cu alloy layer and a semiconductor layer The contact resistivity of the TLM (Transfer Length Method) device was measured, and the contact resistivity was measured by the TLM method shown in Figs. 2 and 3. First, a method of fabricating the TLM device will be described. First, plasma CVD is performed on the glass substrate. The method forms a low-resistance amorphous germanium film doped with impurities (P) having a thickness of about 200 nm at a thickness of about 200 nm. Then, only oxygen is supplied to the plasma in the same plasma CVD apparatus, and the plasma is passed through the oxygen plasma. The surface of the low-resistance amorphous germanium film was treated for 30 seconds to form an oxygen-containing layer. As the oxygen plasma device, a measuring device (model: PR41) manufactured by Yamato Scientific Co., Ltd. was used, and electric power was applied at 450 W, and the film forming temperature was room temperature, and the gas pressure was 67 Pa. -20- 201131785 Next, 'Cu alloy film is formed by sputtering method (single layer structure. Laminated structure). In more detail, the film formation of a single layer structure is a pure Cvi or cu which is formed by the composition shown in Table 1 at 300 nm. The film of the alloy and the film formation of the laminated structure were deposited on the substrate under the conditions shown in Tables 2 to 4, and a pure film (the film thickness of the entire Cu alloy layer: about 300 nm) was formed thereon. The sputtering temperature was room temperature. After the protective layer is patterned by photoetching, the CuM alloy film is etched with the protective layer as a mask, thereby forming a plurality of electrodes. Here, various changes are made to the distance between the electrodes. Finally, heat treatment was carried out for 30 minutes at 270 ° C for analogy to the actual fabrication process of thin film transistors. Next, the principle of measuring the contact resistance by the TLM method will be described with reference to Figs. 2 and 3 . Fig. 2(a) is a cross-sectional view schematically showing a wiring structure of a TLM element fabricated according to the above-described method, and Fig. 2(b) is a plan view of the TLM element. First, in the wiring structure of Fig. 2(a), the current-voltage characteristics between the plurality of electrodes were measured, and the resistance 値 between the electrodes was obtained. The resistance 値 between the electrodes thus obtained was plotted on the vertical axis, and the distance between the electrodes (transition length, L) was plotted on the horizontal axis to obtain a graph of Fig. 3 . In the graph of Fig. 3, 値 of the y slice corresponds to 値(2 R c ) twice the contact resistance R c , and the front X of the X slice corresponds to the effective contact length (LT: transger length ). From the above, the contact resistivity pc is represented by the following formula.
Pc = Rc * Lt * Z 式中，Z是圖2(b)中所示的電極寬度。 -21 - 201131785 (2 )黏著性的測定 以如下要領製作黏著性評價試驗用的試料。首先，在 玻璃基板上利用電漿CVD法形成膜厚lOOnm的SiN膜，和膜 厚200nm的摻雜雜質（P)的低電阻的非晶矽膜（n-a-si: Η層）。該低電阻的非晶矽膜（n-a-Si : Η層）是利用進行 以SiH4、ΡΗ3爲原料的電漿CVD而形成的。電漿CVD的成 膜溫度爲320°C。 接著，在相同的電漿CVD裝置的相同的腔內僅供給氧 氣，使電漿產生，通過氧電漿對上述的低電阻的非晶矽膜 的表面進行30秒的處理，形成含氧層。氧電漿的條件與上 述測定接觸電阻率時相同。 接著，利用濺射法分別根據表1 (單層結構）、表2〜 4 (層積結構）所示的條件（X含量、膜厚）形成Cu-X合 金膜。對於層積結構在表2〜4所示的第一層之上再形成純 Cu膜。Cu合金膜全體的膜厚，單層結構時爲大約3 00nm， 層積結構時爲大約3 OOnm，濺射溫度爲室溫。接著，利用 光蝕刻對保護層形成圖案後，以保護層爲遮罩，對Cu系合 金膜進行蝕刻，由此，形成黏著性試驗用的圖案。其後， 在氮氣環境下，在270°C進行30分鐘的熱處理》 黏著性評價通過膠帶剝離試驗進行。詳細地說，利用 刀刃在Cu合金膜的表面切刻1mm間隔的棋盤狀的切痕。接 著，將住友3M社制的黑色聚酯膠帶（產品編號8422B )緊 密貼在上述Cu合金膜上，上述膠帶的剝離以保持在60。一 -22- 201131785 舉剝下該膠帶，計算由上述膠帶剝下的棋盤格的數目，求 出和全數目的比率（膜剝離率）。測定進行三次，將三次 的平均値作爲各試料的膜剝離率。 根據接觸電阻率和黏著性的測定結果，接觸電阻率低 於2 Ω _ cm2，並且膜剝離率低於1 0 %的爲合格，其他的爲不 合格。這些結果在表1〜3中顯示。 【表1】Pc = Rc * Lt * Z where Z is the electrode width shown in Figure 2(b). -21 - 201131785 (2) Measurement of adhesion The sample for the adhesion evaluation test was prepared in the following manner. First, a SiN film having a thickness of 100 nm and a low-resistance amorphous germanium film (n-a-si: germanium layer) doped with impurities (P) having a thickness of 200 nm were formed by a plasma CVD method on a glass substrate. The low-resistance amorphous germanium film (n-a-Si: germanium layer) is formed by plasma CVD using SiH4 and germanium 3 as raw materials. The plasma CVD film formation temperature was 320 °C. Next, oxygen gas was supplied only in the same chamber of the same plasma CVD apparatus to generate plasma, and the surface of the above-mentioned low-resistance amorphous ruthenium film was treated with oxygen plasma for 30 seconds to form an oxygen-containing layer. The conditions of the oxygen plasma are the same as those in the above measurement of the contact resistivity. Next, a Cu-X alloy film was formed by sputtering according to the conditions (X content, film thickness) shown in Table 1 (single layer structure) and Table 2 to 4 (layer structure). A pure Cu film was formed on the first layer shown in Tables 2 to 4 for the laminated structure. The film thickness of the entire Cu alloy film is about 300 nm in a single layer structure, about 300 nm in a stacked structure, and the sputtering temperature is room temperature. Next, after the protective layer was patterned by photolithography, the protective layer was used as a mask, and the Cu-based alloy film was etched to form a pattern for adhesion test. Thereafter, heat treatment was performed at 270 ° C for 30 minutes in a nitrogen atmosphere. The adhesion evaluation was carried out by a tape peeling test. Specifically, a checker-shaped cut of 1 mm intervals was cut on the surface of the Cu alloy film by a blade. Then, a black polyester tape (product number 8422B) manufactured by Sumitomo 3M Co., Ltd. was adhered to the above-mentioned Cu alloy film, and the tape was peeled off and kept at 60. -22- 201131785 Lift the tape and calculate the number of checkerboard strips peeled off from the above tape to find the ratio of the total number (film peeling rate). The measurement was performed three times, and the average enthalpy of three times was taken as the film peeling rate of each sample. According to the measurement results of contact resistivity and adhesion, the contact resistivity was lower than 2 Ω _ cm 2 , and the film peeling rate was less than 10%, which was acceptable, and the others were unacceptable. These results are shown in Tables 1 to 3. 【Table 1】
No. 膜組成 接觸電阻率 (Ω .cm2〉 膜剝離率 (%) 電阻率 (jj Ω ·ογπ) 1 純Cu 3.20 98 2.0 2 Cu_2 原子 ％Mn 0.35 2 2.0 3 Cu—6 原子 ％Mn 0.18 2 - 4 Cu—10原子％1^〇 0.25 0 - 5 Cu — 20原子％"〇 0.16 0 - ※膜厚30〇n m 【表2】No. Membrane composition contact resistivity (Ω.cm2> Membrane peeling rate (%) Resistivity (jj Ω ·ογπ) 1 Pure Cu 3.20 98 2.0 2 Cu_2 Atomic % Mn 0.35 2 2.0 3 Cu-6 Atomic % Mn 0.18 2 - 4 Cu—10 atom%1^〇0.25 0 - 5 Cu—20 atom%"〇0.16 0 - ※ film thickness 30〇nm [Table 2]
No. 第一層合金組成 接觸電阻率 (Ω *cm2) 膜剝離率 (%) 電阻率 (/i Ω *cm) 1 純Cu 3.2 98 2.0 2 Cu—0.5 原子 ％Mn 0.29 8 2.0 3 Cu—2 原子 ％Mn 0.25 3 2.0 4 Cu—4 原子 ％Mn 0.22 3 2.0 5 Cu—6 原子 0.21 2 2.0 6 Cli 一 10原子％1\^打 0.20 0 2.1 7 Cu —12原夺 0.18 0 2.1 8 Cu — 15原子 0.19 0 2.1 9 Cu—20 原子 ％Mn 0.15 0 2.2 ※第一層的膜厚20nm 【表3】No. First layer alloy composition contact resistivity (Ω *cm2) Film peeling rate (%) Resistivity (/i Ω *cm) 1 Pure Cu 3.2 98 2.0 2 Cu-0.5 Atomic % Mn 0.29 8 2.0 3 Cu-2 Atomic % Mn 0.25 3 2.0 4 Cu - 4 Atomic % Mn 0.22 3 2.0 5 Cu - 6 Atom 0.21 2 2.0 6 Cli - 10 Atomic A1 / ^ 0.20 0 2.1 7 Cu - 12 Original 0.18 0 2.1 8 Cu - 15 Atom 0.19 0 2.1 9 Cu—20 Atomic % Mn 0.15 0 2.2 ※ The film thickness of the first layer is 20 nm [Table 3]
No. 第一層膜厚 (nm) 接觸電阻率 (Q ecm2) 膜剝離率 (%) 電阻率 (jj Ω *cm) 1 5 1.60 21 2.0 2 10 0.28 4 2.0 3 20 0.20 0 2.0 4 50 0.21 0 2.1 5 80 0.18 0 2.1 6 100 0.15 0 2.2 ※第一層的組成爲Cu —10原子％Mn -23- 201131785 【表4】No. First film thickness (nm) Contact resistivity (Q ecm2) Film peeling rate (%) Resistivity (jj Ω *cm) 1 5 1.60 21 2.0 2 10 0.28 4 2.0 3 20 0.20 0 2.0 4 50 0.21 0 2.1 5 80 0.18 0 2.1 6 100 0.15 0 2.2 ※ The composition of the first layer is Cu - 10 atomic % Mn -23- 201131785 [Table 4]
No. 第一層合金組成 接觸電阻率 (Ω .cm2) 膜剝離率 (%) 1 Cu-4 原子 ％Ni 0.86 3 2 1.27 6 3 Cu—4 原子 ％Zn 1.10 5 ※第一層的膜厚2〇nm 從表1、表2可知合金元素X的含量和與半導體層的接 觸電阻率以及黏著性的關係。表1的No.l是不含有合金元 素的純Cu的現有例，接觸電阻率高，黏著性也下降。對此 ，表1的Νο·2〜5的Μη量被適當控制，因此能夠實現希望的 低接觸電阻率和高黏著性。表2的No.l是不含有合金元素 的純Cu的現有例，接觸電阻率高，黏著性也下降。表2的 No.2是合金元素X的含量少的例，與純Cu的No.l相比接觸 電阻率和黏著性得到改善。對此，表2的No.3〜9的Μη被適 當含有，所以能夠實現希望的低接觸電阻率和高黏著性。 從表3可知第一層的爲佳的膜厚和接觸電阻率以及黏 著性的關係。表3的No.l第一層的膜厚薄，因此，黏著性 下降。而表3的No.2〜6的第一層的膜厚被控制在優選範圍 內，因此，能夠實現低接觸電阻率和高黏著性。 在表4中，作爲第一層的合金元素使用Ni、Mg、Zn， 在使用任一元素時，能夠實現低接觸電阻率和高黏著性。 實施例2 在本實施例中對形成於半導體層表面的含氧層對於。 合金層的Cu原子向半導體層擴散的防止進行討論。 首先，在玻璃基板上通過電漿CVD法形成膜厚大，約 -24- 201131785 lOOnm的SiN膜’在其上形成膜厚2〇〇nm的摻雜雜質（p ) 的低電阻的非晶矽膜（n-a-Si: Η層）。電漿CVD的成膜溫 度爲320°C。 接著’在相同的電漿C VD裝置的相同的腔內僅供給氧 氣，使電獎產生，利用氧電漿對上述的低電阻的非晶矽膜 的表面進行10分鐘的處理，形成含氧層。作为氧電漿装置 ’使用大和（YAM ΑΤΟ )科學社製的測量裝置（型號： ?1141)，頻率爲13.56112，投入電力45〇%,成膜溫度爲室 溫，氣體壓力爲67Pa。 接著’通過濺射法形成第一層··(膜厚 :20nm)，第二層：純Cu (膜厚：28〇nm )的以合金層。 其後’在270°C進行30分鐘的熱處理。 對以上述要領製作的試料通過GD_〇es分析，對Cu合 金層成膜後以及熱處理後的深度方向的元素進行分析。 GD-OES分析是從成膜完成後的試料的膜表面（上層）， 通過高頻濺射削去膜同時對膜進行分析的方法。GD-OES 分析的條件如下所述。 氣體壓力300Pa、電力20W、頻率500Hz、能率比0.125 另外’除不進行氧電漿處理，作爲Cu合金層第一層： Cu-l(m子％Mn (膜厚：2〇nm )、第二層：純Cu (膜厚： 2 8 0 nm )以外’與上述s式料相同，製作比較用的試料。 在圖4(a) 、 （b)中顯示這些結果。圖4(a)是顯 示不進行氧電漿處理時的元素分析結果的曲線圖，圖4 ( b )是進行了氧電漿處理時的元素分析結果的曲線圖。圖中 -25- 201131785 虛線表示進行熱處理前的狀態’實線表示熱處理後的狀態 0 從圖4(a)可知’在不進行氧電漿處理時，在熱處理 後Cu合金層中的Si濃度增加，因此，由於熱處理以和“的 相互擴散發生。而在圖4(b)中熱處理前後濃度關係基本 未發現變化，可知抑制Cu和Si的相互擴散。 實施例3 在本實施例中對含氧層中的〔0〕/〔Si〕比和含氧層 的膜厚對於接觸電阻率和黏著性的影響進行討論。 (1 )含氧層中的〇和Si的結合狀態的測定 試料的製作除作爲Cu合金層第一層：Cu-4原子％Mn ( 膜厚：20nm)、第二層：純Cu (膜厚：280nm)以外，與 實施例1的黏著性評價試驗相同。另外，氧電漿處理中的 氧氣流量爲30sccm。 對試料進行XPS分析，測定含氧層中Si和Ο的結合狀態 。其結果在圖5中顯示。根據圖5可知，在99.3eV位置檢測 到SNSi結合產生的峰値，在103.5eV位置檢測到Si-Ο結合 產生的峰値。根據這些峰値強度可知，含氧層中的〔〇〕/ 〔Si〕比爲0.88。對該試料進行與實施例1相同的接觸電阻 率測定，測定接觸電阻率，此時接觸電阻率爲〇 . 2 Ω · em2。 即含氧層中的〔〇〕/〔Si〕比爲0.88時，滿足本發明的爲 佳條件，能夠確認到實現了低接觸電阻率。 -26- 201131785 (2)含氧層中的〔〇〕/〔si〕比和含氧層的膜厚對於接 觸電阻率和黏著性的影響的討論 試料的製作除作爲Cu合金層第一層：Cu-10原子。AMn (膜厚：20nm)、第二層：純Cu (膜厚：280nm )，以表 5所示條件進行氧化處理以外’與實施例1的黏著性評價試 驗相同。作爲UV氧化處理的條件，使用GSYUASA社制UV 照射裝置（型號·· DUV-8 00-6 )，燈電壓：300V，UV照射 時間：1分鐘，作爲電漿氧化處理的條件’頻率：13.5 6 Hz ，電力：450W，處理溫度：室溫，氣體氣氛：氧，氣體 壓力：67Pa，處理時間：30分鐘。對表5所示各試料，與 實施例1相同測定接觸電阻率，並且，與實施例2同樣利用 GD-OES分析測定熱處理後的Cu、Si濃度關係。根據Cu、 Si濃度關係，將抑制Cu和Si相互擴散的爲〇，擴散發生的 爲X。 結果在表5中顯示。 【表5】No. First layer alloy composition contact resistivity (Ω.cm2) Film peeling rate (%) 1 Cu-4 Atomic % Ni 0.86 3 2 1.27 6 3 Cu-4 Atomic % Zn 1.10 5 * Film thickness of the first layer 2 〇nm From Tables 1 and 2, the relationship between the content of the alloying element X and the contact resistivity and adhesion to the semiconductor layer is known. No. 1 in Table 1 is a conventional example of pure Cu which does not contain an alloy element, and has a high contact resistivity and a low adhesiveness. On the other hand, the amount of Μη of Νο·2 to 5 in Table 1 is appropriately controlled, so that a desired low contact resistivity and high adhesion can be achieved. No. 1 in Table 2 is a conventional example of pure Cu which does not contain an alloying element, and has a high contact resistivity and a low adhesiveness. No. 2 in Table 2 is an example in which the content of the alloying element X is small, and the contact resistivity and the adhesion are improved as compared with No. 1 of pure Cu. On the other hand, the Μη of Nos. 3 to 9 in Table 2 are appropriately contained, so that a desired low contact resistivity and high adhesion can be achieved. From Table 3, the relationship between the film thickness and the contact resistivity and the adhesion of the first layer is known. The first layer of No. 1 in Table 3 has a small film thickness, and therefore the adhesiveness is lowered. On the other hand, the film thicknesses of the first layers of Nos. 2 to 6 in Table 3 were controlled within a preferred range, and therefore, low contact resistivity and high adhesion were able to be achieved. In Table 4, Ni, Mg, and Zn are used as the alloying elements of the first layer, and when any element is used, low contact resistivity and high adhesion can be achieved. Embodiment 2 In this embodiment, an oxygen-containing layer formed on the surface of a semiconductor layer is used. The prevention of diffusion of Cu atoms of the alloy layer into the semiconductor layer will be discussed. First, a low-resistance amorphous germanium having a film thickness of about -24 - 201131785 lOOnm is formed on the glass substrate by a plasma CVD method to form a doping impurity (p) having a film thickness of 2 〇〇 nm. Membrane (na-Si: Η layer). The film formation temperature of the plasma CVD was 320 °C. Then, 'only oxygen is supplied to the same cavity of the same plasma C VD device to generate the electric prize, and the surface of the above-mentioned low-resistance amorphous ruthenium film is treated with oxygen plasma for 10 minutes to form an oxygen-containing layer. . As an oxygen plasma device, a measuring device (model: ?1141) manufactured by Yamato Scientific Co., Ltd. (model: ?1141) was used, the frequency was 13.56112, the input power was 45%, the film formation temperature was room temperature, and the gas pressure was 67 Pa. Next, a first layer (film thickness: 20 nm) was formed by a sputtering method, and a second layer: an alloy layer of pure Cu (film thickness: 28 Å). Thereafter, heat treatment was performed at 270 ° C for 30 minutes. The samples prepared in the above manner were analyzed by GD_〇es, and the elements in the depth direction after the formation of the Cu alloy layer and after the heat treatment were analyzed. The GD-OES analysis is a method of analyzing a film from a film surface (upper layer) of a sample after film formation by high-frequency sputtering. The conditions for the GD-OES analysis are as follows. Gas pressure 300Pa, electric power 20W, frequency 500Hz, energy ratio 0.125, in addition to 'no oxygen plasma treatment, as the first layer of Cu alloy layer: Cu-l (m sub% Mn (film thickness: 2〇nm), second Layer: Pure Cu (thickness: 280 nm) is the same as the above s-type material, and a comparative sample is prepared. These results are shown in Fig. 4 (a) and (b). Fig. 4 (a) is a display A graph showing the results of elemental analysis when oxygen plasma treatment is not performed, and Fig. 4 (b) is a graph showing the results of elemental analysis when oxygen plasma treatment is performed. In the figure -25-201131785, the dotted line indicates the state before heat treatment. The solid line indicates the state after the heat treatment. 0 As is clear from Fig. 4(a), when the oxygen plasma treatment is not performed, the Si concentration in the Cu alloy layer is increased after the heat treatment, and therefore, the interdiffusion occurs due to the heat treatment. In Fig. 4(b), the concentration relationship was not substantially changed before and after the heat treatment, and it was found that the mutual diffusion of Cu and Si was suppressed. Example 3 In the present example, the ratio of [0]/[Si] in the oxygen-containing layer and oxygenation were observed. The effect of the film thickness of the layer on the contact resistivity and adhesion is discussed. (1) In the oxygen-containing layer The measurement sample of the state of bonding with Si was prepared as the first layer of Cu alloy layer: Cu-4 atom% Mn (film thickness: 20 nm), and the second layer: pure Cu (film thickness: 280 nm), and Example 1 The adhesion evaluation test was the same. The oxygen flow rate in the oxygen plasma treatment was 30 sccm. The sample was subjected to XPS analysis to determine the bonding state of Si and cerium in the oxygen-containing layer. The results are shown in Fig. 5. The peak of SNSi binding was detected at the 99.3 eV position, and the peak of Si-Ο binding was detected at the position of 103.5 eV. According to the intensity of these peaks, the ratio of [〇]/[Si] in the oxygen-containing layer was 0.88. The same contact resistivity as in Example 1 was measured for the sample, and the contact resistivity was measured. The contact resistivity at this time was 〇. 2 Ω · em2. That is, the [〇]/[Si] ratio in the oxygen-containing layer was At 0.88, it is confirmed that the low contact resistivity is achieved by satisfying the conditions of the present invention. -26- 201131785 (2) The [〇]/[si] ratio in the oxygen-containing layer and the film thickness of the oxygen-containing layer are in contact with each other. Discussion of the influence of resistivity and adhesion on the preparation of the sample except the first as a Cu alloy layer Layer: Cu-10 atom, AMn (film thickness: 20 nm), second layer: pure Cu (film thickness: 280 nm), and the oxidation treatment was carried out under the conditions shown in Table 5, which was the same as the adhesion evaluation test of Example 1. As a condition for the UV oxidation treatment, a UV irradiation apparatus (Model··DUV-8 00-6) manufactured by GSYUASA Co., Ltd., lamp voltage: 300 V, UV irradiation time: 1 minute was used as a condition for plasma oxidation treatment 'Frequency: 13.5 6 Hz, power: 450W, treatment temperature: room temperature, gas atmosphere: oxygen, gas pressure: 67Pa, treatment time: 30 minutes. With respect to each sample shown in Table 5, the contact resistivity was measured in the same manner as in Example 1, and the relationship between the concentration of Cu and Si after the heat treatment was measured by GD-OES analysis in the same manner as in Example 2. According to the relationship between the concentration of Cu and Si, the mutual diffusion of Cu and Si is suppressed, and the diffusion occurs as X. The results are shown in Table 5. 【table 5】
No. 氧化處理 [〇]/[Si]比 含氧層 膜厚 (nm) 接觸電阻率 (Ω - cm2) 相互擴散 1 UV氧化（1分） 0.37 1.2 0.20 X 2 電漿氧化(3分） 0.61 1.7 0.23 〇 3 電獎氧化(30分） 1.14 2.5 0.70 〇 4 電漿氧化(60分） 1.75 3.0 1.80 〇 5 電漿氧化(120分） 1.82 4.0 6.50 〇 表5的No.2〜4由於適當控制〔〇〕/〔Si〕比和含氧層 的膜厚，所以Cu和S i相互擴散得到抑制，能夠實現低接觸 電阻率和高黏著性。而表5的Νο·1，由於UV氧化時間短， -27- 201131785 另外由於UV比電漿的氧化效果小，因此，〔Ο〕/〔 Si〕比 小，含氧層的膜厚變小，發生相互擴散，黏著性下降。另 外，表5的No.5，含氧層的厚度超出了爲佳範圍，因此， 雖然黏著性良好，但是接觸電阻率變高。 【圖式簡單說明】 圖1爲模式化顯示本發明的適用例的源-汲電極的構 成之槪略圖。 圖2爲說明TLM元件進行的接觸電阻率的測定原理之 圖。 圖3爲顯示電極距離和電阻的關係之曲線圖。 圖4 (a)是顯示未進行氧電漿處理時的Cu和Si的濃度 態勢（profile)的曲線圖，圖4(b)是顯示進行了氧電漿 處理時的Cu和Si的濃度態勢（profile)的曲線圖。 圖5爲顯示利用XP s分析進行的結晶衍射峰値之曲線圖 【主要元件符號說明】 2 6 :概電極 2 7 :柵極絕緣膜 2 8 :源電極 29 :汲電極 28a 、 29a :含氧層 28b 、 29b : Cu合金層 -28- 201131785 3 3 :非晶矽通道層（活性半導體層） 5 2 :阻障金屬層 -29-No. Oxidation treatment [〇]/[Si] Thickness of oxide film (nm) Contact resistivity (Ω - cm2) Interdiffusion 1 UV oxidation (1 point) 0.37 1.2 0.20 X 2 Plasma oxidation (3 points) 0.61 1.7 0.23 〇3 Electric Award Oxidation (30 points) 1.14 2.5 0.70 〇4 Plasma Oxidation (60 points) 1.75 3.0 1.80 〇5 Plasma Oxidation (120 points) 1.82 4.0 6.50 No Table 5 No. 2~4 due to proper control Since the [〇]/[Si] ratio is thicker than the film of the oxygen-containing layer, mutual diffusion of Cu and Si is suppressed, and low contact resistivity and high adhesion can be achieved. In the case of Νο·1 of Table 5, since the UV oxidation time is short, -27-201131785, since the UV has a smaller oxidation effect than the plasma, the [Ο]/[Si] ratio is small, and the film thickness of the oxygen-containing layer becomes small. Interdiffusion occurs and adhesion decreases. Further, in No. 5 of Table 5, the thickness of the oxygen-containing layer exceeded a preferable range, and therefore, although the adhesiveness was good, the contact resistivity became high. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing the construction of a source-electrode electrode of a practical example of the present invention. Fig. 2 is a view for explaining the principle of measuring the contact resistivity by the TLM device. Figure 3 is a graph showing the relationship between electrode distance and resistance. 4(a) is a graph showing the concentration profile of Cu and Si when no oxygen plasma treatment is performed, and FIG. 4(b) is a graph showing the concentration postures of Cu and Si when the oxygen plasma treatment is performed ( Profile) of the graph. Fig. 5 is a graph showing a crystal diffraction peak 利用 by XP s analysis [main element symbol description] 2 6 : a general electrode 2 7 : a gate insulating film 2 8 : a source electrode 29: a germanium electrode 28a, 29a: oxygen-containing Layer 28b, 29b: Cu alloy layer -28- 201131785 3 3 : Amorphous germanium channel layer (active semiconductor layer) 5 2 : barrier metal layer -29-