201124006 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種印刷電路板結構， ^ 利用訊號導線之厚度或寬度而調整特^疋關於一種 板。 阻抗之印刷電路基 【先前技術】 於大型印刷電路基板以及封裝基板上，/ 線以電性連接兩個不同之元件或端點 係採用訊號導201124006 VI. Description of the Invention: [Technical Field] The present invention relates to a printed circuit board structure, which is adapted to a board by the thickness or width of the signal conductor. Impedance printed circuit base [Prior Art] On large printed circuit boards and package substrates, / wires are electrically connected to two different components or end points.
冉線寬均Φ /J2L 致以使電子訊號在訊號導線之間傳遞時 2 抗（characteristic impedance)能保持不變。等，之，性阻 咼頻的訊號傳遞上，兩元件或端點之 贽在同速與 阻抗匹配設計，以降低阻抗不匹配所造成之要藉由良好的 J射將形成雜音而降低了於其之間所傳遞的 因岸=區=型印刷電路基板以及封裝基板的製作中， 因應不Η £域内元件所需設置情形 不同區域内之大型印刷電λ ，、’因“要針對 或平面切财切裝純進行如鑽孔 ,見印刷電路板製程的實施，因此於大型印 厘声乂1佶封裝基板上不同區域内之介電層的層數、 厚度以及使：材料之介電常數上便產生了差異。 、 入@:大型印刷電路基板以及封裝基板上之不同區 域内、曰的層數、厚度與使用材料之介電材料上有所 差異’；同區域内具有線寬一致之訊號導線將受到麒 201124006 ' 其鄰近的介電層的介電材料特性的影響，因而於大型印刷 - 電路基板以及封裝基板上之不同區域内之訊號導線段部中 產生了不期望之訊號導線阻抗不匹配的問題。 【發明内容】 有鑑於此，本發明提供了 一種利用訊號導線之厚度或 寬度而調整不同區域内之訊號導線的特性阻抗之印刷電路 基板，藉以克服印刷電路基板内之多個區域内之介電層特 $ 性差異問題。 依據一實施例，本發明提供了一種可調整特性阻抗之 印刷電路基板，包括： 一第一介電層，其上定義有相鄰之一第一區與一第二 區，其中該第一介電層具有相對之第一表面與第二表面； 一第一導電層，設置於該第一介電層之該第一區與該第二 區内之該第一表面的一部上；一第二導電層，設置於該第 一介電層之該第一區内之該第一導電層之上，其中該第二 • 導電層與該第一導電層具有相同線寬並構成了一訊號導 線；以及一第二介電層，設置於該第一介電層之該第一區 内之該第二導電層之上或該第一介電層之該第一區内之該 第二表面之上。 依據另一實施例，本發明提供了一種可調整 之印刷電路基板，包括： ^ ^ 一第一介電層，其上定義有相鄰之一第一區、一第二 區與一第三區，其中該第一介電層具有相對之第一表面= 第二表面；一第一導電層，設置於該第一介電層之^第二 201124006 區、該第二區與該第三區内之該第—表面的一部上. 二導電層，設置於該第—介電層之該第-區與該第三區内 之該第-導電層之上，其中該第二導電層與該第4 具有相同線寬；一第三導電層與一第二介電層，^ 於該第-介電層之該第-區内之該第二導電層之上 該第三導電層與該第二導電層以及該第一導目 ，，且該第三導電層、該第二導電層以及該第 號導線，以及一第三介電層與一第四介電層， 为別设置於該第一介電層之該第— 二表面之上。 /第咖第三區内之該第 依據又-實施例’本發明提供了—種可調 之印刷電路基板，包括： 子!·生阻抗 -第-介電層’其上定義有相鄰之一第一區盘二 第其=一介電層具有相對之第-表面與第：表面7 表=於該第—介電層之該第—區與該第二 部上，其中該第-導電層包括:- 面之上，具有固定之一第—一 ^弟表 第一介電層之該第二區内之該’ 段部，設置於該 -第二線寬，其中該第二線之上，具有固定之 二設置於該第一介電層之該第一區 ： =二之上且實體接觸該第-段部與該第；ί 中該第二段部具有非固定二其 :於該第-線寬及不大於該第二線寬：第^ 層，設置於該第-介電層之該第-區内之=4;;: 201124006 上以部份覆蓋該第-導電層之該第三段部以及完 -導電層之該第-段部’紐置於該第—介 區之該第二表面之上。 弟一 依據另-實施例’本發明提供了—種可調整特 之印刷電路基板，包括： & 一第一介電層’其上定義有相鄰之 、 ^與:第三區，其中該第—介電層具有相對之第—表砂 第二表面；一第一導電層’設置於該第-介電層之該第二 區、該第二區與該第三區内之該第一表面的一部上， 該第-導電層包括：-第一段部，設置於該第一介電層之 第一表面之上’具有固定之-第-線寬； -又和&置於該第—介電層之該第二區内之該第一 兮：之i寳具有，定之一第二線寬’其中該第二線寬大於 寬，以及一第三段部，設置於該第一介電層之該 由之邊第一表面之上，具有固定之-第三線寬，ι 寬該第：線寬小於該第二線寬且相等或不相等於該第一線 ^:第四段部，設置於該第—介電層之該第—區與該第 :内之該第-表面之上且實體接觸 :r:r固定之一第四線寬，其中該第四^ :二線；且不大於該第二線寬；以及一第五段部，設置 且實電層之該第二區與該第三區之該第一表面之上 五線寶甘該第二段部與該第三段部，具有非固定之一第 二繞ΐ該第五線寬不小於該第三線寬且不大於該第 -介ί展帛一導電層與一第二介電層’依序設置於該第 之該第一區内之該第一導電層之上，以部份覆蓋 201124006 該第一導電層之該第四段部以及完全覆蓋該第一段部；以 及一第三介電層，設置於該第一介電層之該第三區之該第 二表面之上。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 【實施方式】 以下將配合第1-11圖詳細說明本發明一實施例之可調 整特性阻抗之印刷電路基板的製作。此處須注意的是，該 些圖式均為簡化之示意圖，以強調本發明之特徵，因此圖 中之元件尺寸並非完全依實際比例繪製。且本發明之實施 例也可能包含圖中未顯示之元件。 首先，提供適用於印刷電路基板製作之一介電層1〇〇, 其具有相對之兩個表面102、104，而介電層100之上則大 體定義有三個相鄰之區域A、B與C。於區域A、B與C 内之介電層100的表面102之上則坦覆地形成有一導電層 106，而於區域A内之表面104之上則形成有一導電層 108。在此，導電層106與108例如為一超薄之金屬層或非 金屬導體層，導電層106之厚度顯示為T!，而導電層108 之厚度顯示為T2，而介電層100之材質如紙質酚醛樹脂 (paper phenolic resin)、複合環氧樹脂（composite epoxy)、聚 201124006 亞醯胺樹脂(polyimide resin)或玻璃纖維(glass fiber)等絕緣 材料。於介電層100之上形成導電層106與108之方法例 如為濺鎪（sputtering)、壓合（laminate)或塗佈（coating)等製 程0 請參見第2圖，於導電層106之上形成一光阻層no， 光阻層110例如為一乾膜光阻，其可於一適當之溫度與壓 力之下密合貼附於導電層106之上。 請參照第3圖，接著施行一微影程序114以曝光光阻 層110。在此，微影程序114中使用了具有複數個遮光區 112a以及至少-透光區U2b之—光罩ιΐ2，其中透光區 112b大體對準於區域B’而遮规心則大體對 A與〇於微影程序114施行過後，_Bj^光 =過曝光後成為經曝光之植層⑽，並於區域AW内 留下為未經曝光之光阻層11〇a。 八 光之光阻層ma並露出區域未顯不），移除未經曝 進行一沈積製程(未顯示= 與二之導電層⑽ 製程，以於區域八與。内為一道電鍍製程或-化學鍵 為m金之_ 電層116，其材質可 以銅為較常使用之材料。金屬導電材料，其中又 地與區域B内之導電層1〇6 κ，導電層116之厚度T3較佳 6上之經曝光之光阻芦彳〗；(：目 同，以提供後續製程施行之—平整表面。^層11%相 請參照第5圖，於導電 > .^ ^ 1ΛΟ θ 116與經曝光之光阻層ii〇b 之上形成一先阻層118’光阻 其可於-適當之溫度與壓力；六’*”、-乾膜光阻， 之下岔S貼附於導電層116與 201124006 經曝光之光阻層ll〇b之上。 請參照第6圖’接著施行一微影程序122以曝光光阻 層118。在此，微影程序122中使用了具有一遮光區12〇& 以及一透光區120b之一光罩120，其中透光區120b大體 對準於區域B與C，而遮光區120a則大體對準了區域A。 於祕影程序122施行過後，區域B與C内之光阻層118經 過曝光後成為經曝光之光阻層118b，並於區域a内留下為 未經曝光之光阻層118a。 ^睛參照第7圖，施行一顯影程序（未顯示），移除未經曝 光之光阻層118a並露出區域A内之導電層116。接著，進 仃一沈積製程（未顯示），例如為一電鍍製程或一化學鍍製 程’以於區域A内形成-導電層12〇,其材f可為銅、銘、 鎳、金之金屬或其他非金屬導電材料，其中又以銅為較常 使用之材料。在此，導電層12G之厚度τ4較佳地與區域b 與C内之導電層116上之經曝光之光阻層服相同， 供後續製程施行之一平整表面。 請參照第8目，施行-脫膜程序（未顯示）以將區域 fC内之經曝光之光阻層簡與⑽剝除，並露出區土 内之導電層ι〇6(見於第7圖）與區域c内之導電層ιΐ6〇 =第7圖）。接著針對此些導電層⑽、116與^等顧 =圖案化，可採用相似於前述第3_4圖與第卜7圖之箱 U刻程序而部份移除了區域A、B與 ::宰導::Γ116與106,進而於介電二 圖f化之導電層12G，、116,與讓，等圖案化膜層。 Μ參照第9圖’顯示了如第8圖所示結構之上視情形， 201124006 =J案化之導電層12G’、116’與1G6,便構成了設置且 =區域a、b與⑶介電層刚之—部上的訊號導線。 導線於區域a、b、c内具林同之膜層結構與 匕度，:、中於區域A内部份160係由圖案化之導電層12〇，、 所構成，於區❹内之部份則由圖案化之導電 i電芦：：，以及於區域C内之部份150則由圖案化之 導電層116與1G6,所構成。然而，參照第9圖所示之情形 可得^ ’設置與延伸於區域A、B與c之介電I謂上之 訊號V線之各部份則具有相同之線寬Wi。 請參照第10圖，接著於區域B/c内之介電層謂 與導電層116,與1()6，之上形成—介電層m，以及於區域 C内之介電層之另一表面1〇4之μ卜主0 & , 力衣囬1υ4之上（凊見第1圖）形成介電層 ’I電層17G係為如綠漆之—種防坪材料所組成，其係 作為抗焊絕緣層之用，以避免區域内之構成訊號導 線之導電層綱，與H6,遭受線路氧化與焊接短路等問題。 而介電層⑽則可藉由黏著層172的設置而附著於區域c 内之介電層100的表面104上以作為一補強板之用。黏著 層172與介電層180係為如紙質酚醛樹脂(paper卩以⑽以 resin)、複合環氧樹脂（comP〇site epoxy)、聚亞醯胺樹脂 (polyimide resin)或含浸玻纖布(prepreg)等具黏著性之介電 材料所組成，而介電層180係為如玻璃纖維、紙質酚醛樹 月曰（paper phenolic resin)、複合環氧樹脂（composite epoxy)、 聚亞醯胺樹脂（polyimide resin)或含浸玻纖布（prepreg) 等絕緣材料所組成，其厚度可適當調整以補強區域C内板 件的機械強度。 201124006 請參照第11圖，接著於區域A内之介電層100之表面 1〇2(見於第1圖）與導電層120,之上形成一介電層185以及 於區域A内之導電層108之上形成一介電層195，以及分 別於介電層185與195的表面選擇性地形成之一導電層 187/197以及一介電層189/199。在此，介電層185/195係 作為一增層板之用，其可包括如紙質酚醛樹脂（paper phenolic resin)、複合環氧樹脂(composite epoxy)、聚益醢 胺樹脂(polyimide resin)或玻璃纖維(glass fiber)等絕緣材 料，而其厚度可適當調整以補強區域A内板件的機械強度 並提供額外導電層187/197的設置。導電層187/197則為如 一超薄之金屬層或或非金屬導體層，具有厚度T5與T6,而 介電層100之材質如紙質酚醛樹脂(paper phenolic resin)、 複合環氧樹脂（composite epoxy)、聚亞醯胺樹脂(P〇lyimide resin)或玻璃纖維（glass fiber)等絕緣材料。於介電層 185/195之上形成導電層187與197之方法例如為濺鍍 (sputtering)、壓合(iaminate)或塗佈（coating)等製程。介電 層189/199係為如綠漆之一種防焊材料所組成’其係作為 抗焊絕緣層之用，以避免區域A内之構成訊號導線之導電 層106’、116,與120’以及導電層187/197等膜層遭受線路 氧化與焊接短路等問題。 如第11圖所示，顯示了依據本發明一實施例之可調整 特性阻抗之印刷電路基板，包括： 一第一介電層（介電層1〇〇)，其上定義有相鄰之一第一 區（區域A或〇與一第二區（區域B)，其中該第一介電層具 201124006 • 有相對之第一表面（表面102)與第二表面（表面104); 一第 • —導電層（導電層106，）’設置於該第一介電層之該第一區 與該第—區内之該第一表面的一部上；一第二導電層（導電 層116’），設置於該第一介電層之該第一區内之該第一導電 層之上，其中該第二導電層與該第一導電層具有相同線寬 並構成了 一訊號導線；以及一第二介電層（185或180)，設 置於該第一介電層之該第一區（區域A)内之該第二導電層 之上或該第一介電層之該第一區（區域c)内之該第二表面 • 之上。於其他實施例中，可更於該第二導電層（導電層116，) 之上依序設置一第三導電層（導電層120，)與一第三介電層 (w電層185)，而該第三導電層、該第二導電層與該第一導 電層具有相同線寬並構成了該訊號導線，而該第二介電層 係设置於該第一介電層之該第一部（區域A)内之該第二表 面之上。於其他實施例中，該第一介電層之該第一區（區域 或）例如為硬板元件區（區域A)或一軟板元件區（區域 該第-介電層之該第二區（區域B)例如為—轉板零折 於如第11®所示之本發_印刷f路基_實施情形 中’主要利㈣定訊號導線之線寬條件下藉由改變位於不 =區域内之訊號導線(至少由導電層1〇6，與116，所組成)的 =度而調整於區域A/c與區域B内等不同區域内之訊 a:::特:生阻抗，藉以使得設置於上述印刷電路基板 1、及C β舰軸之訊料線之各部份 表現相近，使之不受到各區域内之介電層膜層數 1不同或各區域内使用之介電層材料的介電常數的不同^ 13 201124006 影響。 於上述貫施例中，位於各區域A、B與c内訊號導線 之各部分的厚度則可視各區域A、B與c内之介電層之數 里及/或介電層使用材料之介電常數並參照下述公式（1)進 行凋整而並不以上述實施例内之實施情形而加以限定本發 明。 717+1·4 丨料‘1 (1) 其中zQ為訊號導線之各部份之特性阻抗值、&為介電 ”介電層185、195、170、172與180及其組合)之 ”電㊉數、1^為導電層（例如為導電層12〇，、116，與1 及其組合)之厚度、w為導電層之線徑、h為導電層到參考 層(例如為介電層185、195、170、172與180等膜層)之介 電層厚度。The width of the 冉 line is Φ / J2L so that the characteristic impedance can remain unchanged when the electronic signal is transmitted between the signal wires. Etc., the signal transmission of the squeezing frequency, the two components or the end points of the same speed and impedance matching design to reduce the impedance mismatch caused by the good J shot will form a noise and is reduced In the production of the inland=region=type printed circuit board and the package substrate which are transmitted between them, the large-sized printed electric λ in the different regions in the range of the components required in the field is not required, and the For the cutting process, such as drilling, see the implementation of the printed circuit board process, so the number and thickness of the dielectric layer in different areas on the large-scale printed substrate, and the dielectric constant of the material There is a difference. In @: large printed circuit board and different areas on the package substrate, the number of layers, the thickness of the germanium differs from the dielectric material used. 'The signal has the same line width in the same area. The wire will be affected by the dielectric properties of the adjacent dielectric layer of 24201124006', resulting in a large number of printed-circuit boards and signal conductor segments in different areas on the package substrate. SUMMARY OF THE INVENTION In view of the above, the present invention provides a printed circuit board that utilizes the thickness or width of a signal conductor to adjust the characteristic impedance of signal conductors in different regions, thereby overcoming the printed circuit. The present invention provides a printed circuit board having an adjustable characteristic impedance, comprising: a first dielectric layer on which a phase is defined. a first region and a second region, wherein the first dielectric layer has a first surface and a second surface; a first conductive layer disposed in the first region of the first dielectric layer a portion of the first surface of the second region; a second conductive layer disposed over the first conductive layer of the first region of the first dielectric layer, wherein the second conductive layer The layer has the same line width as the first conductive layer and constitutes a signal wire; and a second dielectric layer is disposed on the second conductive layer of the first region of the first dielectric layer or The first dielectric layer According to another embodiment, the present invention provides an adjustable printed circuit substrate comprising: ^ ^ a first dielectric layer on which a first one is defined a second region and a third region, wherein the first dielectric layer has a first surface = a second surface; a first conductive layer is disposed on the second dielectric layer of the first dielectric layer 201124006 And a second conductive layer on the first surface of the second region and the third region, the first conductive layer disposed in the first region and the third region of the first dielectric layer Above, wherein the second conductive layer has the same line width as the fourth; a third conductive layer and a second dielectric layer, the second conductive region in the first region of the first dielectric layer The third conductive layer and the second conductive layer and the first guide, and the third conductive layer, the second conductive layer and the first wire, and a third dielectric layer and a first layer A fourth dielectric layer is disposed over the first surface of the first dielectric layer. / The third basis of the third section of the third embodiment - the embodiment of the present invention provides an adjustable printed circuit board comprising: a sub-! - raw impedance - the first - dielectric layer 'on which is defined adjacent a first region of the second dielectric layer = a dielectric layer having a first surface and a surface: a surface of the first dielectric layer and the second portion, wherein the first conductive portion The layer includes: - a surface portion of the second region of the first dielectric layer having a fixed one of the first dielectric layers, disposed at the second line width, wherein the second line And having a fixed second disposed on the first region of the first dielectric layer: = two above and physically contacting the first segment and the third; the second segment having a non-fixed state: The first line width is not greater than the second line width: the second layer is disposed in the first region of the first dielectric layer = 4;;: 201124006 partially covers the first conductive layer The third segment and the first segment of the finish-conducting layer are placed over the second surface of the first via. According to another embodiment, the present invention provides an adjustable printed circuit board comprising: & a first dielectric layer having adjacent regions defined thereon, and a third region, wherein The first dielectric layer has a second surface opposite to the first sand; a first conductive layer is disposed in the second region of the first dielectric layer, the first region of the second region and the first region On a portion of the surface, the first conductive layer includes: a first segment disposed on the first surface of the first dielectric layer 'having a fixed-first-line width; - and a & The first 兮 of the second dielectric region of the first dielectric layer has a second second line width, wherein the second line width is greater than a width, and a third portion is disposed at the first a dielectric layer having a fixed - third line width above the first surface of the dielectric layer, the first line width being less than the second line width and equal or not equal to the first line ^: fourth a segment portion disposed on the first region of the first dielectric layer and above the first surface of the first: and in physical contact: r: r fixed by a fourth line width, wherein the fourth ^: two a line; and not greater than the second line width; and a fifth segment portion, the second portion of the real layer and the first surface of the third region are over the fifth line The third segment has a non-fixed one of the second turns, the fifth line width is not less than the third line width, and is not larger than the first conductive layer and a second dielectric layer And over the first conductive layer in the first region of the first portion, partially covering the fourth portion of the first conductive layer of 201124006 and completely covering the first portion; and a third dielectric layer And disposed on the second surface of the third region of the first dielectric layer. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. [Embodiment] Hereinafter, the production of a printed circuit board having an adjustable characteristic impedance according to an embodiment of the present invention will be described in detail with reference to Figs. It is to be noted that these drawings are simplified schematic diagrams to emphasize the features of the present invention, and therefore the dimensions of the elements in the drawings are not drawn to the actual scale. Embodiments of the invention may also include elements not shown in the figures. First, a dielectric layer 1 适用 suitable for printed circuit substrate fabrication is provided having opposite surfaces 102, 104, and three adjacent regions A, B and C are generally defined above the dielectric layer 100. . A conductive layer 106 is formed over the surface 102 of the dielectric layer 100 in regions A, B, and C, and a conductive layer 108 is formed over the surface 104 in region A. Here, the conductive layers 106 and 108 are, for example, an ultra-thin metal layer or a non-metal conductor layer, the thickness of the conductive layer 106 is shown as T!, and the thickness of the conductive layer 108 is shown as T2, and the material of the dielectric layer 100 is as Paper phenolic resin, composite epoxy, poly 201124006 polyimide resin or glass fiber. The method of forming the conductive layers 106 and 108 over the dielectric layer 100 is, for example, sputtering, laminating, or coating, etc. See FIG. 2, forming over the conductive layer 106. A photoresist layer no, the photoresist layer 110 is, for example, a dry film photoresist that is adhered to the conductive layer 106 under a suitable temperature and pressure. Referring to Figure 3, a lithography process 114 is then performed to expose the photoresist layer 110. Here, the lithography program 114 uses a reticle ι 2 having a plurality of opaque regions 112a and at least a transparent region U2b, wherein the light transmissive region 112b is substantially aligned with the region B' and the occlusion is generally aligned with A and After the lithography process 114 is performed, _Bj^light=overexposure becomes the exposed implant layer (10), and leaves the unexposed photoresist layer 11〇a in the region AW. Baguang's photo-resist layer ma and exposed areas are not visible), removed without exposure to a deposition process (not shown = and two conductive layer (10) process, in the area of eight and inside. An internal plating process or - chemical bond The electric layer 116 is made of copper, which is a commonly used material. The metal conductive material, which is in turn with the conductive layer 1 〇 6 κ in the region B, the thickness T3 of the conductive layer 116 is preferably 6 The exposed light-resistance reed 〗; (: the same, to provide the subsequent process to perform - flat surface. ^ layer 11% phase please refer to Figure 5, in the conductive > gt; . ^ ^ 1 ΛΟ θ 116 and the exposed light A resistive layer 118' is formed on the resist layer ii〇b to prevent the temperature and pressure from being appropriate; six '*', - dry film photoresist, and 岔S attached to the conductive layer 116 and 201124006 Above the exposed photoresist layer 11 〇 b. Please refer to FIG. 6 and then perform a lithography process 122 to expose the photoresist layer 118. Here, the lithography program 122 uses a light-shielding region 12 〇 & a light-shielding region 120b, wherein the light-transmitting region 120b is substantially aligned with the regions B and C, and the light-shielding region 120a is substantially aligned Region A. After the ghosting process 122 is performed, the photoresist layer 118 in regions B and C is exposed to become the exposed photoresist layer 118b, leaving an unexposed photoresist layer 118a in region a. Referring to Figure 7, a development process (not shown) is performed to remove the unexposed photoresist layer 118a and expose the conductive layer 116 in the region A. Next, a deposition process (not shown) is performed, for example An electroplating process or an electroless plating process is performed to form a conductive layer 12〇 in the region A, and the material f may be copper, indium, nickel, gold metal or other non-metallic conductive material, wherein copper is used more frequently. Here, the thickness τ4 of the conductive layer 12G is preferably the same as the exposed photoresist layer on the conductive layer 116 in the regions b and C, for performing a flat surface on the subsequent process. , performing a stripping process (not shown) to strip the exposed photoresist layer in the region fC and (10), and exposing the conductive layer ι 6 (see Figure 7) and the region c in the soil. Conductive layer ΐ6ΐ=Fig. 7). Then, for these conductive layers (10), 116 and ^, etc. The regions A, B and:: the salvage:: Γ 116 and 106, and the conductive layer of the dielectric digraph can be partially removed by using a box U-etching procedure similar to the above-mentioned 3_4 and 7th. 12G, 116, and let, etc. patterned film layer. Μ Refer to Figure 9 for the top view of the structure shown in Figure 8, 201124006 = J case of conductive layers 12G', 116' and 1G6, It constitutes the signal conductors on the parts of the dielectric layers that are set and = areas a, b and (3). The wires have the same film structure and twist in the areas a, b, c, and are in the area A. The inner portion 160 is composed of a patterned conductive layer 12, and the portion in the region is patterned by the conductive i-ring::, and the portion 150 in the region C is patterned. The conductive layer 116 and 1G6 are formed. However, referring to the case shown in Fig. 9, it is possible to set and extend the portions of the signal V line extending over the dielectric regions I of the regions A, B and c to have the same line width Wi. Please refer to FIG. 10, and then the dielectric layer in the region B/c and the conductive layer 116, and 1 () 6, on the dielectric layer m, and the dielectric layer in the region C The surface of the surface 1 〇 4 卜 main 0 &, the power back to 1 υ 4 (see Figure 1) to form a dielectric layer 'I electrical layer 17G is a green paint - a kind of anti-flat material, its system As a solder resist layer, it avoids the problem of the conductive layer of the signal wires in the region, and H6, which suffers from line oxidation and soldering short circuit. The dielectric layer (10) can be attached to the surface 104 of the dielectric layer 100 in the region c by the adhesive layer 172 to serve as a reinforcing plate. The adhesive layer 172 and the dielectric layer 180 are, for example, paper phenolic resin (paper 卩 (10) as resin), composite epoxy resin (comP〇site epoxy), polyimide resin or impregnated glass cloth (prepreg) The dielectric layer 180 is composed of a glass dielectric material such as glass fiber, paper phenolic resin, composite epoxy, polyimide resin (polyimide). The resin is composed of an insulating material such as impregnated fiberglass (prepreg), and the thickness thereof can be appropriately adjusted to reinforce the mechanical strength of the panel in the region C. 201124006 Referring to FIG. 11, a dielectric layer 185 and a conductive layer 108 in the region A are formed on the surface 1〇2 (see FIG. 1) of the dielectric layer 100 in the region A and the conductive layer 120. A dielectric layer 195 is formed thereon, and a conductive layer 187/197 and a dielectric layer 189/199 are selectively formed on the surfaces of the dielectric layers 185 and 195, respectively. Here, the dielectric layer 185/195 is used as a build-up board, which may include, for example, a paper phenolic resin, a composite epoxy, a polyimide resin, or An insulating material such as glass fiber, and the thickness thereof can be appropriately adjusted to reinforce the mechanical strength of the panel in the region A and provide an additional conductive layer 187/197. The conductive layer 187/197 is such as an ultra-thin metal layer or a non-metal conductor layer having thicknesses T5 and T6, and the dielectric layer 100 is made of a paper phenolic resin or a composite epoxy resin. ), an insulating material such as a P〇lyimide resin or a glass fiber. The method of forming the conductive layers 187 and 197 over the dielectric layer 185/195 is, for example, a sputtering process, an iaminate or a coating process. The dielectric layer 189/199 is composed of a solder resist material such as green paint, which is used as a solder resist layer to avoid the conductive layers 106', 116, and 120' constituting the signal wires in the region A and The conductive layer 187/197 and the like are subject to problems such as line oxidation and solder short circuit. As shown in FIG. 11, a printed circuit board having an adjustable characteristic impedance according to an embodiment of the present invention includes: a first dielectric layer (dielectric layer 1) on which one of adjacent ones is defined a first zone (Zone A or 〇 and a second zone (Zone B), wherein the first dielectric layer has 201124006 • has a first surface (surface 102) and a second surface (surface 104); a conductive layer (conductive layer 106) disposed on a portion of the first region of the first dielectric layer and the first surface of the first region; a second conductive layer (conductive layer 116') And disposed on the first conductive layer in the first region of the first dielectric layer, wherein the second conductive layer and the first conductive layer have the same line width and constitute a signal wire; a second dielectric layer (185 or 180) disposed on the second conductive layer in the first region (region A) of the first dielectric layer or the first region (region) of the first dielectric layer c) above the second surface. In other embodiments, the second conductive layer (conductive layer 116,) may be sequentially disposed. a third conductive layer (conductive layer 120) and a third dielectric layer (w electrical layer 185), and the third conductive layer, the second conductive layer and the first conductive layer have the same line width and constitute the a signal conductor, and the second dielectric layer is disposed on the second surface of the first portion (region A) of the first dielectric layer. In other embodiments, the first dielectric layer The first region (region or) is, for example, a hard plate component region (region A) or a soft plate component region (the region of the second dielectric region (region B) is, for example, a transfer plate zero-folded as in The present invention shown in the 11th®_printing f subgrade_in the case of the main advantage (4), the signal width of the signal conductor is changed by changing the signal conductor located in the non-region (at least by the conductive layer 1〇6, and 116) The degree of the composition is adjusted in the different areas such as the area A/c and the area B. a::: special: the impedance is generated, so that the printed circuit board 1 and the C β ship axis are arranged. The parts of the feed line behave similarly so that they are not subject to the dielectric constant of the dielectric layer material used in each region or the dielectric constant of the dielectric layer material used in each region. Different ^ 13 201124006 effect. In the above embodiments, the thickness of each part of the signal wires located in each of the areas A, B and c can be regarded as the number of dielectric layers in each of the areas A, B and c and/or The electric layer uses the dielectric constant of the material and is smeared with reference to the following formula (1) without limiting the present invention by the implementation of the above embodiment. 717+1·4 ''1 (1) where zQ The characteristic impedance value of each part of the signal wire, & is the dielectric "dielectric layer 185, 195, 170, 172 and 180 and combinations thereof", the electrical number, 1 ^ is a conductive layer (for example, a conductive layer) 12〇, 116, and 1 and combinations thereof), w is the wire diameter of the conductive layer, and h is the conductive layer to the reference layer (for example, the dielectric layers 185, 195, 170, 172, and 180) Dielectric layer thickness.
除了前述之於固定訊號導線之線寬條件下藉由改變 於不同區域内之訊號導線的厚度而調整於不同區域内之 號導線部分之間特性阻抗差異，使得設置於印刷電路基 =之不同區域A、B及C内之訊號導線之各部份的特性 ，表現相近的本發明之方法之外，本發明亦提供了採用 疋訊號導線之厚度條件下藉由改變不同區域内之訊號導 之線寬而調整於不龍域内之訊號導線部分之間特性阻 差異之方法，使得設置於印刷電路基板内之不同區域A、 14 201124006 * 及c内之訊號導線之各部份的特性阻抗表現相近。 δ青參照第12-16圖以詳細說明本發明另一實施.例之可 調整特性阻抗之印刷電路基板的製作。此處須注意的是， 該些圖式均為簡化之示意圖，以強調本發明之特徵，因此 圖中之元件尺寸並非完全依實際比例緣製。且本發明之實 施例也可能包含圖中未顯示之元件 _ 明參照第12圖，首先提供適用於印刷電路基板製作之 一介電層200，其具有相對之兩個表面2〇2、2〇4，而介電 層200之上則大體定義有三個相鄰之區域Α、β與c。於 區域A、Β與C内之介電層200的表面2〇2之上則坦覆地 形成有一導電層206，而於區域A内之表面2〇4之上則形 成有一導電層208。請參照第13圖，顯示了如第12圖所 示結構之上視情形。在此，導電層2〇6與2〇8例如為一超 薄之金屬層或非金屬導體層，導電層2〇6之厚度顯示為 # T7’而導電層208之厚度則顯示為丁8，而介電層2〇〇之材 質如紙質酚酸樹脂（paper phen〇lic resin)、複合環氧樹脂 (composite epoxy)、聚亞醯胺樹脂（p〇iyimide resin)或玻璃纖 維(glass fiber)等絕緣材料。於介電層1〇〇之上形成導電層 106與108之方法例如為濺鍍（sputtering)、壓合（iaminate) 或塗佈（coating)等製程。 請參照第14圖，接著施行一圖案化程序250以圖案化 位於介電層200上之導電層206(見於第12圖），所使用之 圖案化程序250可包括相似於前述第3-4圖與第6-7圖之 15 201124006 微影與蝕刻程序，因而部份移除了區域A、B與C内之介 電層200上之導電層2〇6，進而於介電層2〇〇上形成了由 五個經圖案化之|電段部206a〜2〇6e所構成之一訊號導 線。第15圖則顯示了如第14所示結構之上視情形。 如第14與15圖所示，在此訊號導線包括了設置於介 電層200之區域a内之表面202之上的導電段部2〇6a、設 置於介電層200之區域b内之表面202之上之導電段部 206b °又置於”電層200之區域c内之表面202之上之導 電段部206c、設置並延伸於介電層2〇〇之區域八與B内之 表面202之上之導電段部2〇6c以及設置並延伸於介電層 200之區域B與C内之表面202之上之導電段部2〇6e。在 此’導電段部206a具有固定之一線寬My而導電段部2〇讣 具有固定之-第二線寬w3，且此第二線$ %大於第一段 部206a之第一線寬貿2,以及導電段部2〇6c具有固定之一 第三線寬W4,且該第三線寬Μ*小於該第二線寬W3並相 等或不相等於第一線寬W”另外，設置於區域A與B内 表面202上之導電段部2〇6d則實體接觸第一段部汕如與 第二段部2〇6b，具有非固定之一第四線寬，其不小於第一 線覓W2且不大於該第二線寬W3，以及設置於區域B與c 内表面202上之導電段部206e則實體接觸第二段部2〇6b 與第三段部206c，具有非固定之一第五線寬，其不大於第 二線寬W3且不小於該第三線％ %。於其他實施例中，介 電層200之區域A或c例如為一硬板元件區或一軟板元件 區，而電層200之區域b例如為一轉板彎折區。 請參照第16圖，接著可採用相同或相似於第1〇_u圖 201124006 所不製造流程的實施，於區域A、B、c等各區域内形成如 •介電層 170、180、185、189、195 與 199，以及導電層 187、 197，以及黏著層172 4相同膜層。於本實施例中，上述膜 層亦扮演了與如第10-11圖所示結構中之相同功能，故於 此不在詳細描述其各別功能。 如第16圖所示，顯示了依據本發明另一實施例之可調 整特性阻抗之印刷電路基板，包括： 一第一介電層（介電層200)，其上定義有相鄰之一第一 區（區域A/C)與一第二區（區域B)，其中該第一介電層具有 相對之第一表面（表面202)與第二表面（表面2〇4); 一第一 導電層（導電層206a〜e所組成），設置於該第一介電層之該 第區與該第二區内之該第一表面的一部上，其中該第一 導電層包括：-第-段部（導電段部禀a/施c)，設置於該 第了介電層之該第-區内之該第—表面之上，具有固定之 一第-線寬(線寬W2); -第二段部（導電段部2_)，設置 =該第-介電層之該第二區内之該第—表面之上，具有固 定之-第二線寬(線寬W3) ’其中該第二線寬大於該第一線 寬；-第三段部（導電段部2〇6c)設置於該第一介電層之該 第-區内之該第-表面之上，具有—固定之—第三線寬 (W4) ’其中第三線寬小於第二線寬且相等或不相等於第一 線寬；以及-第四段部（導電段部·/2 一介電層之該第-區與該第二區内之該第—表面 體接觸該第-段部與該第二段部以及第二段料第三段 部，其中該第四段部具有非固定之一第四線寬及第五線 17 201124006 寬’且該第四線寬不小於該第一線寬（線寬wo及不大於該 第二線寬(線寬w3)，而該第五線寬不大於該第二線寬（線寬 wo及相等或不相等於該第一線寬（線寬Wi);以及一第二 介電層（介電層185/180)，設置於該第一介電層之該第一區 内之該第一導電層之上以部份覆蓋該第一導電層之該第四 段部以及完全覆蓋第一導電層之該第一段部，或設置於該 第一介電層之該第一區之該第二表面之上。 於其他實施例中，更包括依序設置於該第一介電層之 該第一區（區域A)内之該第二表面上之一第三導電層（導電 層208)與一第三介電層（介電層195)。 於其他實施例中，該第一介電層之該第一區（區域A或 C)例如為一硬板元件區（區域A)或一軟板元件區（區域c)， 而該第”電層之該第二區（區域B)例如為一轉板彎折區。 於如第16圖所示之本發明的印刷電路基板的實施情形 中主要利用固定訊號導線之厚度條件下藉由改變位於不 同區域，之訊號導線（至少由導電段部2〇6a/c與2〇6b以及 2〇6d/e等導電段部所組成）的線寬而調整於區域與區域 B曰内等不同區域内之訊號導線部分之間特性阻抗，藉以使 得又置於上述印刷電路基板内之區域A、^及c等多個區 域内之訊號導線之各部份的特性阻抗表現相近，使之不受 到各區域内之介電層膜層數量不同或各區域内使用之介電 層材料的介電常數的不同而影響。 201124006 於上述實施例中，位於各區域A、B與C内構成訊號 導線之各導電段部的線寬則可視各區域A、B與C内之介 電層之數量及/或介電層使用材料之介電常數並參照前述 公式（1)進行調整而並不以上述實施例内之實施情形而加 以限定本發明。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。In addition to the above-described line width of the fixed signal conductor, the difference in characteristic impedance between the portions of the conductors in different regions is changed by changing the thickness of the signal conductors in different regions, so that they are disposed in different regions of the printed circuit base. In addition to the characteristics of the various portions of the signal conductors in A, B and C, which are similar in performance, the present invention also provides for the use of varying the thickness of the signal conductors by varying the thickness of the signal lines in different regions. The method of widening the difference in characteristic resistance between the signal conductor portions in the non-long field makes the characteristic impedances of the portions of the signal wires disposed in the different regions A, 14 201124006* and c in the printed circuit board be similar. Δ青 Referring to Figures 12-16, the fabrication of a printed circuit board with adjustable characteristic impedance can be further described in detail in another embodiment of the present invention. It is to be noted that the drawings are simplified diagrams to emphasize the features of the present invention, and therefore the dimensions of the elements in the drawings are not in the true proportion. Furthermore, embodiments of the present invention may also include components not shown in the figures. Referring to FIG. 12, a dielectric layer 200 suitable for use in a printed circuit substrate is first provided, having opposite surfaces 2, 2, 2 〇. 4, and above the dielectric layer 200 is generally defined by three adjacent regions Α, β and c. A conductive layer 206 is formed over the surface 2〇2 of the dielectric layer 200 in the regions A, Β and C, and a conductive layer 208 is formed over the surface 2〇4 in the region A. Referring to Fig. 13, the top view of the structure as shown in Fig. 12 is shown. Here, the conductive layers 2〇6 and 2〇8 are, for example, an ultra-thin metal layer or a non-metal conductor layer, the thickness of the conductive layer 2〇6 is shown as #T7', and the thickness of the conductive layer 208 is shown as D8. The material of the dielectric layer 2 such as paper phen〇lic resin, composite epoxy, p〇iyimide resin or glass fiber, etc. Insulation Materials. The method of forming the conductive layers 106 and 108 over the dielectric layer 1 is, for example, a sputtering process, an iaminate or a coating process. Referring to FIG. 14, a patterning process 250 is then performed to pattern the conductive layer 206 on the dielectric layer 200 (see FIG. 12). The patterning process 250 used may include similar to the aforementioned 3-4. And the 201124006 lithography and etching process of Figures 6-7, thus partially removing the conductive layer 2〇6 on the dielectric layer 200 in the regions A, B and C, and then on the dielectric layer 2 A signal wire composed of five patterned electric portion sections 206a to 2〇6e is formed. Figure 15 shows the top view of the structure shown in Figure 14. As shown in FIGS. 14 and 15, the signal conductor includes a conductive segment portion 2〇6a disposed on the surface 202 in the region a of the dielectric layer 200, and a surface disposed in the region b of the dielectric layer 200. The conductive segment portion 206b above the 202 is again placed on the conductive segment portion 206c above the surface 202 in the region c of the electrical layer 200, and the surface 202 disposed in the region 8 of the dielectric layer 2 and B The conductive segment portion 2〇6c above and the conductive segment portion 2〇6e disposed over the surface 202 in the regions B and C of the dielectric layer 200. Here, the conductive segment portion 206a has a fixed line width My The conductive segment portion 2 has a fixed second line width w3, and the second line $% is larger than the first line width 2 of the first segment portion 206a, and the conductive segment portion 2〇6c has a fixed one. The three line width W4, and the third line width Μ* is smaller than the second line width W3 and equal or not equal to the first line width W". Further, the conductive segment portions 2〇6d disposed on the inner surfaces 202 of the regions A and B are The physical contact first segment, for example, and the second segment 2〇6b, has a non-fixed one of the fourth line widths, which is not less than the first turn W2 and not greater than the second line width W3, And the conductive segment portion 206e disposed on the inner surface 202 of the regions B and c physically contacts the second segment portion 2〇6b and the third segment portion 206c, and has a non-fixed one of the fifth line widths, which is not greater than the second line width W3 is not less than the third line %%. In other embodiments, the region A or c of the dielectric layer 200 is, for example, a hard plate component region or a soft board component region, and the region b of the electrical layer 200 is, for example, a turn plate bending region. Please refer to FIG. 16 , and then the same or similar to the implementation process of the first manufacturing process of No. 201124006 can be used to form dielectric layers 170 , 180 , 185 in the regions A , B , and c , 189, 195 and 199, and the conductive layers 187, 197, and the adhesive layer 172 4 are the same film layer. In the present embodiment, the above-mentioned film layer also functions in the same manner as in the structure shown in Figs. 10-11, and thus its respective functions will not be described in detail. As shown in FIG. 16, a printed circuit board having an adjustable characteristic impedance according to another embodiment of the present invention includes: a first dielectric layer (dielectric layer 200) on which a adjacent one is defined. a region (region A/C) and a second region (region B), wherein the first dielectric layer has an opposite first surface (surface 202) and a second surface (surface 2〇4); a first conductive a layer (consisting of the conductive layers 206a-e) disposed on the first region of the first dielectric layer and a portion of the first surface of the second region, wherein the first conductive layer comprises: - a segment portion (conductive segment portion 禀a / c) disposed on the first surface of the first region of the first dielectric layer, having a fixed first-line width (line width W2); a second segment (conductive segment portion 2_), disposed on the first surface of the second region of the first dielectric layer, having a fixed - second line width (line width W3) The second line width is greater than the first line width; the third length portion (the conductive portion portion 2〇6c) is disposed on the first surface of the first dielectric region of the first dielectric layer, and has a fixed- Third line width (W4) ' The middle third line width is smaller than the second line width and equal or not equal to the first line width; and - the fourth segment portion (the conductive portion portion / / the second region of the dielectric layer and the second region) The first surface member contacts the first segment portion and the second segment portion and the second segment third segment portion, wherein the fourth segment portion has a non-fixed one of the fourth line width and the fifth line 17 201124006 width 'and The fourth line width is not less than the first line width (the line width wo and not more than the second line width (line width w3), and the fifth line width is not greater than the second line width (the line width wo and the equal or Not equal to the first line width (line width Wi); and a second dielectric layer (dielectric layer 185/180) disposed on the first conductive layer in the first region of the first dielectric layer And partially covering the fourth segment of the first conductive layer and the first segment completely covering the first conductive layer, or the second surface of the first region of the first dielectric layer In other embodiments, further comprising a third conductive layer (conductive layer 208) and one of the second surfaces disposed in the first region (region A) of the first dielectric layer The third dielectric layer (dielectric layer 195). In other embodiments, the first region (region A or C) of the first dielectric layer is, for example, a hard board component region (region A) or a soft board component a region (region c), and the second region (region B) of the first "electric layer" is, for example, a turn plate bending region. The main use of the printed circuit board of the present invention as shown in Fig. 16 is mainly utilized. The thickness of the fixed signal wire is adjusted by changing the line width of the signal wires located in different regions (at least consisting of conductive segments such as conductive segments 2〇6a/c and 2〇6b and 2〇6d/e) The characteristic impedance between the signal conductor portions in different regions such as the region and the region B, so that the portions of the signal wires in the regions A, ^, and c in the printed circuit board are placed The characteristic impedances are similar, so that they are not affected by the difference in the number of dielectric layers in each region or the dielectric constant of the dielectric layer material used in each region. In the above embodiment, the line widths of the conductive segments forming the signal wires in the respective regions A, B and C can be determined by the number of dielectric layers in each of the regions A, B and C and/or the dielectric layer. The dielectric constant of the material is adjusted with reference to the above formula (1) and is not limited to the embodiment of the above embodiment. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.
19 201124006 【圖式簡單說明】 第1 8、UM1圖為-系列剖面圖，顯示了依據本發明 -實施例之可調整特性阻抗之印刷電路基板的製作； ' 第9圖為一不意圖’顯示了如第8圖所示結構之上 情形； 第12 14、16圖為一系列剖面圖’顯示了依據本發明 另一實施例之可調整特性阻抗之印刷電路基板的製作；以 及 第15圖為一示意圖’顯示了如第14圖所示結構之上 視情形。 φ 【主要元件符號說明】 100、200〜介電層； 102、104、202、204〜介電層之表面； 106、116、120〜導電層； 106’、116’、120,〜經圖案化之導電層； 108〜導電層； 110、118〜光阻層； 鲁 110a、118a〜未經曝光之光阻層； 110b、118b〜經曝光之光阻層； 112、120〜光罩； 112a、120a〜遮光區； 112b、120b〜透光區； 114、122〜微影程序； 15 0〜訊5虎導線之-'部份； 20 201124006 160〜訊號導線之一部份； 170〜介電層； 172〜黏著層； 180、185、189、195、199〜介電層； 187、197〜導電層； 200〜介電層； 202、204〜介電層之表面； 206、208〜導電層； • 206a、206b、206c、206d、206e〜訊號導線之導電段部 A、B、C〜區域， 丁广導電層106之厚度； T2〜導電層108之厚度； Τ3〜導電層116之厚度； Τ4〜導電層120之厚度； Τ5〜導電層187之厚度； Τ6〜導電層197之厚度； _ Τ7〜導電層202之厚度； Τ8〜導電層208之厚度； 〜訊號導線之線寬； W2、W3、W4〜訊號導線之導電段部之線寬。19 201124006 [Simplified description of the drawings] The first UM1 is a series of sectional views showing the fabrication of a printed circuit board with adjustable characteristic impedance according to the present invention - 'Fig. 9 is an unintended 'display Figure 12 is a series of cross-sectional views showing the fabrication of a printed circuit board having an adjustable characteristic impedance in accordance with another embodiment of the present invention; and Figure 15 is a A schematic diagram shows the top view of the structure as shown in Fig. 14. Φ [Description of main component symbols] 100, 200~ dielectric layer; 102, 104, 202, 204~ surface of dielectric layer; 106, 116, 120~ conductive layer; 106', 116', 120, ~ patterned Conductive layer; 108~ conductive layer; 110, 118~ photoresist layer; Lu 110a, 118a~ unexposed photoresist layer; 110b, 118b~ exposed photoresist layer; 112, 120~ reticle; 112a, 120a~ opaque area; 112b, 120b~ light transmission area; 114, 122~ lithography program; 15 0~5 5 wire conductor - 'part; 20 201124006 160~ one part of signal wire; 170~ dielectric layer 172~Adhesive layer; 180, 185, 189, 195, 199~ dielectric layer; 187, 197~ conductive layer; 200~ dielectric layer; 202, 204~ dielectric layer surface; 206, 208~ conductive layer; • 206a, 206b, 206c, 206d, 206e~ the conductive segments A, B, C~ regions of the signal wires, the thickness of the D-poly conductive layer 106; the thickness of the T2~ conductive layer 108; the thickness of the Τ3~ conductive layer 116; Τ4 ~ thickness of conductive layer 120; thickness of Τ5~ conductive layer 187; thickness of Τ6~ conductive layer 197; thickness of _ Τ7~ conductive layer 202; Τ8 The thickness of the conductive layer 208; width of the signal wires ~; W2, W3, the line width of the conductive signal wires W4~ of segments.