TWI393493B - Printed circuit substrate with adjustable characteristic impendance - Google Patents

Description

Printed circuit substrate with adjustable characteristic impedance

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a printed circuit board structure, and more particularly to a printed circuit board that utilizes the thickness or width of a signal conductor to adjust the characteristic impedance.

On a large printed circuit board and a package substrate, a signal wire is used to electrically connect two different components or end points, and the line widths thereof are required to be uniform so that the characteristic impedance of the signal wire when the electronic signal is transmitted between the signal wires (Characteristic impedance) can remain unchanged. Especially in high-speed and high-frequency signal transmission, the two components or the end point need to be designed with good impedance matching to reduce the reflection caused by impedance mismatch. Such reflections will create noise and reduce the quality of the electronic signals transmitted between them.

However, in the production of large-sized printed circuit boards and package substrates, it is necessary to perform common printing such as drilling or planar cutting for large printed circuit boards and package substrates in different areas in response to the difference in the arrangement of components in different areas. The implementation of the board process results in a difference in the number of layers of the dielectric layer, the thickness of the dielectric layer in different areas on the large printed circuit board and the package substrate, and the dielectric constant of the material used.

In this way, when the number and thickness of the dielectric layers in different regions on the large printed circuit board and the package substrate are different from those of the materials used, the signal wires having the same line width in different regions will be subjected to The effect of the dielectric material properties of the adjacent dielectric layers results in undesirable signal line impedance mismatches in the signal conductor segments in different regions of the large printed circuit substrate and package substrate.

In view of the above, the present invention provides a printed circuit board that utilizes the thickness or width of a signal conductor to adjust the characteristic impedance of signal conductors in different regions, thereby overcoming the difference in dielectric layer characteristics in a plurality of regions within the printed circuit substrate. .

According to an embodiment, the present invention provides a printed circuit board with adjustable characteristic impedance, comprising: a first dielectric layer having an adjacent one of the first area and a second area defined thereon, wherein the first medium The electrical layer has a first surface and a second surface; a first conductive layer is disposed on the first portion of the first dielectric layer and a portion of the first surface of the second region; a second conductive layer disposed on the first conductive layer in the first region of the first dielectric layer, wherein the second conductive layer and the first conductive layer have the same line width and constitute a signal wire; And a second dielectric layer disposed on the second conductive layer in the first region of the first dielectric layer or on the second surface of the first region of the first dielectric layer .

According to another embodiment, the present invention provides a printed circuit substrate with adjustable characteristic impedance, comprising: a first dielectric layer having adjacent one of the first region, a second region and a third region The first dielectric layer has opposite first and second surfaces; a first conductive layer is disposed in the first region, the second region and the third region of the first dielectric layer a portion of the first surface; a second conductive layer disposed over the first region of the first dielectric layer and the first conductive layer of the third region, wherein the second conductive layer The first conductive layer has the same line width; a third conductive layer and a second dielectric layer are sequentially disposed on the second conductive layer of the first region of the first dielectric layer, wherein the The third conductive layer has the same line width as the second conductive layer and the first conductive layer, and the third conductive layer, the second conductive layer and the first conductive layer constitute a signal wire; and a third medium An electrical layer and a fourth dielectric layer are respectively disposed in the first region of the first dielectric layer and the second region in the third region Above the surface.

According to still another embodiment, the present invention provides a printed circuit substrate with adjustable characteristic impedance, comprising: a first dielectric layer having an adjacent one of the first region and a second region defined thereon, wherein the first The dielectric layer has a first surface and a second surface opposite to each other; a first conductive layer is disposed on a portion of the first surface of the first dielectric layer and the first surface of the second region, wherein The first conductive layer includes: a first segment disposed on the first surface of the first region of the first dielectric layer, having a fixed first line width; a second segment portion, And disposed on the first surface of the second region of the first dielectric layer, having a fixed second line width, wherein the second line width is greater than the first line width; and a third portion And disposed on the first surface of the first dielectric layer and the first surface of the second region and physically contacting the first segment and the second segment, wherein the third segment has a non- Fixing one of the third line widths, and the third line width is not less than the first line width and not greater than the second line width; and a second dielectric layer, And disposed on the first conductive layer in the first region of the first dielectric layer to partially cover the third segment of the first conductive layer and completely cover the first segment of the first conductive layer Or disposed on the second surface of the first region of the first dielectric layer.

According to another embodiment, the present invention provides a printed circuit substrate with adjustable characteristic impedance, comprising: a first dielectric layer having adjacent one of the first region, a second region and a third region The first dielectric layer has opposite first and second surfaces; a first conductive layer is disposed in the first region, the second region and the third region of the first dielectric layer a portion of the first surface, wherein the first conductive layer comprises: a first segment disposed on the first surface of the first region of the first dielectric layer, having a fixed one a second line portion disposed on the first surface of the second region of the first dielectric layer and having a fixed second line width, wherein the second line width is greater than the first a line width; and a third portion disposed on the first surface of the third region of the first dielectric layer, having a fixed third line width, wherein the third line width is smaller than the second The line width is equal or unequal to the first line width; a fourth segment is disposed in the first area and the second portion of the first dielectric layer Above the first surface and physically contacting the first segment and the second segment, having a non-fixed one of the fourth line widths, wherein the fourth line width is not less than the first line width and not greater than the a second line width; and a fifth segment disposed over the first surface of the first dielectric layer and the first surface of the third region and physically contacting the second segment and the third segment a portion having a fifth line width that is not fixed, wherein the fifth line width is not less than the third line width and not greater than the second line width; a second conductive layer and a second dielectric layer are sequentially disposed on The first conductive layer of the first dielectric layer of the first dielectric layer partially covers the fourth segment of the first conductive layer and completely covers the first segment; and a third dielectric layer An electrical layer disposed over the second surface of the third region of the first dielectric layer.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

Hereinafter, the fabrication of a printed circuit board with adjustable characteristic impedance according to an embodiment of the present invention will be described in detail with reference to Figs. It is to be noted that the drawings are a simplified schematic diagram to emphasize the features of the present invention, and thus the component dimensions in the drawings are not drawn to the actual scale. Embodiments of the invention may also include elements not shown in the figures.

First, a dielectric layer 100 suitable for use in a printed circuit substrate is provided having opposite surfaces 102, 104, and three adjacent regions A, B and C are generally defined above the dielectric layer 100. A conductive layer 106 is formed over the surface 102 of the dielectric layer 100 in the regions A, B and C, and a conductive layer 108 is formed over the surface 104 in the region A. Here, the conductive layers 106 and 108 are, for example, an ultra-thin metal layer or a non-metal conductor layer, the thickness of the conductive layer 106 is shown as T ₁ , and the thickness of the conductive layer 108 is shown as T ₂ , and the material of the dielectric layer 100 Insulating materials such as paper phenolic resin, composite epoxy, polyimide resin or glass fiber. The method of forming the conductive layers 106 and 108 over the dielectric layer 100 is, for example, a process such as sputtering, laminating, or coating.

Referring to FIG. 2, a photoresist layer 110 is formed on the conductive layer 106. The photoresist layer 110 is, for example, a dry film photoresist, which can be closely attached to the conductive layer 106 under a proper temperature and pressure. on.

Referring to FIG. 3, a lithography process 114 is then performed to expose the photoresist layer 110. Here, the lithography program 114 uses a mask 112 having a plurality of light-shielding regions 112a and at least one light-transmitting region 112b, wherein the light-transmitting regions 112b are substantially aligned with the regions B, and the light-shielding regions 112a are substantially aligned. Areas A and C. After the lithography process 114 is performed, the photoresist layer 110 in the region B is exposed to become the exposed photoresist layer 110b, and leaves the unexposed photoresist layer 110a in the regions A and C.

Referring to FIG. 4, a developing process (not shown) is performed to remove the unexposed photoresist layer 110a and expose the conductive layers 106 in the regions A and C. Next, a deposition process (not shown) is performed, such as an electroplating process or an electroless plating process, to form another conductive layer 116 in the regions A and C, which may be made of copper, aluminum, nickel, gold metal or Other non-metallic conductive materials, in which copper is the more commonly used material. Here, the thickness T _{3 of the} conductive layer 116 is preferably the same as the exposed photoresist layer 110b on the conductive layer 106 in the region B to provide a planar surface for subsequent processing.

Referring to FIG. 5, a photoresist layer 118 is formed on the conductive layer 116 and the exposed photoresist layer 110b. The photoresist layer 118 is, for example, a dry film photoresist, which can be dense under a suitable temperature and pressure. Attached to the conductive layer 116 and the exposed photoresist layer 110b.

Referring to FIG. 6, a lithography process 122 is then performed to expose the photoresist layer 118. Here, the lithography program 122 uses a reticle 120 having a light-shielding region 120a and a light-transmitting region 120b, wherein the light-transmitting region 120b is substantially aligned with the regions B and C, and the light-shielding region 120a is substantially aligned. Area A. After the lithography process 122 is performed, the photoresist layer 118 in the regions B and C is exposed to become the exposed photoresist layer 118b, and leaves the unexposed photoresist layer 118a in the region A.

Referring to FIG. 7, a developing process (not shown) is performed to remove the unexposed photoresist layer 118a and expose the conductive layer 116 in the region A. Next, a deposition process (not shown) is performed, such as an electroplating process or an electroless plating process, to form a conductive layer 120 in the region A, which may be made of copper, aluminum, nickel, gold metal or other non-metal. Conductive materials, in which copper is the more commonly used material. Here, the thickness T _{4 of the} conductive layer 120 is preferably the same as the exposed photoresist layer 118b on the conductive layer 116 in the regions B and C to provide a planar surface for subsequent processing.

Referring to FIG. 8, a stripping process (not shown) is performed to strip the exposed photoresist layers 110b and 118b in regions B and C, and expose the conductive layer 106 in region B (see Figure 7). And conductive layer 116 in region C (see Figure 7). Then, the film layers such as the conductive layers 120, 116, and 106 are patterned, and the regions A and B are partially removed by using a lithography and etching process similar to the above-mentioned FIGS. 3-4 and 6-7. Patterned film layers such as patterned conductive layers 120', 116' and 106' are formed on dielectric layer 100 with conductive layers 120, 116 and 106 on dielectric layer 100 in C.

Referring to FIG. 9, the top view of the structure shown in FIG. 8 is shown, and the patterned conductive layers 120', 116' and 106' constitute the arrangement and the extension areas A, B and C are interposed. A signal conductor on one of the electrical layers 100. Here, the signal wires have different film structures and thicknesses in the regions A, B, and C, wherein the inner portion 160 of the region A is composed of the patterned conductive layers 120', 116' and 106'. Portions of B are formed of patterned conductive layer 106', and portions 150 of region C are formed of patterned conductive layers 116' and 106'. However, referring to the case shown in Fig. 9, it is known that portions of the signal wires disposed on the dielectric layer 100 extending over the regions A, B and C have the same line width W ₁ .

Referring to FIG. 10, a dielectric layer 170 is formed over the dielectric layer 100 and the conductive layers 116' and 106' in the regions B and C, and the other surface 104 of the dielectric layer in the region C. The dielectric layer 180 is formed on top (see Fig. 1). The dielectric layer 170 is composed of a solder resist material such as green lacquer, which is used as a solder resist layer to prevent the conductive layers 106' and 116' constituting the signal wires in the regions B and C from being subjected to line oxidation and Welding short circuit and other issues. The dielectric layer 180 can be attached to the surface 104 of the dielectric layer 100 in the region C by the adhesive layer 172 to serve as a reinforcing plate. The adhesive layer 172 and the dielectric layer 180 are adhesive such as paper phenolic resin, composite epoxy, polyimide resin or impregnated glass cloth (prepreg). The dielectric layer 180 is composed of, for example, glass fiber, paper phenolic resin, composite epoxy, polyimide resin or impregnated fiberglass cloth. (prepreg) and other insulating materials, the thickness of which can be appropriately adjusted to reinforce the mechanical strength of the panel in the region C.

Referring to FIG. 11, a dielectric layer 185 is formed over the surface 102 of the dielectric layer 100 in the region A (see FIG. 1) and over the conductive layer 120', and over the conductive layer 108 in the region A. A dielectric layer 195, and a conductive layer 187/197 and a dielectric layer 189/199 are selectively formed on the surfaces of the dielectric layers 185 and 195, respectively. Here, the dielectric layer 185/195 is used as a build-up board, which may include, for example, a paper phenolic resin, a composite epoxy, a polyimide resin, or An insulating material such as glass fiber, and the thickness thereof can be appropriately adjusted to reinforce the mechanical strength of the panel in the region A and provide an additional conductive layer 187/197. The conductive layer 187/197 is such as an ultra-thin metal layer or a non-metal conductor layer having a thickness T ₅ and T ₆ , and the dielectric layer 100 is made of a paper phenolic resin or a composite epoxy resin ( Insulation material such as composite epoxy), polyimide resin or glass fiber. The method of forming the conductive layers 187 and 197 over the dielectric layer 185/195 is, for example, a process such as sputtering, laminating, or coating. The dielectric layer 189/199 is composed of a solder resist material such as green lacquer, which is used as a solder resist layer to avoid the conductive layers 106', 116' and 120' constituting the signal wires in the region A and The conductive layer 187/197 and the like are subject to problems such as line oxidation and solder short circuit.

As shown in FIG. 11, a printed circuit board having an adjustable characteristic impedance according to an embodiment of the present invention includes a first dielectric layer (dielectric layer 100) on which a first one is defined. a region (region A or C) and a second region (region B), wherein the first dielectric layer has an opposite first surface (surface 102) and a second surface (surface 104); a first conductive layer (conductive a layer 106') disposed on a portion of the first surface of the first dielectric layer and the first surface of the second region; a second conductive layer (conductive layer 116') disposed on the first a first conductive layer in the first region of a dielectric layer, wherein the second conductive layer and the first conductive layer have the same line width and constitute a signal wire; and a second dielectric layer ( 185 or 180) disposed on the second conductive layer in the first region (region A) of the first dielectric layer or in the first region (region C) of the first dielectric layer Above the second surface. In other embodiments, a third conductive layer (conductive layer 120') and a third dielectric layer (dielectric layer 185) may be sequentially disposed on the second conductive layer (the conductive layer 116'). The third conductive layer, the second conductive layer and the first conductive layer have the same line width and constitute the signal wire, and the second dielectric layer is disposed on the first portion of the first dielectric layer Above the second surface in (Area A). In other embodiments, the first region (region A or C) of the first dielectric layer is, for example, a hard board component region (region A) or a soft board component region (region C), and the first interface The second zone (region B) of the electrical layer is, for example, a turn plate bending zone.

In the implementation of the printed circuit board of the present invention as shown in FIG. 11, the signal conductors located in different regions are mainly changed by using the line width of the fixed signal wires (at least by the conductive layers 106' and 116'). The thickness of the composition is adjusted to the characteristic impedance between the signal conductor portions in different regions such as the region A/C and the region B, so that the regions A, B, and C disposed in the printed circuit board are in a plurality of regions. The characteristic impedances of the various portions of the signal conductor are similar, so that they are not affected by the difference in the number of dielectric layers in each region or the dielectric constant of the dielectric layer material used in each region.

In the above embodiments, the thickness of each portion of the signal wires located in each of the regions A, B, and C can be determined by the number of dielectric layers in each of the regions A, B, and C and/or the dielectric constant of the material used for the dielectric layer. The present invention is also limited by the following formula (1) and is not limited by the implementation of the above embodiments.

Where Z ₀ is the characteristic impedance value of each part of the signal wire, ε _r is the dielectric constant of the dielectric layer (for example, dielectric layers 185, 195, 170, 172 and 180, and combinations thereof), and h ₁ is a conductive layer (eg, the thickness of conductive layers 120', 116' and 106', and combinations thereof), w is the wire diameter of the conductive layer, and h is the conductive layer to the reference layer (eg, dielectric layers 185, 195, 170, 172, and 180) The thickness of the dielectric layer of the film layer.

In addition to the above-described line width of the fixed signal conductor, the characteristic impedance difference between the signal conductor portions in different regions is adjusted by changing the thickness of the signal conductors located in different regions, so that different regions are disposed in the printed circuit board. In addition to the method of the present invention in which the characteristic impedances of the portions of the signal conductors in A, B and C are similar, the present invention also provides for changing the line of signal conductors in different regions by using the thickness of the fixed signal conductor. The method of widening the difference in characteristic impedance between the signal conductor portions in different regions enables the characteristic impedances of the portions of the signal wires disposed in different regions A, B, and C in the printed circuit board to be similar.

Referring to Figures 12-16, the fabrication of a printed circuit board having an adjustable characteristic impedance according to another embodiment of the present invention will be described in detail. It is to be noted that the drawings are a simplified schematic diagram to emphasize the features of the present invention, and thus the component dimensions in the drawings are not drawn to the actual scale. And embodiments of the invention may also include components not shown in the figures.

Referring to FIG. 12, a dielectric layer 200 suitable for a printed circuit substrate is first provided, which has two opposite surfaces 202, 204, and three adjacent regions A are generally defined above the dielectric layer 200. B and C. A conductive layer 206 is formed over the surface 202 of the dielectric layer 200 in the regions A, B and C, and a conductive layer 208 is formed over the surface 204 in the region A. Please refer to Fig. 13, which shows the top view of the structure as shown in Fig. 12. Here, the conductive layers 206 and 208 are, for example, an ultra-thin metal layer or a non-metal conductor layer, the thickness of the conductive layer 206 is shown as T ₇ , and the thickness of the conductive layer 208 is shown as T ₈ , and the dielectric layer 200 The material is an insulating material such as a paper phenolic resin, a composite epoxy, a polyimide resin or a glass fiber. The method of forming the conductive layers 106 and 108 over the dielectric layer 100 is, for example, a process such as sputtering, laminating, or coating.

Referring to FIG. 14, a patterning process 250 is then performed to pattern the conductive layer 206 on the dielectric layer 200 (see FIG. 12). The patterning process 250 used may include similar to the aforementioned 3-4. And the lithography and etching process of FIGS. 6-7, thus partially removing the conductive layer 206 on the dielectric layer 200 in the regions A, B, and C, and forming five vias on the dielectric layer 200. The patterned conductive segments 206a-206e form one of the signal wires. Figure 15 shows the top view of the structure shown in Figure 14.

As shown in FIGS. 14 and 15, the signal conductor includes a conductive segment portion 206a disposed on the surface 202 in the region A of the dielectric layer 200, and a surface 202 disposed in the region B of the dielectric layer 200. Conductive segment portion 206b, conductive segment portion 206c disposed over surface 202 in region C of dielectric layer 200, conductive segment disposed over surface 202 in regions A and B of dielectric layer 200 Portion 206c and conductive segment portion 206e disposed over and extending over surface 202 in regions B and C of dielectric layer 200. Here, the conductive segment portion 206a has a fixed line width W ₂ , and the conductive segment portion 206b has a fixed second line width W ₃ , and the second line width W _{3 is} greater than the first line width of the first segment portion 206a. W ₂ , and the conductive segment portion 206c has a fixed third line width W ₄ , and the third line width W _{4 is} smaller than the second line width W ₃ and is equal or not equal to the first line width W ₂ . In addition, the conductive segment portion 206d disposed on the inner surface 202 of the regions A and B physically contacts the first segment portion 206a and the second segment portion 206b, and has a non-fixed one of the fourth line widths, which is not less than the first line width W. ₂ and not greater than the second line width W ₃ , and the conductive segment portion 206e disposed on the inner surface 202 of the regions B and C physically contacts the second segment portion 206b and the third segment portion 206c, and has a non-fixed fifth The line width is not greater than the second line width W ₃ and not less than the third line width W ₄ . In other embodiments, the region A or C of the dielectric layer 200 is, for example, a hard plate component region or a soft board component region, and the region B of the dielectric layer 200 is, for example, a turn plate bending region.

Referring to FIG. 16, the dielectric layers 170, 180, 185, 189, 195 may be formed in regions A, B, and C, respectively, using the same or similar implementations as the manufacturing processes shown in FIGS. The same film layer as 199, and the conductive layers 187, 197, and the adhesive layer 172 are used. In the present embodiment, the above-mentioned film layer also functions as the same function as in the structure shown in Figs. 10-11, and thus its respective functions will not be described in detail herein.

As shown in FIG. 16, a printed circuit board having an adjustable characteristic impedance according to another embodiment of the present invention includes a first dielectric layer (dielectric layer 200) on which a adjacent one is defined. a region (region A/C) and a second region (region B), wherein the first dielectric layer has an opposite first surface (surface 202) and a second surface (surface 204); a first conductive layer ( The conductive layer 206a~e is disposed on a portion of the first surface of the first dielectric layer and the first surface of the second region, wherein the first conductive layer comprises: a first segment a portion (the conductive portion 206a/206c) disposed on the first surface of the first region of the first dielectric layer, having a fixed first line width (line width W ₂ ); a second a segment portion (the conductive segment portion 206b) disposed on the first surface of the second region of the first dielectric layer and having a fixed second line width (line width W ₃ ), wherein the second portion The line width is greater than the first line width; a third portion (the conductive portion 206c) is disposed on the first surface of the first region of the first dielectric layer, and has a fixed third line width (W _4), where The third line width is smaller than the second line width and equal or not equal to the first line width; and a fourth segment portion (the conductive segment portion 206d/206e) is disposed in the first region and the second portion of the first dielectric layer Above the first surface in the region and physically contacting the first segment and the second segment, and the second segment and the third segment, wherein the fourth segment has a non-fixed one of the fourth line width and a fifth line width, and the fourth line width is not less than the first line width (line width W ₂ ) and not greater than the second line width (line width W ₃ ), and the fifth line width is not greater than the second a line width (line width W ₃ ) and equal or unequal to the first line width (line width W ₁ ); and a second dielectric layer (dielectric layer 185/180) disposed on the first dielectric layer The first conductive portion of the first conductive layer partially covers the first conductive portion of the first conductive layer and completely covers the first conductive portion of the first conductive layer, or is disposed on the first conductive layer Above the second surface of the first region of the electrical layer.

In other embodiments, the method further includes a third conductive layer (conductive layer 208) and a third dielectric disposed on the second surface in the first region (region A) of the first dielectric layer. Electrical layer (dielectric layer 195).

In other embodiments, the first region (region A or C) of the first dielectric layer is, for example, a hard board component region (region A) or a soft board component region (region C), and the first interface The second zone (region B) of the electrical layer is, for example, a turn plate bending zone.

In the implementation of the printed circuit board of the present invention as shown in FIG. 16, the signal wires located in different regions are changed by using the thickness of the fixed signal wires (at least by the conductive segments 206a/c and 206b and The line width of the conductive segment portion such as 206d/e is adjusted to the characteristic impedance between the signal conductor portions in different regions such as the region A/C and the region B, so that the region A disposed in the printed circuit board is The characteristic impedances of the signal conductors in the B and C regions are similar, so that they are not affected by the difference in the number of dielectric layers in each region or the dielectric constant of the dielectric layer materials used in each region. The difference is different.

In the above embodiment, the line widths of the conductive segments forming the signal wires in the respective regions A, B and C can be regarded as the number of dielectric layers in the regions A, B and C and/or the materials used for the dielectric layer. The dielectric constant is adjusted with reference to the above formula (1), and the present invention is not limited by the embodiments in the above embodiments.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100, 200. . . Dielectric layer

102, 104, 202, 204. . . Surface of the dielectric layer

106, 116, 120. . . Conductive layer

106', 116', 120'. . . Patterned conductive layer

108. . . Conductive layer

110, 118. . . Photoresist layer

110a, 118a. . . Unexposed photoresist layer

110b, 118b. . . Exposured photoresist layer

112, 120. . . Mask

112a, 120a. . . Shading area

112b, 120b. . . Light transmission area

114, 122. . . Microfilm program

150. . . One part of the signal wire

160. . . One part of the signal wire

170. . . Dielectric layer

172. . . Adhesive layer

180, 185, 189, 195, 199. . . Dielectric layer

187, 197. . . Conductive layer

200. . . Dielectric layer

202, 204. . . Surface of the dielectric layer

206, 208. . . Conductive layer

206a, 206b, 206c, 206d, 206e. . . Conductive section of the signal conductor

A, B, C. . . region

T ₁ . . . Thickness of conductive layer 106

T ₂ . . . Thickness of conductive layer 108

T ₃ . . . Thickness of conductive layer 116

T ₄ . . . Thickness of conductive layer 120

T ₅ . . . Thickness of conductive layer 187

T ₆ . . . Thickness of conductive layer 197

T ₇ . . . Thickness of conductive layer 202

T ₈ . . . Thickness of conductive layer 208

W ₁ . . . Line width of signal wire

W ₂ , W ₃ , W ₄ . . . Line width of the conductive segment of the signal wire

1-8, 10-11 are a series of cross-sectional views showing the fabrication of a printed circuit board with adjustable characteristic impedance in accordance with an embodiment of the present invention;

Figure 9 is a schematic view showing the top view of the structure as shown in Figure 8;

12-14, 16 are a series of cross-sectional views showing the fabrication of a printed circuit board with adjustable characteristic impedance in accordance with another embodiment of the present invention;

Fig. 15 is a schematic view showing the top view of the structure as shown in Fig. 14.

100. . . Dielectric layer

106', 116', 120'. . . Patterned conductive layer

108. . . Conductive layer

150. . . One part of the signal wire

160. . . One part of the signal wire

170. . . Dielectric layer

172. . . Adhesive layer

180, 185, 189, 195, 199. . . Dielectric layer

187, 197. . . Conductive layer

A, B, C. . . region

T ₅ . . . Thickness of conductive layer 187

T ₆ . . . Thickness of conductive layer 197

Claims (9)

A printed circuit board with adjustable characteristic impedance, comprising: a first dielectric layer having an adjacent one of a first region and a second region defined thereon, wherein the first dielectric layer has a first surface opposite to a second surface; a first conductive layer disposed on the first portion of the first dielectric layer and a portion of the first surface of the second region; a second conductive layer disposed on the first surface Above the first conductive layer in the first region of the dielectric layer, wherein the second conductive layer and the first conductive layer have the same line width and constitute a signal wire, and the second conductive layer physically contacts the a first conductive layer; and a second dielectric layer disposed on the second conductive layer in the first region of the first dielectric layer or the first region of the first dielectric layer Above the second surface. The printed circuit board of the adjustable characteristic impedance of claim 1, further comprising a third conductive layer and a third dielectric layer disposed on the second conductive layer, wherein the third The conductive layer, the second conductive layer and the first conductive layer have the same line width and constitute the signal wire, and the second dielectric layer is disposed in the first region of the first dielectric layer Above the surface. The printed circuit board of the adjustable characteristic impedance of claim 2, wherein the second dielectric layer and the third dielectric layer are a build-up board. The printed circuit board of the adjustable characteristic impedance of claim 1, wherein the second dielectric layer is disposed on the first dielectric layer One of the second surfaces above the first zone is reinforced. The printed circuit board of the adjustable characteristic impedance of claim 1, wherein the first region of the first dielectric layer is a hard plate component region or a soft plate component region, and the first dielectric The second zone of the layer is a turn plate bending zone. A printed circuit board with adjustable characteristic impedance, comprising: a first dielectric layer defining a first one of the first region, a second region and a third region, wherein the first dielectric layer has a relative a first surface and a second surface; a first conductive layer disposed on the first region of the first dielectric layer, a portion of the second region and the first surface of the third region; a second conductive layer disposed on the first conductive layer of the first dielectric layer and the first conductive layer, wherein the second conductive layer and the first conductive layer have the same line width. And the second conductive layer is in physical contact with the first conductive layer; a third conductive layer and a second dielectric layer are sequentially disposed on the second conductive layer in the first region of the first dielectric layer The third conductive layer has the same line width as the second conductive layer and the first conductive layer, the third conductive layer physically contacts the second conductive layer, and the third conductive layer and the second conductive layer And the first conductive layer constitutes a signal wire; and a third dielectric layer and a fourth dielectric layer are respectively disposed on The second region of the first surface of the first dielectric layer and the third region of the above. The printed circuit board of the adjustable characteristic impedance of claim 6, wherein the second dielectric layer and the third dielectric layer are a build-up layer board. The printed circuit board of the adjustable characteristic impedance of claim 6, wherein the fourth dielectric layer is reinforced on one of the second surfaces of the third region of the first dielectric layer. board. The printed circuit board of the adjustable characteristic impedance of claim 6, wherein the first region of the first dielectric layer is a hard plate component region, and the second region of the first dielectric layer is A turn plate bending zone and the third zone of the first dielectric layer are a soft board component region.