TW201121016A - Systems and methods of improved heat dissipation with variable pitch grid array packaging - Google Patents

Systems and methods of improved heat dissipation with variable pitch grid array packaging Download PDF

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TW201121016A
TW201121016A TW99121577A TW99121577A TW201121016A TW 201121016 A TW201121016 A TW 201121016A TW 99121577 A TW99121577 A TW 99121577A TW 99121577 A TW99121577 A TW 99121577A TW 201121016 A TW201121016 A TW 201121016A
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Taiwan
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region
solder
package
pads
interface
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TW99121577A
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TWI442531B (en
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Jianjun Li
Robert Warren
Nic Rossi
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Conexant Systems Inc
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Abstract

Adequate heat dissipation is essential for semiconductor devices. When a device exceeds a specified junction temperature, the device can be damaged, not perform correctly, or can have a reduced operating life. Semiconductor packages must dissipate heat from the chip to the external environment (i.e. to the PCB, air, etc) to keep the semiconductor device below a certain temperature threshold. For most devices, the most efficient way to dissipate the heat is through the package external I/O connections and into the PCB that it is mounted to. For Ball Grid Array (BGA) packages, the external I/Os are solder balls. Variable pitch packages pose advantages in heat dissipation without introducing significant costs.

Description

201121016 六、發明說明： 【發明所屬之技術領域】 本發明大體上係關於半導體封裝且特定言之係關於可調 間距介面之使用。 【先前技術】 由於對於具有現代積體電路（IC)之更多輸入_輸出（1/〇)介 面之需要，ic封裝已自雙列直插引腳（DIp)封裝（其中僅在 引腳柵格陣列（PGA)周邊上引腳係有用的）演進而來，其中 在該封裝下在一柵格圖案中引腳係有用的。在一pga中之 引腳係用於將來自積體電路之電訊號傳導至一印刷電路 板，且反之亦然。一經封裝的球柵格陣列BGA以附接至該 封裝（其將電訊號傳導至印刷電路板PCB且自印刷電路板 PCB傳導電訊號）之底部之焊料球代替該等引腳，而不是具 有長引腳E配的pCB具有呈匹配該等焊料球之圖案之導 電墊。當加熱該封裝時，焊料熔化並耦合該封裝至該 PCB。當該封裝冷卻時’焊料凝固，從而完成組裝。 一 BGA封裝提供高密度連接，當技術微型化時尤為如 此。隨著輸出引腳密度增加，諸如DIp與p(JA之較老技術 ，寻不將引腳更緊密地封裝在一起，使得組裝更固難。若 f料溢出，焊接高密度引腳則造成使相鄰引腳短路之一更 间機率》BGA避免此缺點，此係因為該焊料為被禁大小之 幵v式且係預先定位於該封裝上。 因為輸出導體比在基於封裝之引腳内短得多，所以 有較低電感。在—封裝内之電感可引起不必要之訊號失 I49183.doc 201121016 真’在高速應用中尤為如此。優於基於封裝之引腳之BGA 封裝之另一優點提供該封裝與PCB之間之較低熱電阻。此 允許更多地將熱量從積體電路導走，從而有助於防止過 *、、、 一積體電路可透過接線或藉由覆晶連接而連接至球。圖 1圖解說明一典型接線接合BGA封裝之一截面。經製造晶 粒102與晶粒附接件104一起附接至基板1〇6。經製造晶粒 102係透過接合墊11 〇而電氣地接達穿過接線丨〇8。接線1 〇8 亦可透過諸如金屬跡線112之一金屬跡線而連接至基板 106。在一些封裝中，基板106可包括多層且含有用於繞送 之額外金屬跡線，但在此圖解中，基板1〇6係一多層。金 屬跡線112係透過通孔114而連接至諸如金屬跡線丨丨6之一 接合指狀物》諸如金屬跡線116之在基板底部上之金屬跡 線包括諸如焊料墊118之一焊料墊，其中諸如焊料球12〇之 一焊料球可在工廠被附接。焊料遮罩122覆蓋在基板底部 上之該等金屬跡線，但使開口曝露諸如焊料墊118之該等 焊料墊。模製化合物13 0填充該封裝。 通常，諸如通孔114之該等通孔係鑽入該基板中且沿著201121016 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to semiconductor packages and, in particular, to the use of adjustable pitch interfaces. [Prior Art] Due to the need for more input-output (1/〇) interfaces with modern integrated circuits (ICs), the ic package has been packaged from a dual in-line pin (DIp) package (where only the pin gate The pins on the perimeter of the cell array (PGA) are useful, where pins are useful in a grid pattern under the package. The pins in a pga are used to conduct electrical signals from the integrated circuit to a printed circuit board and vice versa. A packaged ball grid array BGA replaces the pins with solder balls attached to the bottom of the package that conducts electrical signals to the printed circuit board PCB and conducts electrical signals from the printed circuit board PCB, rather than having a length The pCB of pin E has a conductive pad that matches the pattern of the solder balls. When the package is heated, the solder melts and couples the package to the PCB. When the package cools, the solder solidifies, thereby completing the assembly. A BGA package provides a high density connection, especially when the technology is miniaturized. As the output pin density increases, such as DIp and p (the older technology of JA, it is harder to pack the pins together, making assembly more difficult. If the material overflows, soldering high-density pins causes One of the shortcomings of shorting adjacent pins" BGA avoids this disadvantage because the solder is banned and is pre-positioned on the package because the output conductor is shorter than in the package-based pins. Much more, so there is a lower inductance. Inductors in the package can cause unnecessary signal loss. I49183.doc 201121016 This is especially true in high-speed applications. Another advantage over package-based BGA packages is provided. The lower thermal resistance between the package and the PCB. This allows more heat to be conducted away from the integrated circuit, thereby helping to prevent over-,, or an integrated circuit from being through the wiring or by flip-chip connection. Connected to the ball. Figure 1 illustrates a cross section of a typical wire bonded BGA package. The fabricated die 102 is attached to the substrate 1〇6 along with the die attach 104. The fabricated die 102 is passed through the bond pad 11 And electrically access through the wiring丨8. The wiring 1 〇 8 may also be connected to the substrate 106 through a metal trace such as one of the metal traces 112. In some packages, the substrate 106 may comprise multiple layers and contain additional metal traces for routing, but here In the illustration, the substrate 1 〇 6 is a plurality of layers. The metal trace 112 is connected through a via 114 to a metal such as a metal trace 116, such as a metal trace 116, on the bottom of the substrate. The trace includes a solder pad, such as one of the solder pads 118, wherein one of the solder balls, such as solder balls 12, can be attached at the factory. The solder mask 122 covers the metal traces on the bottom of the substrate but exposes the opening such as The solder pads of the solder pads 118. The molding compound 130 fills the package. Typically, such vias such as vias are drilled into the substrate and along

通孔壁塗覆一 116之間之電掮 孔並非必要。 、焊料球電接It is not necessary to apply a hole between the walls of the through hole 116. , solder ball electrical connection

穿過基板106之通孔除了與—經製造晶粒 觸外，亦可用 102熱接觸。 149183.doc 201121016 128在此情況下，通孔124亦可用作為一熱通孔。一通孔 可用作為一電通孔、—熱通孔之一者或二者。一熱通孔可 用諸如金屬之一熱導體完全填滿。此較若該通孔僅用熱 導體塗覆提供更好之熱傳導。因此，該通孔接著將以焊料 遮罩材料填滿。 諸如經電耦合之介面墊118之介面墊通常係耦合至一印 刷電路板内之一金屬跡線，其中訊號或電流可耦合至其他 組件。在BGA封裝之情況下，該等介面墊係稱為焊料墊。 諸如可用於熱目的之焊料球128之該等焊料球經常係耦合 至一單一共同金屬線。事實上，通常此金屬線係pCB上之 一接地平面。 圖2更詳細地顯示基板之表面上之金屬跡線。一些例示 性跡線係顯示為基板106之頂部上之金屬跡線112。亦指出 晶粒102之位置。在該詳細視圖中，區域2〇2顯示接線可在 何處附接至金屬跡線。區域2〇4顯示諸如鋪設於該等金屬 跡線下方之通孔114之該等通孔之位置。 圖3更詳細地顯示基板底部上之金屬跡線。六個例示性 金屬跡線係顯示為金屬跡線丨16。各金屬跡線包括顯示為 118之一焊料墊。區域3 02顯示通孔下方之區域。 圖4顯示覆蓋圖3中顯示之該等金屬跡線之焊料遮罩122 的一對應區段。焊料遮罩122覆蓋基板底部上之該等金屬 跡線，但為焊料塾留下開口。 圖5圖解說明稱為一下腔bga封裝之一替代BGA封裝。 經製造晶粒502與晶粒附接件504 —起附接至通常由銅製成 149183.doc 201121016. 之金屬塊506。此組態相較於圖1之組態係上下顛倒。接線 5 10透過接合墊508連接至經製造晶粒502。接線5 10亦連接 至層壓板512。層壓板512包括金屬跡線514與通孔516。接 線510特定連接至金屬跡線514。通孔516連接金屬跡線514 至;tp料塾518與焊料球520 » —蓋子或液體囊封劑（522)完成 該封裝。 圖6圖解說明使用一覆晶附接之一 bga封裝。經製造晶 粒602係附接於多層基板606。覆晶附接不僅提供經製造晶 粒602至多層基板606之一實體附接，亦提供經製造晶粒 602與多層基板606之間之電接觸。經製造晶粒6〇2係使用 凸塊604而不是使用接線附接至通孔墊62〇。通孔墊62〇繼 而附接至本文藉由通孔61 〇顯示之通孔。此後，介於經製 造晶粒602與基板606之間包含凸塊604之介面被填膠622包 住此封裝使用金屬跡線6 0 8與額外通孔6 2 4以透過基板 606將電成號自經製造晶粒602繞送至焊料塾612。焊料球 614係在工廠中附接至焊料墊612。該封裝係以導熱膏616 與金屬蓋618完成。雖然實施可能較為複雜，但是熱介面 亦可用於腔BGA與覆晶附接BGA封裝中。 • 圖7顯示用於一BGA封裝之一例示性焊料球圖案。基板 702係顯示為包括複數個焊料墊704。在各焊料墊上的是一 焊料球’在該圖中由焊料球7〇6表示。在此特定實例中， 焊料球不覆蓋該基板之整個基底。對於BGa封裝之一些形 式，此係更佳。圖8顯示一BGA封裝之另一焊料球圖案。 基板802係顯示為包括由焊料墊8〇4表示之複數個焊料墊。 149183.doc 201121016 在各焊料墊上的是一焊料球8〇6。在放大圖中，為清晰起 見，一些焊料墊係顯示為不具有一悍料球。更為清晰地， 只顯示由該焊料遮罩保留為曝露之該焊料墊。應瞭解在此 圖表與後續圖纟中-焊料遮罩可呈現為僅曝露上文金屬跡 線層中之焊料墊^各焊料墊具有於8〇8處所示之一相對均 勻直k 各&料球亦具有於810處所示之一實質均勻直 徑。此外，相鄰焊料球中心或等效焊料墊中心之間之距離 被稱為間距812。 值得一提的是亦存在非焊料遮罩界定之BGA封裝。與一 非焊料遮罩界定之BGA之間，之關鍵區別係焊料遮罩中之開 未界疋知料塾之曝路程度。圖9A顯示該焊料遮罩界定之 BGA封裝之一近視圖。此實質上係與上述描述之bga封裝 一致。焊料墊902為焊料球904提供一接觸點。烊料遮罩 9〇6為焊料球904提供一開口。事實上，該焊料球可填滿藉 由焊料遮罩9 0 6提供之整個開口。 圖9B顯示一非焊料遮罩界定之BGA封裝之一近視圖。不 同於該焊料遮罩界定之BGA封裝，焊料球914位於焊料墊 912上且潛在地圍繞焊料墊912。在此情況下，焊料遮罩 916具有比該等焊料墊更大之開口。不管使用焊料遮罩界 定之BGA或非焊料遮罩界定之BGA與否，關於熱傳導所討 論之原理仍適用。 雖然使用熱通孔以從該經製造晶粒汲取鈦| 叉取熱重’可助於熱 消散’但是其具有其限制。首先’可用於熱目的之焊料墊 數量受電連接至該經製造晶粒所需之焊料墊數量的限制。 149183.doc 201121016 因此若存在1〇0個焊料塾，但是電連接需要88個，則僅12 個可用於熱目的。焊料墊數量可藉由減少間距增加。然 而’此可構成增加該封裳與用於與該封裝連通之PCB之成 • I t 冑&疋因為必須使用細尺寸跡線與通孔用於繞 送。對於由短路或開路引起之較低良率，細間距BGA之組 裝亦可為更有挑戰性。 其他方法已藉由下列方式試圖解決該熱消散問題：為封 裝添加散熱器；使用較高熱導率模製化合物；增加封裝層 數或大小或使用較高熱導率晶粒附接環氧樹脂。在一些極 端情況下，增加該晶粒大小以改善熱消散。然而，此等努 力係非常昂貝且負面影響產品利潤，加上已證明景多響裝置 之可罪性。因此在工業中需要廉價封裝技術來改善熱消 散。 【發明内容】 在諸如BGA、PGA、圓柱柵格陣列（CGA)及平面栅格陣 列（LGA)之一陣列式介面封裝中，可列陣該等介面之間 距。一半導體封裝包括附接至一基板之一經製造晶粒。該 基板之頂面含有通常用於將電訊號傳導至該基板中之通孔 . 之金屬跡線。該基板之底面亦含有連接該等通孔至可為一 引腳或一焊料墊之介面之金屬跡線。該等介面可隔開至少 兩個間距。一焊料遮罩係視需要應用於該基板底部以防止 知路。該焊料遮罩具有對應於該等焊料墊之開口。若該等 焊料墊具有可調間距’則該等焊料遮罩開口亦具有可調間 距°然後可在該等焊料墊上放置焊料球。該等焊料球之間 149183.doc 201121016 距係與該等對應焊料墊之間距相同。 ^ ^電通孔或用於傳導電訊號之通孔僅以導體塗覆於 其等之壁。與之相反，熱通孔係以導體填滿以使其等能夠 從晶粒導走更多熱量。此外，耦合至熱通孔之焊料墊可以 更同役度封裝在一起並因此成為較高間距介面之理想候選 者。 額外的封裝類型亦可利用可調間距陣列佈局，包含覆晶 BGA、下腔BGA、PGA^LGA。 在檢視下列圖式及詳細描述後，本揭示内容之其他系 統、方法、特徵及優點將為熟悉此項技術者所顯而易見。 希望所有此類額外系統、方法、特徵及優點係包含於此描 述内，係在本揭示内容之範疇内，且受隨附申請專利範圍 的保護。 【實施方式】 可參考下列圖式更好地理解本揭示内容之許多態樣。圖 式中之組件未必係按比例繪製，重點而是在於清晰地圖解 說明本揭示内容之原理。此外，在圖式中，相同參考數字 4曰疋貫穿若干圖視之對應部分。 下文呈現本發明之實施例之一詳細描述。雖然將結合此 等圖式描述本揭示内容’但是不希望將本揭示内容限於本 文所揭示之該（等）實施例。相反言之，本發明意欲涵蓋包 含於如由隨附申請專利範圍定義之本揭示内容之精神及範 嘴内之所有替代物、修改及等效物。 圖10顯示具有可調間距1/〇介面之一封裝之一仰視圖。 149183.doc •10- 201121016 該封裝可為諸如BGA、PGA及/或LGA之陣列技術之任一 者，但是出於本文之目的，使用BGA之實例。此外，使用 類似圖1描述之封裝作為一實例。然而，一般技術者將瞭 解其對諸如PGA與LGA之替代陣列封裝及諸如CBGA與覆 晶BGA之不同BGA組態之適用性。 在圖11中，區域Π02係最直接地位於經製造晶粒下方。 在一多層基板中，如圖1所示，該經製造晶粒下方之區域 係最不適合於繞送電訊號但最適合於熱傳導。該經製造晶 粒下方之一細間距陣列允許每單位面積更大數量之焊料 球，其增加自晶粒至該晶粒所安裝之pcB之導熱路徑。在 區域1102外’使用允許更經濟之電繞送之一粗間距。因為 »亥間距更寬’故跡線寬度、跡線間隔及該之電鑛穿孔 大小可為更大，其導致更高的組件良率。 使用可調間距之-困難係為了允許：級組裝，該等焊料 球大小必須為相同大小圖解說明使用不同大小焊料 球之封裝之截面。假定區域UG4巾具有—粗間距之焊料 球大於區域11G2中具有—細間距之焊料球。因為該等焊料 収直徑^同，故料較小焊料料與下方之pcB接觸， 從而無法相H由料焊料球之熱料之目的，或者區域 1104中之料焊料球在㈣㈣期間經過度壓縮使得焊料 可溢出並與相鄰焊料球電接觸。因此為使此類型之封裝為 有效，應維持一均勻焊料球平坦性。 通吊’建議-給定焊料球大小用於某一範圍之柵格陣列 間距。例如’通常將相同焊料球大小用於㈣米及1〇毫 149183.doc 201121016 米間距。例如，500微米或600微米焊料球可通常用在〇 8 毫米或1.0毫米間距應用中。由於球數係與間距大小的平 方成正比，故用於熱消散之該0.8毫米間距允許超過40%的 球數增加。圖丨2圖解說明一封裝之截面，其中相同球大小 用於所示之兩個間距。在區域12〇2中，使用一細間距，諸 如〇.8毫米。在區域1204中，使用一粗間距，諸如1〇毫 米。 在圖12中，建4相同球大小用於區域12〇2及區域12⑽中 之門距#在特疋區域中需要球之較高密度，則可使用 經建議用於細間距之球大小。圖13圖解說明此實例，在區 域1 302中使用甚至細於圖丨2所示之間距的一間距。通常， 會建議-較小球大小用於細間距。然而，由於熱疲勞，該 較小球大小會遭遇較低可靠度之問題，且使用該較小球大 小之封裝在-落下測試中會有—較高失敗率。& 了避免圖 11所示之情形’此較小球大小即可用於所有區域包含具 有-粗間距且將通常使用一經建議較大球大小之區域 1304。 使用經建議用於每-各自區域之兩個球大小之較小者之 主要基本原理係為了避免當球被加熱及被附接至pc該 等球之間之電接觸。此將防止短路。然而，如圖Μ所示了 若具有細間距之區域贈係用於熱目@，則可使用該兩個 球大小之較大者。相較於該較小球大小’該較大球大小將 有助於更多熱傳導1為區域刚中之該等焊料球與對應 通孔係❹於熱㈣，故相鄰焊_之間的接觸將不會有 149183.doc •12- 201121016 負面影響。 一般而言，使用細間距陣列之另一困難係，諸如基板底 面上之跡線之金屬跡線必須具有細線且此外該等焊料墊在 其等之間潛在地具有較小間隔，此導致較低良率及/或較 尚封裝成本。然而，若一可調間距封裝之該細間距區域僅 用於熱目的，則不必為各焊料墊維持單獨金屬跡線。圖15 圖解說明-金屬跡線’纟包括一可調間距封裝之細間距區 域中之複數個焊料墊。此實例中之金屬跡線15〇2實際上包 括該細間距區域中之所有該等焊料墊。由開口 1504表示之 該等區域表示由焊料遮}留下之該等開口。（為清晰起 見，僅標注該等開口中之一些）。由於為熱㈣，不必電 分開該等焊料墊，-單_金屬跡線或若干大金屬跡線可包 括在該細間距區域内之該等焊料墊。若在該細間距區域中 需要-些電介©’則對應焊料塾可由與用於熱介面之金屬 跡線分開之金屬跡線形成。 雖然上述貧例暗指在中心區域中之細間距之用途，可調 門距之用途可應用於封裝底部上之任何位置。圖16顯示使 用細間距之兩個區域之一實例。特定言之，區域祕及 上之焊料墊/焊料球具有較基板1602之剩餘區域上之 谭料塾/焊料球為細的間距。該兩個區域可代表—多晶粒 1中之兩個單獨晶粒下方之基板。雖然並非必要，在附 接曰曰粒下配置熱通孔係用於冷卻之一有效焊料球配置。因 此右日日粒附接在區域1 604及1 606上，則焊料球之一細間 距陣列更能促進冷卻。 149183.doc -13- 201121016 在電性上，可調間距封裝亦可能係有用#。通常，該等 接合墊在一晶粒之表面上基本上係等距間隔的。晶”之 内部電路必須繞送訊號至其等之各自接合塾。$了滿足由 該等接合塾引起之該等需求，可能需要金屬跡線方面之進 一步繞送n 放寬此等需求，晶粒繞送中之金屬跡 線數量可潛在減少。事實上，可行的是，^肖除若干金屬 跡線層，從而減少製造一晶粒及/或基板之成本。 圖17顯示利用可調間距以放鬆對晶粒之繞送需求之一假 疋實例。在此實例中，晶粒17〇6係以略圖顯示。為了清晰 起見，未顯示在晶粒1706下之任何焊料墊及焊料球。舉例 而言，晶粒1706裝置可需要1〇〇個接合墊於該晶粒之各側 上，但區域1708中需要150個。此可引起在區域17〇8附近 之側上之繞送困難，因為其將需要不在該封裝側上之額外 1/〇傳統地，留給該設計者之唯一選擇，貫穿該封裝不 使用一細間距以獲得額外介面’係為了從該封裝之其他側 借封裝介面（例如焊料球）並將1/0繞送至該等借來的介面。 取而代之，措由使用一細間距在區域17 〇 4中提供額外介 面’使得繞送更容易，且由於該等跡線不必經繞送至該封 裝之其他側，故跡線電阻及電感係較低且性能不會退化。 不平衡的I/O情形可（尤其）在多晶片封裝中出現。因為細間 距使用於該封裝之僅一部分，故由細間距介面施加之較高 谷限需求僅應用於該封裝之一部分’因此使得在具有細間 距之一封裝上製造更容易。 圖18顯示圖解說明用於產生具有一可調間距介面之一封 149183.doc -14- 201121016 裝之流程圖。一般技術者將注意到並非所有步驟需按所述 順序執行且許多步驟可按不同順序執行。在步驟18〇2處， 在一基板中形成通孔。此通常係藉由鑽孔而執行。在步驟 1804處，將一導體材料施加於該通孔。在電通孔之情形 下，該等導體通常塗覆該通孔之壁 且在熱通孔之情形 下，該等導體填滿該通孔。在步驟1806處，在為一接線提 供一場所之基板頂部上形成金屬跡線且將該等金屬跡線連 接至該等通孔之至少-些通孔。在步驟18()8處，於基板底 部上形成金屬跡線，其中該等金屬跡線包括成__陣列之介 面墊。該等介面墊包括至少兩個區域，一粗區域（其中該 等介面墊係分開得較遠）及一細區域（其中該等介面墊分開 得較近）。在步驟1810處，將一焊料遮罩施加於具有開口 之基板底部，該等開口曝露粗區域中之該等介面墊與細區 域中之該等介面墊。在步驟1812處，將該晶粒附接至該基 板。在步驟1814處，將接線附接i晶粒上之該等接合塾並 附接至基板頂部上之該等金屬跡線。或者，可將該晶粒覆 晶至該等通孔墊或基板頂部上之金屬跡線上。在步驟UK 處’使用-模製化合物来囊封該晶粒、接線及該基板頂 部。在步驟1818處，將諸如焊料球之介面之一陣列附接至 該等介面塾，#中該等焊料球在該細區域中係、—起間隔得 較近且在一粗區域中係分開得較遠。在？(}八情形下’一引 腳陣列可附接至該等介面塾。在CGA情形下，一陣列圓柱 可附接至該等介面墊。在LGA情形下，該等介面塾本身係 該等介面。 ” 149183.doc -15- 201121016 因為應用可調間距介面之製造技術使用既有製造技術且 僅要求修改基板下之金屬跡線層之設計，放置該等介面 塾，修改焊料遮罩之設計及放置介面，所以不會招致明顯 額外製造成本。使用一可調間距BGA封裝已觀察到封裝熱 消散之一 2%至5°/。的改善。儘管該熱改善可能看似很小， 此差別可影響5%至15%之封裝成本，及/或影響一裝置可 適應之功能量或速度量。 如前所述’除了所示之多層基板BGA外，可調間距介面 亦可用於使用介面陣列（諸如上述BGA以及PGA及LGA之其 他類型）之任何封裝技術中。 應強調上述實施例僅係可能實施方案之實例。舉例而 s ’所描述之實施例係在BGA之背景下，但可同樣應用於 使用陣列式介面之PGA、LGA或其他封裝》熟悉此項技術 者應瞭解彼等可容易地使用所揭示之概念與特定實施例作 為設計或修改其他結構之一基礎以實現本文所提出之相同 目的。熟悉此項技術者應瞭解彼等可在不脫離本發明之最 廣泛形式之本發明的精神及範疇的情況下，可於本文中作 出各種改變、替代及變更。所有此等修改及變動於本文中 係意欲包含於此揭示内容之範疇内且受下列申請專利範圍 的保護》 【圖式簡單說明】 圖1圖解說明一典型接線之BGA封裝之一截面； 圖2更詳細地顯示基板表面上之金屬跡線； 圖3更詳細地顯示基板底部上之金屬跡線； 149183.doc •16· 201121016 圖4顯示覆蓋圖3所 區段； 示之金屬跡線之一 焊料遮罩之一 對應 圖5圖解說明被稱為-腔BGA封裝之一替代隐封裝； 圖6圖解說明使用—覆晶附接之-BGA封裝； 圖7 員示B GA封裝之一例示性焊料球圖案； 圖8顯不一 BGA封裝之另一焊料球圖案； 圖9A顯示該焊料遮罩BGA封裝之一近視圖； 圖9B顯示—非焊料遮罩bga封裝之—近視圖； 圖10顯示具有可調間距1/〇介面之一封裝之一仰視圖； 圖11圖解說明使用不同球大小之一封裝之—截面； 圖12圖解說明相同球大小用於所示之兩個間距之一封装 之一截面； 圖13圖解說明—封裝之截面’其中若介面為細間距，則 該兩個球大小之較大者係用於熱目的； 圖"圖解說明—金屬跡線，其包括在一可調間距封裝之 細間距區域内之複數個焊料墊； 圖15顯示包括疊於其上的諸焊料墊之一金屬跡線； 圖16顯示使用細間距之兩個區域之一實例； 圖17顯示利用可調間距以放鬆對晶粒之繞送要求之一假 定實例；及 圖18顯示圖解說明用於產生具有一可調間距介面之一封 裝之程序之一流程圖。 【主要元件符號說明】 經製造晶粒 . 149183.doc -17- 201121016 104 附接晶粒 106 基板 108 接線 110 接合墊 112 金屬跡線 114 通孔 116 金屬跡線 118 焊料墊/介面墊 120 焊料球 122 焊料遮罩 124 通孔 126 焊料墊 128 焊料球 130 模製化合物 202 區域202 204 區域204 302 區域302 502 經製造晶粒 504 附接晶粒 506 金屬塊 508 接合墊 510 接線 512 層壓板 514 金屬跡線 149183.doc -18· 201121016 516 通孔 518 焊料墊 520 焊料球 522 液體囊封劑 602 經製造晶粒 604 凸塊 606 多層基板 608 金屬跡線 610 通孔 612 焊料墊 614 焊料球 616 導熱膏 618 金屬蓋 620 通孔墊 622 填膠 624 額外通孔 702 基板 704 焊料墊 706 焊料球 802 基板 804 焊料墊 806 焊料墊 808 直徑 810 直徑 -19- 149183.doc 201121016 902 焊料墊 904 焊料墊 906 焊料遮罩 912 焊料墊 914 焊料墊 916 焊料遮罩 1102 區域 1104 區域 1202 區域 1204 區域 1302 區域 1304 區域 1402 區域 1502 金屬跡線 1504 開口 1602 基板 1604 區域 1606 區域 1704 區域 1706 晶粒 1708 區域 -20 149183.docThe through holes that pass through the substrate 106 can be thermally contacted with 102, in addition to being contacted by the fabricated die. 149183.doc 201121016 128 In this case, the through hole 124 can also be used as a thermal through hole. A through hole can be used as one of the electrical vias, one of the thermal vias, or both. A thermal via can be completely filled with a thermal conductor such as a metal. This provides better heat transfer if the via is only coated with a thermal conductor. Therefore, the via will then be filled with the solder mask material. An interface pad, such as an electrically coupled interface pad 118, is typically coupled to a metal trace within a printed circuit board where signals or current can be coupled to other components. In the case of a BGA package, the interface pads are referred to as solder pads. Such solder balls, such as solder balls 128 that can be used for thermal purposes, are often coupled to a single common metal line. In fact, this metal line is usually a ground plane on pCB. Figure 2 shows the metal traces on the surface of the substrate in more detail. Some exemplary traces are shown as metal traces 112 on top of substrate 106. The location of the die 102 is also indicated. In this detailed view, area 2〇2 shows where the wiring can be attached to the metal trace. The area 2〇4 shows the positions of the through holes such as the through holes 114 laid under the metal traces. Figure 3 shows the metal traces on the bottom of the substrate in more detail. Six exemplary metal traces are shown as metal traces 丨16. Each metal trace includes one of the solder pads shown as 118. Area 3 02 shows the area under the through hole. Figure 4 shows a corresponding section of the solder mask 122 covering the metal traces shown in Figure 3. The solder mask 122 covers the metal traces on the bottom of the substrate but leaves an opening for the solder bumps. Figure 5 illustrates one of the sub-cavity bga packages instead of a BGA package. The fabricated die 502 is attached to the die attach 504 to a metal block 506 that is typically made of copper 149183.doc 201121016. This configuration is upside down compared to the configuration of Figure 1. Wiring 5 10 is coupled to fabricated die 502 through bond pads 508. Wiring 5 10 is also attached to laminate 512. The laminate 512 includes metal traces 514 and vias 516. The wire 510 is specifically connected to the metal trace 514. The via 516 connects the metal trace 514 to the tp magazine 518 and the solder ball 520 » the lid or the liquid encapsulant (522) completes the package. Figure 6 illustrates a bga package using a flip chip attachment. The manufactured crystal 602 is attached to the multilayer substrate 606. The flip chip attachment not only provides physical attachment of the fabricated wafer 602 to one of the multilayer substrates 606, but also provides electrical contact between the fabricated die 602 and the multilayer substrate 606. The fabricated dies 6 〇 2 are attached to the via pads 62 使用 using bumps 604 instead of using wires. The via pad 62 is then attached to the via shown by the via 61 本文 herein. Thereafter, the interface including the bumps 604 between the fabricated die 602 and the substrate 606 is encapsulated by the fill 622. The package uses the metal traces 608 and the additional vias 6 2 4 to pass through the substrate 606. The die 602 is wound from the fabricated die 612 to the solder bump 612. Solder balls 614 are attached to solder pads 612 in the factory. The package is completed with a thermal paste 616 and a metal cover 618. Although implementation may be more complicated, the thermal interface can also be used in cavity BGA and flip chip attached BGA packages. • Figure 7 shows an exemplary solder ball pattern for a BGA package. Substrate 702 is shown to include a plurality of solder pads 704. On each of the solder pads is a solder ball 'indicated by solder balls 7 〇 6 in the figure. In this particular example, the solder balls do not cover the entire substrate of the substrate. This is better for some forms of BGa packaging. Figure 8 shows another solder ball pattern of a BGA package. Substrate 802 is shown to include a plurality of solder pads represented by solder pads 8A4. 149183.doc 201121016 On each solder pad is a solder ball 8〇6. In the enlarged view, for the sake of clarity, some solder pads are shown as not having a ball of paint. More clearly, only the solder pads that are left exposed by the solder mask are shown. It should be understood that in this and subsequent figures - the solder mask can be rendered to expose only the solder pads in the metal trace layer above. Each solder pad has one of the relatively uniform straight k & The ball also has a substantially uniform diameter as shown at 810. In addition, the distance between the centers of adjacent solder balls or the center of the equivalent solder pads is referred to as the pitch 812. It is worth mentioning that there is also a BGA package defined by a non-solder mask. The key difference between a BGA defined by a non-solder mask is the degree of exposure in the solder mask. Figure 9A shows a close up view of the BGA package defined by the solder mask. This is essentially the same as the bga package described above. Solder pad 902 provides a contact point for solder ball 904. The dip mask 9〇6 provides an opening for the solder ball 904. In fact, the solder ball can fill the entire opening provided by the solder mask 906. Figure 9B shows a close up view of a non-solder mask defined BGA package. Unlike the BGA package defined by the solder mask, solder balls 914 are located on solder pads 912 and potentially surround solder pads 912. In this case, the solder mask 916 has a larger opening than the solder pads. Regardless of whether a BGA defined by a solder mask or a BGA defined by a non-solder mask is used, the principles discussed for heat transfer still apply. Although the use of thermal vias to extract titanium from the fabricated grains|forklift thermograviity can contribute to heat dissipation' but it has its limitations. First, the number of solder pads that can be used for thermal purposes is limited by the number of solder pads that are required to be electrically connected to the fabricated die. 149183.doc 201121016 So if there are 1 塾 solder 塾, but 88 electrical connections are needed, only 12 can be used for thermal purposes. The number of solder pads can be increased by reducing the pitch. However, this can constitute an increase in the package and the PCB used to communicate with the package. • I t 胄 & 疋 because thin-sized traces and vias must be used for routing. For lower yields caused by short circuits or open circuits, the assembly of fine pitch BGAs can also be more challenging. Other methods have attempted to address this heat dissipation problem by adding a heat sink to the package; molding the compound with a higher thermal conductivity; increasing the number of layers or sizes of the package or attaching the epoxy using a higher thermal conductivity die. In some extreme cases, the grain size is increased to improve heat dissipation. However, such efforts are very expensive and negatively affect the profitability of the product, coupled with the conviction of the proven multi-sound device. Therefore, inexpensive packaging techniques are needed in the industry to improve heat dissipation. SUMMARY OF THE INVENTION In an array interface package such as BGA, PGA, cylindrical grid array (CGA), and planar grid array (LGA), the inter-frame spacing can be arrayed. A semiconductor package includes a die that is attached to one of the substrates. The top surface of the substrate contains metal traces that are commonly used to conduct electrical signals into the vias in the substrate. The bottom surface of the substrate also includes metal traces connecting the vias to an interface which can be a pin or a solder pad. The interfaces can be separated by at least two spacings. A solder mask is applied to the bottom of the substrate as needed to prevent knowledge. The solder mask has openings corresponding to the solder pads. If the solder pads have an adjustable pitch, then the solder mask openings also have an adjustable pitch. Then solder balls can be placed on the solder pads. The distance between the solder balls is the same as the distance between the corresponding solder pads. ^ ^Electrical vias or vias for conducting electrical signals are only coated with conductors on their walls. In contrast, thermal vias are filled with conductors to enable them to conduct more heat away from the die. In addition, the solder pads coupled to the thermal vias can be packaged more together and thus are ideal candidates for higher pitch interfaces. Additional package types are also available in an adjustable pitch array layout including flip chip BGA, lower cavity BGA, PGA^LGA. Other systems, methods, features, and advantages of the present disclosure will be apparent to those skilled in the art. All such additional systems, methods, features, and advantages are intended to be included within the scope of the present disclosure and are protected by the scope of the appended claims. [Embodiment] Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, but the focus is on a clear understanding of the principles of the disclosure. Moreover, in the drawings, the same reference numerals are used throughout the drawings. A detailed description of one of the embodiments of the present invention is presented below. The present disclosure will be described in conjunction with the drawings, but the disclosure is not intended to be limited to the embodiments disclosed herein. Rather, the invention is to cover all alternatives, modifications, and equivalents of the present invention as defined by the appended claims. Figure 10 shows a bottom view of one of the packages with an adjustable pitch 1/〇 interface. 149183.doc •10- 201121016 This package can be any of the array technologies such as BGA, PGA and/or LGA, but for the purposes of this article, examples of BGA are used. Further, a package similar to that described in Fig. 1 is used as an example. However, the average technician will understand its applicability to alternative array packages such as PGA and LGA and different BGA configurations such as CBGA and overlay BGA. In Figure 11, the region Π02 is most directly located below the fabricated die. In a multi-layer substrate, as shown in Figure 1, the area underlying the fabricated die is least suitable for routing electrical signals but is most suitable for heat transfer. A fine pitch array below the fabricated crystal grain allows a larger number of solder balls per unit area, which increases the thermal path from the die to the pcB on which the die is mounted. Use outside the zone 1102 to allow for a more economical electrical winding of one of the coarse pitches. Because of the wider spacing, the trace width, trace spacing, and the size of the electroporation perforations can be larger, resulting in higher component yields. Using Adjustable Spacing - Difficulty To allow for: level assembly, the solder balls must be the same size to illustrate the cross-section of the package using solder balls of different sizes. It is assumed that the region UG4 has a solder ball having a coarse pitch larger than a solder ball having a fine pitch in the region 11G2. Because the solders are of the same diameter, the smaller solder material is in contact with the underlying pcB, so that it is not possible to phase the heat of the solder balls, or the solder balls in the region 1104 are subjected to compression during (4) (4). The solder can overflow and be in electrical contact with adjacent solder balls. Therefore, in order for this type of package to be effective, a uniform solder ball flatness should be maintained. Hanging ‘Recommendation—The given solder ball size is used for a range of grid array spacing. For example, 'the same solder ball size is usually used for (four) meters and 1 〇 149183.doc 201121016 meters pitch. For example, 500 micron or 600 micron solder balls can be used in 〇 8 mm or 1.0 mm pitch applications. Since the number of balls is proportional to the square of the pitch size, the 0.8 mm pitch for heat dissipation allows an increase in the number of balls exceeding 40%. Figure 2 illustrates a cross section of a package in which the same ball size is used for the two pitches shown. In the area 12〇2, a fine pitch, such as 88 mm, is used. In region 1204, a coarse pitch, such as 1 〇 millimeter, is used. In Fig. 12, the same ball size is used for the gate distance in the region 12〇2 and the region 12(10). In the special region, the higher density of the ball is required, and the ball size recommended for the fine pitch can be used. Figure 13 illustrates this example in which a spacing, even finer than the spacing shown in Figure 2, is used in region 1 302. Usually, it is recommended - a smaller ball size for fine pitch. However, due to thermal fatigue, the smaller ball size suffers from lower reliability issues, and the package using the smaller ball size will have a higher failure rate in the drop test. & avoids the situation shown in Figure 11 'This smaller ball size can be used for all regions containing areas with a coarse pitch and will typically use a suggested larger ball size 1304. The primary rationale for using the smaller of the two ball sizes suggested for each respective region is to avoid electrical contact between the balls when they are heated and attached to the pc. This will prevent a short circuit. However, as shown in Fig. 若, if the area with a fine pitch is used for the hot item @, the larger of the two balls can be used. Compared to the smaller ball size, the larger ball size will help more heat conduction 1 for the solder balls in the region and the corresponding via holes to be hot (4), so the contact between adjacent solders There will be no negative impacts of 149183.doc •12- 201121016. In general, another difficulty in using fine pitch arrays, such as metal traces of traces on the bottom surface of the substrate, must have thin lines and, in addition, the solder pads potentially have less spacing between them, which results in lower Yield and/or cost of packaging. However, if the fine pitch region of an adjustable pitch package is used only for thermal purposes, it is not necessary to maintain separate metal traces for each solder pad. Figure 15 illustrates that the metal trace '纟' includes a plurality of solder pads in a fine pitch region of an adjustable pitch package. The metal trace 15〇2 in this example actually includes all of the solder pads in the fine pitch region. The areas indicated by openings 1504 represent the openings left by the solder. (For clarity, only some of these openings are marked). Since it is hot (four), it is not necessary to electrically separate the solder pads, and a single-metal trace or a plurality of large metal traces may include the solder pads in the fine pitch region. If a certain dielectric © is required in the fine pitch region, the corresponding solder bumps may be formed by metal traces separated from the metal traces for the thermal interface. Although the above-mentioned leans imply the use of fine pitches in the central region, the use of adjustable gate distances can be applied anywhere on the bottom of the package. Figure 16 shows an example of one of two regions using fine pitch. In particular, the area of the solder pad/solder ball has a finer pitch than the tantalum/solder ball on the remaining area of the substrate 1602. The two regions may represent a substrate below the two individual dies of the multi-die 1 . Although not necessary, a thermal via is provided under the attached niobium for cooling one of the effective solder ball configurations. Therefore, the right-day granules are attached to the regions 1 604 and 1 606, and one of the solder balls is more finely spaced from the array to promote cooling. 149183.doc -13- 201121016 Electrically, the adjustable pitch package may also be useful #. Typically, the bond pads are substantially equally spaced apart on the surface of a die. The internal circuitry of the crystal must wrap the signal to its respective junction. The satisfaction of the requirements caused by the junctions may require further routing of the metal traces to relax these requirements. The number of metal traces in the feed can be potentially reduced. In fact, it is possible to eliminate several metal trace layers, thereby reducing the cost of manufacturing a die and/or substrate. Figure 17 shows the use of adjustable pitch to relax the pair One example of the entanglement of the die is a dummy example. In this example, the die 17〇6 is shown in a schematic view. For the sake of clarity, any solder pads and solder balls under the die 1706 are not shown. The die 1706 device may require one bond pad on each side of the die, but 150 in the region 1708. This may cause difficulty in routing around the side of the region 17A8 because it will The extra 1/〇 that is not required on the package side is left to the designer's only choice, and the package does not use a fine pitch to obtain an additional interface' in order to borrow a package interface (eg solder from the other side of the package) Ball) and 1/0 Sent to the borrowed interface. Instead, the use of a fine pitch to provide an additional interface in the area 17 〇 4 makes the routing easier, and since the traces do not have to be routed to the other side of the package, Therefore, the trace resistance and inductance are low and the performance is not degraded. Unbalanced I/O conditions can occur especially in multi-chip packages. Because fine pitch is used for only a portion of the package, it is applied by a fine pitch interface. The higher limit requirement applies only to one portion of the package's, thus making it easier to manufacture on a package with fine pitch. Figure 18 shows an illustration for generating a 149183.doc-14 with an adjustable pitch interface. A flow chart of 201121016. It will be noted by those skilled in the art that not all steps need to be performed in the stated order and many steps can be performed in a different order. At step 18〇2, vias are formed in a substrate. This is usually done by Drilling is performed. A conductive material is applied to the via at step 1804. In the case of electrical vias, the conductors typically coat the walls of the via and in the case of thermal vias The conductors fill the via. At step 1806, metal traces are formed on top of the substrate providing a location for a wire and the metal traces are connected to at least some of the vias. At step 8 (), a metal trace is formed on the bottom of the substrate, wherein the metal traces comprise an interface pad of the array. The interface pads include at least two regions, a thick region (where the interface pads are Separating further away and a thin area (where the interface pads are spaced closer together). At step 1810, a solder mask is applied to the bottom of the substrate having openings that are exposed in the thick regions The interface pads and the interface pads in the thin regions. The die is attached to the substrate at step 1812. At step 1814, the wires are attached to the pads on the i-die and attached to the substrate The metal traces on the top. Alternatively, the die can be crystallized onto the metal traces on the top of the via pads or substrate. The mold, the wiring and the top of the substrate are encapsulated at the step UK using a molding compound. At step 1818, an array of interfaces, such as solder balls, is attached to the interface 塾, the solder balls are tied in the fine regions, spaced apart and separated in a thick region. Farther. in? (In the case of eight cases, a one-pin array can be attached to the interface 塾. In the case of CGA, an array of cylinders can be attached to the interface pads. In the case of LGA, the interfaces are themselves such interfaces 149183.doc -15- 201121016 Because the manufacturing technique using the adjustable pitch interface uses existing manufacturing techniques and only requires modification of the design of the metal trace layer under the substrate, placing the interfaces, modifying the design of the solder mask and The interface is placed so that no significant additional manufacturing costs are incurred. An improvement in package heat dissipation of 2% to 5°/. has been observed with a tunable pitch BGA package. Although this thermal improvement may seem small, this difference can be Affecting the cost of packaging from 5% to 15%, and/or affecting the amount of functionality or speed that a device can accommodate. As mentioned above, in addition to the multilayer substrate BGA shown, the adjustable pitch interface can also be used to use an interface array ( In any packaging technique such as the BGA described above and other types of PGA and LGA, it should be emphasized that the above-described embodiments are merely examples of possible implementations. By way of example, the embodiments described are in the context of a BGA, but may be PGA, LGA, or other packages that use an array interface. Those skilled in the art will appreciate that they can readily use the disclosed concepts and specific embodiments as a basis for designing or modifying other structures to achieve the teachings herein. The same purpose is to be understood by those skilled in the art that various changes, substitutions and changes can be made herein without departing from the spirit and scope of the invention. And variations are intended to be included within the scope of this disclosure and are protected by the scope of the following claims. [FIG. 1 illustrates a cross section of a typical wired BGA package; FIG. 2 shows in more detail. Metal traces on the surface of the substrate; Figure 3 shows the metal traces on the bottom of the substrate in more detail; 149183.doc •16· 201121016 Figure 4 shows the section covering Figure 3; one of the metal traces shown as solder mask Figure 5 illustrates one of the - cavity BGA packages instead of the hidden package; Figure 6 illustrates the use of a flip chip attached - BGA package; Figure 7 shows the B GA package One exemplary solder ball pattern; Figure 8 shows another solder ball pattern of the BGA package; Figure 9A shows a close up view of the solder mask BGA package; Figure 9B shows - non-solder mask bga package - close up view Figure 10 shows a bottom view of one of the packages with an adjustable pitch 1/〇 interface; Figure 11 illustrates a package using one of the different ball sizes - Figure 12 illustrates the same ball size for the two spacings shown One of the packages is a section; Figure 13 illustrates a section of the package. Where the interface is a fine pitch, the larger of the two balls is used for thermal purposes; Figure "Illustration-metal traces, a plurality of solder pads including a fine pitch region of a tunable pitch package; Figure 15 shows a metal trace comprising one of the solder pads stacked thereon; Figure 16 shows an example of two regions using fine pitch; Figure 17 shows a hypothetical example of the use of adjustable spacing to relax the routing requirements for the die; and Figure 18 shows a flow chart illustrating one of the procedures for producing a package having an adjustable pitch interface. [Major component symbol description] Fabric Manufactured. 149183.doc -17- 201121016 104 Attached die 106 Substrate 108 Wiring 110 Bonding pad 112 Metal trace 114 Through hole 116 Metal trace 118 Solder pad / interface pad 120 Solder ball 122 solder mask 124 via 126 solder pad 128 solder ball 130 molding compound 202 region 202 204 region 204 302 region 302 502 fabricated die 504 attached die 506 metal block 508 bond pad 510 wire 512 laminate 514 metal trace Line 149183.doc -18· 201121016 516 Via 518 solder pad 520 solder ball 522 liquid encapsulant 602 fabricated die 604 bump 606 multilayer substrate 608 metal trace 610 via 612 solder pad 614 solder ball 616 thermal paste 618 Metal Cover 620 Via Hole 622 Filler 624 Additional Through Hole 702 Substrate 704 Solder Pad 706 Solder Ball 802 Substrate 804 Solder Pad 806 Solder Pad 808 Diameter 810 Diameter -19- 149183.doc 201121016 902 Solder Pad 904 Solder Pad 906 Solder Mask 912 solder pad 914 solder pad 916 solder mask 1102 area 1104 area 1202 area Area 1302 1304 1204 region region region 1502 1402 1504 metal traces opening region 1602 of the substrate 1604 1606 1704 region region region 1706 1708 -20 149183.doc grain

Claims (1)

201121016 七、申請專利範圍： 1. 一種半導體封裝，其包括： 一半導體晶粒； 具有一頂面及一底面之一基板，該基板包括若干含有 一導體之通孔； 在5亥基板頂面上之若干金屬跡線； 在該底面上若干包含介面墊之金屬跡線； 其中該底面上之諸金屬跡線耦合該等介面墊至該等通 孔；及 其中該底面包括-第—區域及_第二區域且該第—區 域中之該等介面墊係以一第—間距隔開且該第二區域中 之該等介面墊係以一第二間距隔開。 2. 如請求項1之半導體封裝，其進一步包括： 焊料遮罩’其具有在各介面墊下之一開口；其中在 :第-區域中該焊料遮罩中之該等開口係以該第二間距 隔開’且在該第二區域中該焊料遮罩係以該第二間距隔 3.如請求項1之半導體封裝 墊之一焊料球。 4·如請求項1之半導體封裝5. 如請求項1之半導體封裝 6. 如請求項丨之半導體封裝 7. 如請求項丨之半導體封裝 8·如請求項丨之半導體封裝 •其進一步包括耦合至各介面 其中該封裝係一覆晶BGA。 其中該封裝係一下腔BGA。 其中該封裝係一 PGA或CGA. 其中該封裝係一 LGA。 其中頂部基板上之該等金屬 I49183.doc 201121016 跡線包括諸接合指狀物且諸接_合該晶粒至該等接合 指狀物。 9.如請求項1之半導體封纟，其中該頂部基板上之該等金 屬跡線包括若干通孔墊且該晶粒係覆晶連接至該等通孔 墊。 !〇•如請求項!之半導體封裝’其中該等通孔包括諸電通孔 及熱通孔且在該第—區域中該等介面塾係福合至諸電通 孔及在該第二區域中諸介面墊係耦合至諸熱通孔。 11. 如請求項10之半導體封裝，其中該等電通孔具有以一導 體塗覆之各壁且該等熱通孔係以一導體填滿。 12. —種用於封裝一半導體晶粒之方法，其包括： 在具有一頂面與一底面並具有一第一區域與一第二區 域之一基板中產生若干通孔； 添加導體至該等通孔； 在該頂面上形成若干金屬跡線； 在該底面上形成若干金屬跡線，其中該等金屬跡線包 括在該第一區域中以一第一間距隔開之若干介面墊及在 S亥第二區域中以一第二間距隔開之若干介面墊； 附接該半導體晶粒至該頂面； 電連接該半導體晶粒至該頂面上之該等金屬跡線；及 囊封该封裝於一模製化合物中。 13.如清求項12之方法，丨中在該頂面上之該等金屬跡線包 括右干接合指狀物且該電連接包括在該晶粒與該等接合 指狀物之間附接若干接線。 149183.doc 201121016 14. 如請求項12之方法，其中在該頂面上之該等金屬跡線包 括若干通孔墊且該電連接包括覆晶連接該晶粒至該等通 孔墊上。 15. 如請求項12之方法，其進一步包括形成一焊料遮罩以覆 盍在該底面上之s亥等金屬跡線，其中該焊料遮罩在各介 面墊下方具有若干開口。 16. 如請求項12之方法，其進一步包括在各介面墊下方附加 一引腳。 17. 如凊求項12之方法，其進一步包括附接一焊料球至各介 面塾。 17. 如請求項12之方法，其中該等通孔具有各壁且其中添加 導體至該等通孔包括以—導體塗覆該等通孔之該等壁。 18. 如請求項12之方法，其中添加導體至該等通孔包括n 導體填滿該等通孔。 19_ 一種半導體封裝’其包括： 一半導體晶粒； 具有-頂面及-底面之一基板，該基板包括若干通 孔； 用於電連接該晶粒至該等通孔之構件； 於該底面上之若干介面墊； 用於連接該等介面塾至料通孔之構件； 。其中該底面包括-第-區域及-第二區域且在該第一 區域中該等介面塾係以—第一 _ .^ 第一間距隔開及在該第二區域 中该專介面墊係以一第二間距隔開。 149183.doc 201121016 20.如請求項19之半導體封裝，其進一步包括： 一遮罩構件，其係用於覆蓋該底面，且包括各介面墊 下方之若干開口。 149183.doc201121016 VII. Patent application scope: 1. A semiconductor package comprising: a semiconductor die; a substrate having a top surface and a bottom surface, the substrate comprising a plurality of through holes including a conductor; a plurality of metal traces; a plurality of metal traces including an interface pad on the bottom surface; wherein the metal traces on the bottom surface couple the interface pads to the vias; and wherein the bottom surface includes a - region and The second regions and the interface pads in the first region are separated by a first spacing and the interface pads in the second region are separated by a second spacing. 2. The semiconductor package of claim 1, further comprising: a solder mask having an opening under each of the interface pads; wherein wherein the openings in the solder mask are in the second region The solder spacers are spaced apart from each other and in the second region the solder mask is separated by a solder ball of one of the semiconductor package pads of claim 1. 4. The semiconductor package of claim 1 5. The semiconductor package of claim 1 6. The semiconductor package of claim 1. The semiconductor package of claim 8 8. The semiconductor package of claim • • further includes coupling To each interface, the package is a flip chip BGA. The package is a cavity BGA. The package is a PGA or CGA. The package is an LGA. The metal I49183.doc 201121016 trace on the top substrate includes bond fingers and the die are joined to the bond fingers. 9. The semiconductor package of claim 1 wherein the metal traces on the top substrate comprise a plurality of via pads and the die is flip chip bonded to the via pads. The semiconductor package of the present invention, wherein the vias include electrical vias and thermal vias, and in the first region, the interfaces are bonded to the vias and in the second region The interface pads are coupled to the thermal vias. 11. The semiconductor package of claim 10, wherein the electrical vias have walls coated with a conductor and the thermal vias are filled with a conductor. 12. A method for packaging a semiconductor die, comprising: creating a plurality of vias in a substrate having a top surface and a bottom surface and having a first region and a second region; adding a conductor to the a plurality of metal traces are formed on the top surface; a plurality of metal traces are formed on the bottom surface, wherein the metal traces comprise a plurality of interface pads spaced apart by a first pitch in the first region and a plurality of interface pads separated by a second pitch in the second region of the S; attaching the semiconductor die to the top surface; electrically connecting the semiconductor die to the metal traces on the top surface; and encapsulating The package is in a molding compound. 13. The method of claim 12, wherein the metal traces on the top surface comprise right dry bonding fingers and the electrical connection comprises attaching between the die and the bonding fingers Several wiring. 14. The method of claim 12, wherein the metal traces on the top surface comprise a plurality of via pads and the electrical connection comprises flip chip bonding the die to the via pads. 15. The method of claim 12, further comprising forming a solder mask to cover the metal traces on the bottom surface, wherein the solder mask has a plurality of openings under each of the interface pads. 16. The method of claim 12, further comprising attaching a pin under each of the interface pads. 17. The method of claim 12, further comprising attaching a solder ball to each of the interface defects. 17. The method of claim 12, wherein the through holes have walls and wherein the addition of conductors to the through holes comprises coating the walls of the through holes with a conductor. 18. The method of claim 12, wherein adding a conductor to the vias comprises n conductors filling the vias. 19_ A semiconductor package comprising: a semiconductor die; a substrate having a top surface and a bottom surface, the substrate comprising a plurality of via holes; a member for electrically connecting the die to the via holes; a plurality of interface pads; members for connecting the interfaces to the material through holes; Wherein the bottom surface includes a -first region and a second region, and in the first region, the interface interfaces are separated by a first spacing and in the second region the dedicated interface is A second spacing is spaced apart. 20. The semiconductor package of claim 19, further comprising: a mask member for covering the bottom surface and including a plurality of openings below each of the interface pads. 149183.doc
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