CN103165472A - Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method - Google Patents
Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method Download PDFInfo
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- CN103165472A CN103165472A CN201110421731XA CN201110421731A CN103165472A CN 103165472 A CN103165472 A CN 103165472A CN 201110421731X A CN201110421731X A CN 201110421731XA CN 201110421731 A CN201110421731 A CN 201110421731A CN 103165472 A CN103165472 A CN 103165472A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The invention relates to a fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method. The FC-BGA packaging bump distributed heat dissipation novel method is characterized in that: effectively solving a heat dissipation problem of a partial hot spot according to different distribution of bumps; plating a layer of metal on a substrate of a chip through under bum metal (UBM); rationally and quickly conducting heat out through corresponding bump distribution, and therefore heat quantity of the chip is reduced, heat balance of the chip is achieved as soon as possible, and a stationary field of a whole packaging system achieves a stable state. In an FC-BGA structure, the bumps are mainly used for heat dissipation. By applying of a Solidworks software to conduct solid modeling, a model can simulate a structure stable temperature field and a transient temperature field, and find out positions of key bumps, namely bumps with high temperature, and classify positions of the bumps, and then bump distribution is adjusted, bump distribution density is appropriately increased in a position of an original bump with high temperature, and eventually heat is rationally and quickly transmitted to a substrate through the bumps and then dissipated outside.
Description
Technical field
The present invention relates to the heat dissipation new method that a kind of FC-BGA encapsulation salient point distributes, relate more specifically to carry out salient point position classification according to the difference of salient point temperature, and then the adjustment salient point distributes, the salient point location-appropriate higher in original temperature improves the salient point distribution density, heat rationally and is promptly conducted, thereby reduce the heat of chip, make chip reach as early as possible heat balance, whole package system stationary field reaches stable state.
Technical background
FC-BGA (Flip Chip Ball Grid Array) is the flip-chip ball grid array package namely, is the high-end Advanced Packaging form of present a kind of main flow, is mainly used in drawing the more jumbo chip of pin.The photo of the graphics accelerator chip of employing FC-BGA encapsulation as shown in Figure 1.
FC-BGA has gathered the advantage of ball-type encapsulation and Flip-Chip Using technology, and at first, it has solved electromagnetic compatibility (EMC) and electromagnetic interference (EMI) problem.Generally speaking, the chip of the Wire Bond encapsulation technology before adopting, its signal transmission is to see through the metal wire with certain-length to carry out, this method forms an obstacle on the signal course in the situation that high frequency can produce so-called impedance effect, but FC-BGA replaces original stitch that adopts to connect processor with bead, 479 balls have been used in this encapsulation altogether, but diameter is 0.78 millimeter, and the shortest external connection distance can be provided.Figure 2 shows that the exemplary block diagram of the FC-BGA encapsulation of organic material base plate strip copper alloy dissipating cover, its composition comprises: Adhesive (adhesive), Underfill (bottom filling), Solder Bump (solder bump), Die (chip), Capacitor (capacitor), CuAlloy Lid (copper alloy dissipating cover), Solder Ball (tin ball), Organic Substrate (organic material substrate).Adopt this encapsulation that excellent electrical property efficiency not only is provided, can reduce loss and inductance between assembly interconnect simultaneously, reduce the problem of electromagnetic interference, and bear higher frequency, break through the overclocking limit and may just become.
Secondly, when the designer of display chip embedded more and more intensive circuit in identical silicon wafer zone, the quantity of input and output terminal and stitch will increase sharply, and another advantage of FC-BGA is to improve the density of I/O.Generally speaking, adopting the I/O lead-in wire of Wire Bond technology is all the surrounding that is arranged in chip, but after adopting the FC-BGA encapsulation, the I/O lead-in wire can be arranged in the mode of array the surface of chip, more highdensity I/O layout is provided, produce best service efficiency, also because of this advantage, flip chip technology is compared to conventional package form area reducing 30% to 60%.
The heat management of Electronic Packaging refers to reasonably cooling/heat dissipation technology and structural design optimization that the heat dissipation element in packaging body and system are adopted, its temperature is controlled, thereby guarantee electronic device or system normally, work reliably.
Origin of heat in packaging body mainly contains two aspects, the one, electric current flows in the package interior chip, be heat energy with electric energy conversion, all can produce heat after the energisings such as lead-in wire, resistance, polysilicon, particularly the heat of the core devices of some high functional densities (as CPU) generation is more many; The 2nd, the fricative heat of the flowable parts of package interior is as micro mirror array etc.Along with constantly gathering of heat, if do not have effective circulation path that heat is taken away, the temperature in packaging body will constantly rise, until electronic device quits work or complete failure till.
In the BGA structure, the heat that chip produces mainly transmits by two kinds of approach, be intrinsic pathways and extrinsic pathways, intrinsic pathways mainly comprises two aspects: the one, in the process of heat by the outside transmission in chip interface, at first running into the heat transfer resistance of semiconductor itself, is then that chip is with the heat transfer resistance of the tack coat between substrate; The 2nd, after hot-fluid arrives substrate, overcome the thermal-conduction resistance of substrate, the thermal-conduction resistance of shell, thereby the outer surface of arrival shell.In addition, some form by convection current and radiation of the heat of the generation of thermal source, pass encapsulation inner space arrival inner surface of outer cover, the thermal-conduction resistance that overcomes again shell arrives outer surface, but because the thermal resistance that encapsulates the inner space is generally all larger, thereby the hot-fluid on this path can be ignored.The extrinsic pathways of hot-fluid transmission is mainly after the heat of chip generation conducts to the encapsulation outer surface, to go in the mode by convection current and radiation spills into environment.Be the simulation schematic diagram of the heat dissipation situation of FC-BGA encapsulating structure as Fig. 3, about 98.5% heat is by chip and substrate and middle this paths of salient point, so the heat radiation of this approach accounts for dominating role, and the present invention is also with significant.
High speed in a new generation, in the display chip of high degree of integration, heat dissipation problem will be a large challenge.Based on the packing forms that falls of FC-BGA uniqueness, the back side of chip can touch air, can directly dispel the heat.Simultaneously substrate also can see through metal level and improve radiating efficiency, installs metal fin additional at the chip back, further strengthens the ability of chip cooling, increases substantially the stability of chip when high-speed cruising.At present, analysis mainly concentrates on chip size [1] to FC-BGA encapsulation Thermal Properties, the substrate number of plies, the substrate conductive coefficient, the conductive coefficient of heat-conducting resin and heat dissipation metal lid adhesive, on the factors such as heat dissipation metal lid structural parameters [2], be thermal resistance with air velocity in the different substrate number of plies and have or not curve chart in external heat radiation sheet situation as Fig. 4, Fig. 5 is junction temperature with circumstance of temperature difference and substrate conductive coefficient at the curve relation figure [3] that has or not in external heat radiation sheet situation.
Can be by the selection of baseplate material in existing research, the selection of the substrate number of plies, the means such as the placement of fin improve the heat-sinking capability of FC-BGA encapsulation, the proposition of the present invention's innovation, distribution by salient point improves the encapsulation chips with the ability of heat dissipation between substrate, and then improves the heat dissipation ability of whole package system.
Along with the particularly fast development of very lagre scale integrated circuit (VLSIC) of integrated circuit, the volume of electronic devices and components is more and more less, meanwhile, the power of chip is increasing, this causes the density of heat flow rate in packaging body day by day to improve, 20 century 70s are between the nineties, and the density of heat flow rate in integrated circuit (IC) chip is from about 10W*cm
-2Be increased to 100W*cm
-2Magnitude, the trend that current this numerical value increases is illustrated in figure 6 as chip maximum heat current density growth trend still continuing, and so large energy density, if can not reasonably carry out the heat management design, will cause the inefficacy of microprocessor.
Statistics is pointed out, the reason that the electronic product generation was lost efficacy, and nearly 55% is because overheated and relevant to heat problem causes.The inefficacy of electronic device is often closely related with its working temperature, and in certain temperature range, along with the rising of temperature, the failure rate of electronic device sharply rises.The failure rate that studies show that device increases along with the rising of temperature is exponential trend.High temperature will bring a series of impacts to electronic devices and components: electronic packing body is to be made of the different material of thermal coefficient of expansion, is producing, and makes, and the processes such as test can produce by thermal coefficient of expansion does not mate and the thermal stress that causes; Significantly temperature fluctuation will cause the fatigue fracture of encapsulating material; The change of temperature will cause the variation of the current gain of transistor and integrated circuit, and the capacitance of bringing thus, the change of resistance etc. will affect the transmission characteristic of the signal of telecommunication etc.
The skewness of chip power density can produce so-called hot localised points, adopt traditional heat dissipation technology can not satisfy the thermal design of present Advanced Electronic Encapsulating, management and demand for control, it has not only limited the increase of chip power, also can bring unnecessary energy waste because of sub-cooled.Therefore the method for the salient point distribution of a kind of FC-BGA encapsulation of the proposition of the present invention's innovation is effectively improved the heat dissipation problems of hot localised points, the heat that the chip diverse location is produced, distribute rationally and rapidly by corresponding salient point and conduct, thereby reduce the heat of chip, make chip reach as early as possible heat balance, whole package system stationary field reaches stable state.
Summary of the invention
The present invention adjusts salient point according to the temperature of salient point position and distributes, and makes chip amount of localized heat higher place, and corresponding salient point distribution density is larger, the place that the chip amount of localized heat is relatively low, and the salient point distribution density is less, and heat is conducted rapidly.
Figure 7 shows that FC-BGA encapsulating structure salient point schematic diagram, its part comprises: LSI chip (LSI chip), Solder Bump (solder bump), Heat Spreader (radiator), Underfill Resin (bottom potting resin), Stiffener (curing agent), Build-up Layer (building layer), Core Layer (core layer).The popular feature of flip-chip syndeton be chip all face down be attached on substrate, what chip was connected connection use with substrate is the salient point that electric conducting material is made, the flip-chip connection of using and be not connected to use lower filler in general minute.When not using lower filler, chip is with connecting by salient point between substrate, conduct electricity characteristic and heat, when using lower filler, the anisotropy that lower filler is arranged, the selection of isotropy or insulating adhesive and different connection process structures is arranged, salient point still has material impact therein.
For chip and salient point, between salient point and substrate, heat transfer is mainly in heat conducting mode.Heat conduction problem in encapsulation can represent with the one dimension Fourier equation:
In formula, q is density of heat flow rate; K is thermal conductivity; A is the area of section perpendicular to direction of heat flow;
Temperature gradient on direction of heat flow; Negative sign represents heat direction of transfer and temperature rising opposite direction.
Can find out heat conduction and the Ohm's law of electric current through conductor from the Fourier equation that conducts heat
Very similar, wherein, hot-fluid q is similar to electric current I, and temperature drop Δ T is similar to voltage drop Δ V.Therefore can define thermal resistance is:
In circuit, resistance represents the size of the suffered resistance of current flowing.Same, in the heat conduction, the thermal resistance representative be the drag size of heat flow.The same temperature difference, thermal resistance is larger, and heat more is not easy transmission.Thermal resistance is important technology index and the characteristic of Electronic Packaging, is also the most frequently used evaluating during heat is analyzed.The purpose of thermal design wishes that exactly encapsulating structure can be easy to heat radiation, makes its thermal resistance the smaller the better.
Main wafer scale salient point is processed as evaporation scolding tin salient point, plated solder salient point and printing soldering viscosity salient point at present.The scolding tin salient point uses thinner improvement ball bonding device, and also uses the lead-in wire of soldering alloy material.
Ubm layer (UBM) is deposited on the chip substrate zone, forms and flip chip bonding is a key factor for salient point.Ubm layer has a lot of functions, and it must possess enough good support substrate plating ability, and coated metal is generally aluminium, and it must as diffusion barrier in the soldering process, keep the good wettability of soldering material, and prevent surface oxidation.To use different salient point metallization for different salient point processing.
The maximum temperature of suggestion welding in filler is 140 ℃ under not using, using lower filler is 150 ℃.The thermal resistance of each weld is 1000-1500 ℃/W.Thermal resistance by flip chip bonding from the chip to the substrate can rough calculation be thermal resistance on each salient point divided by the salient point number on chip, extra salient point number can increase refrigerating efficiency, also can use the lower filler of high thermal conductance, comes acting in conjunction, realizes highly effective refrigeration.
Consider the symmetry of structure and save time, we get 1/4 model and analyze.Model adopts Solidworks software to carry out solid modelling, because ANASYS Workbench finite element software has been set up the interface of seamless link with Solidworks, so directly the Solidworks model is imported to ANSYSWorkbench and analyzes [4].
Because whole model has more regular geometry, divide so adopt hexahedral element to carry out grid.When dividing, grid considers following principle: 1. pair part of being concerned about such as chip, adopt closeer network, to guarantee computational accuracy during grid division; 2. near estimating temperature gradient larger part such as chip, adopt than fine grid, and less part such as package casing and the PCB of temperature gradient adopts the network of dredging.So both guarantee computational accuracy, and do not caused again scale of model too huge, taken the more time.Fig. 8 is the global finite element grid chart of FC-BGA model.
The difference of the chip amount of localized heat of giving chapter and verse of the present invention's innovation, and the difference of the corresponding distribution of design salient point, the place that the chip amount of localized heat is higher, corresponding salient point distribution density is larger, the place that the chip amount of localized heat is relatively low, the salient point distribution density is less, thus rationally and promptly make heat balance be transferred to substrate dissipate away [5] by salient point.The selection of convex point material and inserts material is also very important, can have a great impact the transmission of heat and the distributed needs of salient point corresponding density.
Be illustrated in figure 9 as the position distribution schematic diagram of crucial salient point, by model to the simulation in Stability Analysis of Structures temperature field and the simulation of transient state temperature field, first even distribution salient point, then pass through the simulation to the stable distribution of salient point heat, find the position of crucial salient point, namely the position of the higher salient point of temperature.Carry out salient point position classification according to the difference of salient point temperature, and then the adjustment salient point distributes, the salient point location-appropriate higher in original temperature improves the salient point distribution density, be the high temperature key point as C point in figure, therefore, needs raising C point place salient point distribution density makes the heat of the corresponding chip local location of C point dissipate out faster.
Because the thermal coefficient of expansion of each material of packaging body is different, after variations in temperature, can cause the thermal strain of thermal stress in addition, Figure 10 is that packaging body is subjected to the thermal deformation schematic diagram.Usually packaging body structure after 135 ℃ of tin balls reflux has just been finalized the design, and when cooling to afterwards 25 ℃ of room temperatures, it is recessed downwards that packaging body is deformed into the edge, the middle situation of protruding.Therefore, we need under the circumstances, and bump density is adjusted, and namely spacing between salient point are adjusted.
Description of drawings
Fig. 1 is the photo of the graphics accelerator chip of employing FC-BGA encapsulation;
Fig. 2 is the exemplary block diagram of the FC-BGA encapsulation of organic material base plate strip copper alloy dissipating cover;
Fig. 3 is the simulation schematic diagram of the heat dissipation situation of FC-BGA encapsulating structure;
Fig. 4 is thermal resistance and air velocity in the different substrate number of plies and has or not curve chart in external heat radiation sheet situation;
Fig. 5 is junction temperature with circumstance of temperature difference and substrate conductive coefficient at the curve relation figure that has or not in external heat radiation sheet situation;
Fig. 6 is chip maximum heat current density growth trend;
Fig. 7 is FC-BGA encapsulating structure salient point schematic diagram;
Fig. 8 is the global finite element grid chart of FC-BGA model;
Fig. 9 is the position distribution schematic diagram of crucial salient point;
Figure 10 is that packaging body is subjected to the thermal deformation schematic diagram;
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is further described.
According to above-mentioned inventive principle, we simulate according to Fig. 8 model, and (the 19.7*19.7mm chip size, sample size: be 28 unit) example, the data that experiment obtains are as shown in table 1 with 45mm*45mmFC-BGA for we.
| Change parameter (mm) | The wafer maximum temperature (℃) | FR4 circuit board temperature (℃) | Entire thermal resistance R (℃/W) |
| Bump pitch 0.028 | 56.994 | 29.9784 | 45.5304 |
| Bump pitch 0.024 | 56.746 | 29.980 | 46.0489 |
| Bump pitch 0.02 | 56.273 | 29.9827 | 46.2812 |
Table 1 is the situation of change of different bump pitch lower wafer maximum temperatures/FR4 circuit board temperature/entire thermal resistance R
Can be analyzed by data in table and obtain, adjust bump pitch, namely adjust the density of this part salient point, can significantly improve the maximum temperature of wafer and temperature conditions and the total heat resistance value of FR4 circuit board, when increasing bump density, namely reduce the spacing of salient point, can significantly reduce the maximum temperature of chip, total thermal resistance is reduced, improve the heat transmittability, make the heat of chip faster, the more balanced salient point that passes through partly transfers out.The present invention is by to the consideration of local heat dissipation, avoids the chip local overheating and the chip thermal failure that causes, and the heat management of FC-BGA encapsulating structure and the heat transmission of chip are had more great improvement.
The method that the salient point distribution improves the transmission of FC-BGA encapsulation heat is adjusted in this novel passing through, and can effectively solve the hot localised points problem.Improve the refrigerating efficiency of thermoelectric material, optimize whole encapsulating structure and overall operation situation, the method is with the selection of convex point material, the selection of lower inserts material, the selection of baseplate material, the consideration of the substrate number of plies etc. combines research to be considered, can more effectively improve the heat management situation of FC-BGA encapsulating structure.
The present invention is with 45mm*45mm FC-BGA (19.7*19.7mm chip size, sample size: 28 unit) simulate explanation situation of the present invention for example, the practical examples operation is not arranged, but change this method of bump pitch, workable in packaging technology, simple to operate, and jointly consider can have to reach effect preferably by the selection of material.
Above content is in conjunction with concrete execution mode further description made for the present invention, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (6)
1. the heat dissipation new method that FC-BGA encapsulation salient point distributes, is characterized in that comprising: the heat dissipation problems of effectively improving hot localised points by the different distributions of salient point; By the substrate plating layer of metal of ubm layer UBM to chip; Distribute rationally and promptly by corresponding salient point heat is conducted, thereby the heat of reduction chip makes chip reach as early as possible heat balance, whole package system stationary field reaches stable state.
2. the method for claim 1, it is characterized in that, be connected by salient point between chip and substrate, heat dissipation situation to the encapsulation of FC-BGA structure is simulated, about 98.5% heat is by this paths of salient point of chip and substrate and centre, so the heat radiation of salient point accounts for dominating role.
3. as claim 1 and the described method of Fig. 9, it is characterized in that, carry out salient point position classification according to the difference of salient point temperature, and then the adjustment salient point distributes, the salient point location-appropriate higher in original temperature improves the salient point distribution density, find the high temperature key point, improve the salient point distribution density at this some place.
4. as claim 1 and the described method of Figure 10, it is characterized in that, because the thermal coefficient of expansion of each material of packaging body is different, after variations in temperature, can cause the thermal strain of thermal stress, cause the packaging body distortion, re-start adjustment to bump density.
5.
AsMethod claimed in claim 1 is characterized in that, ubm layer (UBM) must possess enough good support substrate plating ability, is conducive to salient point and forms and flip chip bonding, and the coated metal of general chip substrate is aluminium.
6.
AsMethod claimed in claim 1 is characterized in that, after salient point distributes and to complete, thereby rationally and promptly makes being transferred to substrate by salient point and dissipating away of heat balance.
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| CN105050371A (en) * | 2015-09-02 | 2015-11-11 | 电子科技大学 | High-heat-flux electronic equipment hot spot removing device |
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