CN101740422A - Method for fabricating bump - Google Patents
Method for fabricating bump Download PDFInfo
- Publication number
- CN101740422A CN101740422A CN200810202839A CN200810202839A CN101740422A CN 101740422 A CN101740422 A CN 101740422A CN 200810202839 A CN200810202839 A CN 200810202839A CN 200810202839 A CN200810202839 A CN 200810202839A CN 101740422 A CN101740422 A CN 101740422A
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- Prior art keywords
- layer
- chip
- solder layer
- salient point
- bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a method for fabricating a bump. The method comprises the following steps of: providing a chip on which a solder layer is formed; placing the chip in a refluxing device, wherein the solder layer is positioned below the surface of the chip; and refluxing the solder layer to form the bump. The method for fabricating the bump ensures the reliability of a metal layer below the bump; the bump does not cause a bridging phenomenon so as to avoid a short circuit; and the electrical property of a copper metal layer is improved in the fabricating process of the bump of a copper cylinder.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to the manufacture method of salient point.
Background technology
Along with the continuous development of integrated circuit technique, electronic product more and more develops to miniaturization, intellectuality, high-performance and high reliability direction.And the integrated circuit encapsulation not only directly affects integrated circuit, electronic module and even machine performance, but also is restricting miniaturization, low cost and the reliability of whole electronic system.Progressively dwindle in the integrated circuit (IC) wafer size, under the situation that integrated level improves constantly, electronics industry has proposed more and more higher requirement to the integrated circuit encapsulation technology.
Flip-chip (flip chip) technology is the soldered ball that forms by at chip surface, the chip upset is formed with base plate to be connected, thereby reduce package dimension, satisfy the high-performance (as high speed, high frequency, littler pin) of electronic product, the requirement of little profile, make product have good electric property and heat transfer property.
Salient point (bump) manufacturing technology is a key technology in the flip-chip.Salient point of the prior art be scolder by certain process deposits on chip metal bed course, the metal soldered ball that reflux to form through uniform temperature.Concrete technology is as follows: as shown in Figure 1, dispose metal bed course 104 and the passivation layer 102 in order to protect chip 100 surfaces and metal bed course 104 is exposed on chip 100; On passivation layer 102 and metal bed course 104, form screen 105 by sputter or evaporation process, the effect of described screen 105 is to keep good adhesion with metal bed course 104, and effectively stop the phase counterdiffusion of follow-up convex point material with metal bed course 104, the material of described screen 105 is constituting of a kind of in titanium, tungsten, the chromium or they; Form ubm layer 106 with sputtering method on screen 105, its effect is a protection metal bed course 104 in follow-up reflux technique, and ubm layer 106 can be constituting of a kind of among Al, Ni, Cu, Ti, Cr, Au, the Pd or they.
Then please refer to Fig. 2, on ubm layer 106, form photoresist layer 107, define metal bed course 104 shapes, expose then, developing process by existing photoetching technique, in photoresist layer 107, form opening, expose the ubm layer 106 on the metal bed course 104 of lower floor; With photoresist layer 107 is mask, forms solder layer 108 on the ubm layer 106 in opening, and the method that forms solder layer 108 is galvanoplastic, and described solder layer 108 is tin or leypewter.
With reference to figure 3, behind the removal photoresist layer 107, ubm layer 106 beyond the etching removal solder layer 108 and screen 105 are to exposing passivation layer 102; Be coated with scaling powder on solder layer 108, then, chip 100 put into reflow ovens, just placing on the hot plate, promptly the opposite face of the solder layer place face of chip 100 is placed on the hot plate top and fixes, and then is incubated backflow, forms salient point 108a.
Prior art is in the process of formation salient point that refluxes, owing to just be placed in chip on the hot plate, through behind the reflux technique, owing to gravity and capillary reason, can make convex point material penetrate into (shown in the circle among Fig. 4) in the ubm layer, thereby reduced the quality of ubm layer, influenced its reliability; In addition, in the manufacturing process of copper post salient point, the salient point below is the thicker copper metal layer of one deck, just be placed in chip on the hot plate, when the Reflow Soldering bed of material forms salient point, because the effect of gravity, convex point material can flow to copper metal layer edge (shown in oval among Fig. 5), influence the electrical property of copper metal layer; Same owing to gravity and capillary effect, the salient point that forms through refluxing is generally oval and non-circular, because the integrated level of semiconductor device is more and more higher, spacing between the salient point is more and more littler, therefore, be easy to generate bridge joint between the salient point, cause short circuit between semiconductor device.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of salient point, prevents ubm layer reliability variation, produces bridge joint and copper metal layer electrical property variation between the salient point.
For addressing the above problem, the invention provides a kind of manufacture method of salient point, comprise the following steps: to provide the chip that is formed with solder layer; Chip is placed refluxing unit, and wherein solder layer is positioned at the below of its place chip surface; The Reflow Soldering bed of material forms salient point.
Optionally, the technology of formation solder layer is electroplating technology.
Optionally, the material of described solder layer is tin, leypewter or sn-ag alloy.
Optionally, the thickness of described solder layer is 20 μ m～200 μ m.
Optionally, the temperature of the Reflow Soldering bed of material is 50 ℃～300 ℃.
Optionally, can also comprise a metallic copper post between described solder layer and the chip.The method that forms the metallic copper post is galvanoplastic.
Compared with prior art, the present invention has the following advantages: such scheme contacts the opposite face of chip solder layer place face and is fixing with the reflow ovens hot plate, and chip is positioned at the hot plate below.Because solder layer is inverted, and in reflux course, is subjected to the influence of gravity, solder layer only can be to dirty, and can not penetrate in the ubm layer, and the reliability of ubm layer is guaranteed; Simultaneously, after solder layer was inverted, the salient point that forms that refluxes can not produce the bridge joint phenomenon, has avoided the generation of short circuit; In copper post stud bump making process, the inversion of solder layer makes solder layer when refluxing, and can not flow along the copper metal layer edge, and be attached to the copper metal layer edge, and then the electrical property of copper metal layer is improved.
Description of drawings
Fig. 1 to Fig. 3 is the schematic diagram that existing technology is made salient point;
Fig. 4 is that existing technology is made the design sketch that salient point process bumps lower metal layer produces defective;
Fig. 5 is the design sketch that existing technology is made copper metal layer generation defective in the salient point process;
Fig. 6 is the embodiment flow chart that the present invention makes salient point;
Fig. 7 to Figure 10 is the first embodiment schematic diagram that the present invention makes salient point;
Figure 11 to Figure 14 is the second embodiment schematic diagram that the present invention makes salient point.
Embodiment
Because the size that flip-chip can reduce to encapsulate, so flip chip technology (fct) is more and more paid attention to.And the stud bump making technology is as a key technology in the flip-chip, and its quality that forms quality directly influences the quality of flip-chip.The present invention contacts the opposite face of chip solder layer place face and is fixing with the reflow ovens hot plate, and chip is positioned at the hot plate below.Because solder layer is inverted, and in reflux course, is subjected to the influence of gravity, solder layer only can be to dirty, and can not penetrate in the ubm layer, and the reliability of ubm layer is guaranteed; Simultaneously, after solder layer was inverted, the salient point that forms that refluxes can not produce the bridge joint phenomenon, has avoided the generation of short circuit; In copper post stud bump making process, the inversion of solder layer makes solder layer when refluxing, and can not flow along the copper metal layer edge, and be attached to the copper metal layer edge, and then the electrical property of copper metal layer is improved.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 6 is the embodiment flow chart that the present invention makes salient point.As shown in Figure 6, execution in step S101 provides the chip that is formed with solder layer; Execution in step S102 places refluxing unit with chip, and wherein solder layer is positioned at the below of its place chip surface; Execution in step S103, the Reflow Soldering bed of material forms salient point.
Fig. 7 to Figure 10 is the first embodiment schematic diagram that the present invention makes salient point.As shown in Figure 7; one chip 200 is provided, disposes metal bed course 204 and passivation layer 202 on the described chip 200, wherein in order to protect chip 200 surfaces and metal bed course 204 is exposed; the material of passivation layer 202 can be a silicon nitride etc., and the material of metal bed course 204 is an aluminium etc.
Then, on metal bed course 204 and passivation layer 202, form screen 205, the constituting of a kind of in described screen 205 titaniums, chromium, the tungsten or they, wherein more excellent screen 205 is a titanium; The effect of described screen 205 is to keep good adhesion with metal bed course 204, and effectively stops the phase counterdiffusion of follow-up convex point material with metal bed course 204; It is sputter that the method that forms described screen 205 can adopt the method for existing evaporation or sputter, wherein more excellent method; The thickness of described screen is 500 dusts～3000 dusts.
Form the ubm layer 206 that thickness is 200nm～1500nm with sputtering method or evaporation on screen 205, present embodiment adopts sputtering method.The material of described ubm layer 206 is constituting of a kind of in aluminium, nickel, copper, titanium, the chromium or they.
As shown in Figure 8, on ubm layer 206, form photoresist layer 207 with spin-coating method; Photoresist layer 207 is exposed, behind the developing process, forms opening on photoresist layer 207, and the position of described opening is corresponding with the position of metal bed course 204; Form the solder layer 208 that a layer thickness is 20 μ m～200 μ m with electric plating method in opening, the material of described solder layer 208 is tin, leypewter or sn-ag alloy etc.
Except that present embodiment, before forming solder layer 208, forming thickness with galvanoplastic on can the ubm layer 206 in opening is the inculating crystal layer of 1 μ m～10 μ m, and its material is that Cu, Ni or its constitute.
As shown in Figure 9, remove photoresist layer 207 with the wet etching method; Then, be mask with solder layer 208, with wet etching method etching ubm layer 206 and screen 205 to exposing passivation layer 202; On solder layer 208, be coated with scaling powder; Then, chip 200 is put into reflow ovens, the opposite face of chip 200 solder layers 208 place faces is contacted and fixing with reflow ovens hot plate 230, and make chip 200 be positioned at hot plate 230 belows.
With reference to Figure 10, the solder layer on the chip 200 208 is incubated backflow, form salient point 208a.
In the present embodiment, reflux temperature is 50 ℃～300 ℃.
The opposite face of chip 200 solder layers 208 place faces contacted with reflow ovens hot plate 230 and fixing, and chip 200 is positioned at hot plate 230 belows.Because solder layer 208 is inverted, and in reflux course, is subjected to the influence of gravity, 208 meetings of solder layer are to dirty, and can not penetrate in the ubm layer 206, and the reliability of ubm layer 206 is guaranteed; Simultaneously, after solder layer 208 was inverted, the salient point 208a that forms that refluxes can not produce the bridge joint phenomenon, has avoided the generation of short circuit.
Figure 11 to Figure 14 is the second embodiment schematic diagram that the present invention makes salient point.As shown in figure 11; one chip 300 is provided, disposes metal bed course 304 and passivation layer 302 on the described chip 300, wherein in order to protect chip 300 surfaces and metal bed course 304 is exposed; the material of passivation layer 302 can be a silicon nitride etc., and the material of metal bed course 304 is an aluminium etc.
Then, on metal bed course 304 and passivation layer 302, form screen 305, the constituting of a kind of in described screen 305 titaniums, chromium, the tungsten or they, wherein more excellent screen 305 is a titanium; The effect of described screen 305 is to keep good adhesion with metal bed course 304, and effectively stops the phase counterdiffusion of follow-up convex point material with metal bed course 304; It is sputter that the method that forms described screen 305 can adopt the method for existing evaporation or sputter, wherein more excellent method; The thickness of described screen is 500 dusts～3000 dusts.
Form the ubm layer 306 that thickness is 200nm～1500nm with sputtering method or evaporation on screen 305, present embodiment adopts sputtering method.The material of described ubm layer 306 is constituting of a kind of in aluminium, nickel, copper, titanium, the chromium or they.
As shown in figure 12, on ubm layer 306, form photoresist layer 307 with spin-coating method; Photoresist layer 307 is exposed, behind the developing process, forms opening on photoresist layer 307, and the position of described opening is corresponding with the position of metal bed course 304; In opening, on the ubm layer 306, form metal copper layer 309 with electric plating method, because in the manufacturing process of copper post salient point, the thickness of metal connecting line needs thicker, therefore after forming ubm layer 306, forming a metal copper layer 309 thereon again increases the thickness of the metal connecting line of follow-up formation, to form a bronze medal post; Form the solder layer 308 that a layer thickness is 20 μ m～200 μ m with galvanoplastic on metal copper layer 309, the material of described solder layer 309 is tin, leypewter or sn-ag alloy etc.
As shown in figure 13, remove photoresist layer 307 with the wet etching method; Then, be mask with solder layer 308, with wet etching method etching ubm layer 306 and screen 305 to exposing passivation layer 302; On solder layer 308, be coated with scaling powder; Then, chip 300 is put into reflow ovens, the opposite face of chip 300 solder layers 308 place faces is contacted and fixing with reflow ovens hot plate 330, and make chip 300 be positioned at hot plate 330 belows.
With reference to Figure 14, the solder layer on the chip 300 308 is incubated backflow, form salient point 308a.
In the present embodiment, reflux temperature is 50 ℃～300 ℃.
In the present embodiment, the opposite face of chip 300 solder layers 308 place faces contacts with reflow ovens hot plate 330 and is fixing, and make chip 300 be positioned at hot plate 330 belows, solder layer 308 is inverted, in reflux course, solder layer 308 can not flow along copper metal layer 309 edges, and is attached to copper metal layer 309 edges, and then the electrical property of copper metal layer 309 is improved; In addition, the salient point 308a that forms that refluxes can not produce the bridge joint phenomenon, has avoided the generation of short circuit.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. the manufacture method of a salient point is characterized in that, comprises the following steps:
The chip that is formed with solder layer is provided;
Chip is placed refluxing unit, and wherein solder layer is positioned at the below of its place chip surface;
The Reflow Soldering bed of material forms salient point.
2. according to the manufacture method of the described salient point of claim 1, it is characterized in that the technology that forms solder layer is electroplating technology.
3. convex point production method according to claim 2 is characterized in that, the material of described solder layer is tin, leypewter or sn-ag alloy.
4. convex point production method according to claim 3 is characterized in that, the thickness of described solder layer is 20 μ m～200 μ m.
5. according to each described convex point production method in the claim 1 to 4, it is characterized in that the temperature of the Reflow Soldering bed of material is 50 ℃～300 ℃.
6. convex point production method according to claim 1 is characterized in that, can also comprise a metallic copper post between described solder layer and the chip.
7. convex point production method according to claim 6 is characterized in that, the method that forms the metallic copper post is galvanoplastic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102028398A CN101740422B (en) | 2008-11-17 | 2008-11-17 | Method for fabricating bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102028398A CN101740422B (en) | 2008-11-17 | 2008-11-17 | Method for fabricating bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101740422A true CN101740422A (en) | 2010-06-16 |
| CN101740422B CN101740422B (en) | 2012-08-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008102028398A Expired - Fee Related CN101740422B (en) | 2008-11-17 | 2008-11-17 | Method for fabricating bump |
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| Country | Link |
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| CN (1) | CN101740422B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543898A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Cylindrical bump packaging structure |
| CN103165472A (en) * | 2011-12-15 | 2013-06-19 | 北京大学深圳研究生院 | Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355555A (en) * | 2000-11-28 | 2002-06-26 | 中国科学院微电子中心 | Method for generating convex welding points on semiconductor chip |
| CN100459082C (en) * | 2006-08-10 | 2009-02-04 | 中芯国际集成电路制造(上海)有限公司 | Method for making lead and tin alloy protruding point |
-
2008
- 2008-11-17 CN CN2008102028398A patent/CN101740422B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165472A (en) * | 2011-12-15 | 2013-06-19 | 北京大学深圳研究生院 | Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method |
| CN102543898A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Cylindrical bump packaging structure |
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| Publication number | Publication date |
|---|---|
| CN101740422B (en) | 2012-08-22 |
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Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA Effective date: 20121101 |
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Effective date of registration: 20121101 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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Granted publication date: 20120822 Termination date: 20181117 |