JP2007266427A - Semiconductor light-emitting device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a semiconductor light-emitting element including a current leak point to ensure a certain amount of light emission to suppress a drop in yield. <P>SOLUTION: A chip cut out from a wafer is provided with split electrodes, and a current leak test is conducted at individual electrode. A bump is not formed on an electrode having a current leak point. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device and a manufacturing method thereof. More specifically, in the case of manufacturing a large-area flip-chip type semiconductor light-emitting device from a wafer that essentially includes a leak point with a certain probability, a method for manufacturing a semiconductor light-emitting device for the purpose of improving the yield and its method The present invention relates to a semiconductor light emitting device manufactured by a manufacturing method.

  Since the semiconductor light emitting device can reduce power consumption, it is expected to be put to practical use for illumination. Currently, semiconductor light-emitting devices that are more efficient than incandescent bulbs with a luminous flux per power consumption are in practical use. However, the efficiency is still low compared with fluorescent lamps (see Non-Patent Document 1).

  In order for a semiconductor light emitting device to be put into practical use for illumination, higher output and higher efficiency are required. One method is to increase the light emitting area of one element for high output of the semiconductor light emitting device.

  FIG. 14 shows a general configuration of a semiconductor light emitting device (see Patent Document 1).

A GaN-based n-type semiconductor layer and a p-type semiconductor layer are stacked on a transparent substrate 50 such as sapphire (Al ₂ O ₃ ), SiC, or GaN. An active layer mainly composed of GaInN is provided between the n-type semiconductor layer and the p-type semiconductor layer in a sandwich shape. Part of the substrate is removed by etching the p-type semiconductor layer and the active layer, and the n-type semiconductor layer is exposed.

  An n-side electrode 52 and a p-side electrode 53 are provided on the exposed n-type semiconductor layer and p-type semiconductor layer, respectively. Each electrode is provided with a current path called a bump 54 using mainly gold. The bumps 54 are joined to Ti / Ni / Au electrodes 66 provided on the submount 120. A through hole 70 is formed in the submount 120, and the inside is filled with a conductor. A connection electrode 65 connected to a current terminal from the power source is provided under the submount 120 and is electrically connected to the Ti / Ni / Au electrode 66 through a through hole of the submount 120.

  The light emission of the semiconductor light emitting element occurs in the active layer when current flows along the route from the p-type semiconductor layer to the active layer and the n-type semiconductor layer. A p-n junction is required between the p-type semiconductor layer and the active layer and the n-type semiconductor layer. If the pn junction is destroyed and the current is in a conducting state (hereinafter referred to as “current leakage state”, the point in which the conduction state is established is referred to as “current leakage point”), not only light emission, Damage occurs to the current drive circuit.

Therefore, it is inspected in advance whether or not current leakage has occurred (see Patent Document 2). Note that the current leakage state means that the resistance value is significantly reduced not only from the p-type semiconductor layer to the n-type semiconductor layer but also in the reverse direction.
JP-A-2005-79551 Japanese Patent Laid-Open No. 11-121567 “High-power white LED light source for lighting” Matsushita Electric Works Technical Report (Vol.53 No.1, February 2005) Sugimoto Katsu et al.

  The semiconductor light emitting device shown in FIG. 14 can be obtained by manufacturing and cutting a large number of devices on a large substrate called a wafer using a technique such as photolithography. This wafer is a single crystal material made from a raw material purified to a very high purity, but there are slight crystal defects.

  This crystal defect is inherited by the p-type semiconductor layer, the active layer, and the n-type semiconductor layer that are generated by stacking on this wafer, and does not become a normal pn junction but becomes a conduction point. This is a current leak point of the semiconductor light emitting device.

  FIG. 15 illustrates that a current leak point 90 exists on the wafer. FIG. 15A shows a case where a chip with a small area is cut out, and FIG. 15B shows a case where a chip with a large area is cut out. In (a) and (b) of FIG. 15, each lattice represents the size of the cutout.

  For example, in FIG. 15A, a total of 342 chips of 19 vertical divisions and 18 horizontal divisions can be cut out. If there are five current leak points 90 on this wafer, the ratio of chips with current leak points 90 is about 5/342.

  On the other hand, if nine chips having a large area are cut out from the wafer as shown in FIG. 15B, in the case shown in the figure, the four chips include the current leakage points 90, and the ratio thereof is 4/9. The current leak point 90 is a defective product because a problem such as a decrease in light emission intensity or no light emission and damage to the drive circuit occurs.

  That is, as the chip area of the semiconductor light emitting element increases, the ratio of elements including a current leak point increases. This leads to a decrease in yield.

  This ratio cannot be reduced unless the percentage of crystal defects in the raw material wafer is reduced. Therefore, when all the semiconductor light emitting elements including the current leak point are discarded as defective products, the yield of the semiconductor light emitting element is significantly reduced as the chip area cut out from the wafer is increased.

  The present invention has been conceived to cope with such problems, and it is an object of the present invention to suppress a decrease in yield while securing a constant light emission amount even in a semiconductor light emitting device including a current leak point. .

  In the present invention, a current leak test is performed for each electrode manufactured on a semiconductor light emitting device cut out from a wafer, and bumps are not placed on the electrodes where current leak points exist, or bumps are made nonconductive. By doing so, even a semiconductor light emitting element having a current leak point can emit light at a portion not including the current leak point.

  In the present invention, by providing a plurality of electrodes on a large-area semiconductor light emitting device, the electrode area including the current leakage point and becoming conductive is limited, and the portion is not used. Even a chip including it can emit light. Therefore, even if a chip that becomes a semiconductor light emitting element with a large area is cut out from a wafer that includes lattice defects that cause current leak points at a certain rate, a reduction in yield can be suppressed.

(Embodiment 1)
Next, an embodiment of the present invention will be described. As the wafer, a GaN substrate 100 having a diameter of 2 inches is used. The thickness is 350 μm. An 800 μm square semiconductor light emitting device is formed on the wafer. Before the semiconductor light emitting element is divided into individual chips, the wafer is polished from the back side of the substrate as necessary to reduce the thickness to 100 μm to 300 μm.

  FIG. 1 shows a configuration of a semiconductor light emitting device using a semiconductor light emitting element cut out from a wafer. In the semiconductor light emitting device, a GaN n-type semiconductor layer 101, an InGaN active layer 102, and a GaN p-type semiconductor layer 103 are stacked in this order on a GaN substrate 100.

  Then, the p-type semiconductor layer 103 and part of the active layer 102 are etched to expose the n-type semiconductor layer 101. An n-side electrode 104 was formed on the exposed surface of the n-type semiconductor layer 101. A p-side electrode 105 is formed on the surface of the p-type semiconductor layer 103. As is apparent from the figure, this semiconductor light emitting device is a single-sided electrode type.

  In addition, as a structure of blue LED, it is not limited to the example given here. For example, as an alternative to the GaN substrate 100, a SiC substrate or an insulating sapphire substrate may be used. Further, for example, as the n-type semiconductor layer 101 or the p-type semiconductor layer 103, AlGaN or InGaN may be used, or a buffer layer made of GaN or InGaN between the n-type semiconductor layer 101 and the GaN substrate 100. It is also possible to use. For example, the active layer 102 may have a multilayer structure (quantum well structure) in which InGaN and GaN are alternately stacked.

  Bumps 106 are joined to the p-side electrode 105 and the n-side electrode 104 of the semiconductor light emitting device, and further joined to the p-side wire bond lead electrode 107 and the n-side wire bond lead electrode 108, respectively. The p-side wire bond lead electrode 107 and the n-side wire bond lead electrode 108 are electrodes provided to supply current to the p-side electrode 105 and the n-side electrode 104. These extraction electrodes are provided on the submount 120. The semiconductor light emitting device is configured as described above.

  Note that a semiconductor light-emitting device is obtained if at least a bump is bonded to a semiconductor light-emitting element having electrodes formed throughout this specification.

  Further, throughout the present specification, the direction in which the p-type semiconductors are stacked is referred to as the “p direction” and the substrate side is referred to as the “s direction”. A state in which up to a p-type semiconductor is stacked on a substrate and cut out from the wafer is called a chip. Further, the above-mentioned “direction” is also applied to the semiconductor light emitting device.

  FIG. 2 shows the state of the electrodes formed on the semiconductor light emitting device. FIG. 2A is a side view of a chip on which electrodes are formed. The pn junction 110 is a description of the n-type semiconductor layer 101, the InGaN active layer 102, and the GaN p-type semiconductor layer 103 in FIG. FIG.2 (b) is the figure seen from the p direction.

  Sixteen electrodes are provided, one is an n-side electrode 104 and the other is a p-side electrode 105. The size of the electrode is 150 μm square. The minimum area of the electrode provided on one element is limited by the size of the bump, and the lower limit is about 100 μm square.

  Therefore, the electrode can be installed if it is larger than the cross-sectional area of the bump. However, if the electrode is large, the area of the electrode that cannot be used increases when there is a current leak point under the electrode. When the electrode area that cannot be used is increased, the light emitting area is decreased, so that the performance as a light emitting element is lowered.

  The area of the electrode is determined in consideration of the final target yield based on the density of crystal defects present on the wafer and the accuracy limit during manufacturing. In the present embodiment, the cut-out chip is divided into 16 sections, and the n-side electrode 104 is provided at one place and the p-type electrode is provided at 15 places.

  FIG. 3 shows a state of current leak inspection. The n-side electrode probe needle 210 is an inspection terminal in contact with the n-side electrode 104, and the other p-side electrode probe needles 212 are inspection terminals in contact with the p-side electrode 105. A necessary number of these terminals are fixedly arranged in advance on a card-like substrate, and the semiconductor light emitting element can be moved so that predetermined electrodes of the semiconductor light emitting element are in contact with each other. Of course, the inspection terminal may move, but the inspection object should move. This is because moving the inspection terminal is mechanically complicated. Here, the inspection target is a chip, but it may be a wafer.

  The probe switch 206 has an n-side switch terminal 232 to which the n-side electrode probe needle 210 is connected and a p-side switch terminal 234 to which the p-side electrode probe needle 212 is connected. The probe switch 206 includes a changeover switch that connects one of the n-side switch terminals 232 to one electrode of the current source 208 and a switch that switches one of the p-side switch terminals 234 to the other electrode of the current source 208. Have. That is, the probe switch 206 can connect one of the connected p-side electrode probe needles 212 and one of the n-side electrode probe needles 210 to the electrode of the current source 208. These instructions are based on instructions from the control device 202.

  Each electrode probe needle is assigned a number, and to which electrode probe needle the current is applied is managed by this number.

  A current source 208 is coupled to the electrode of the probe switch 206 and generates a forward current of a predetermined current for inspection according to an instruction from the control device 202.

  The voltage measuring device 204 is disposed between the current source 208 and the probe switch 206 and measures a forward voltage generated between the n-side electrode probe needle 210 and the p-side electrode probe needle 212. The timing of measurement is in accordance with an instruction from the control device 202.

  The control device 202 controls the entire inspection device, sequentially moves the tip provided with the electrode to be inspected under the probe, and brings the probe needle into contact with the electrode on the tip. Thereafter, a predetermined current is applied in the forward direction of the pn junction to sequentially inspect the forward voltage generated between the n-side electrode 104 and the p-side electrode 105.

  FIG. 4 shows an operation flow of current leak inspection performed by the control device 202.

  This flow starts after it is confirmed that the tip to be inspected is arranged at a predetermined position and the probe needle is in contact with the electrode on the tip (Step 1000).

  First, the probe switch 206 selects the n-side electrode probe needle 210 and the p-side electrode probe needle 212 one by one. In the present embodiment, since there is one n-side electrode 104, the selected n-side electrode probe needle 210 is fixed, and one of the p-side electrode probe needles 212 is selected (Step 1010).

  Next, the control device 202 instructs the current source 208 to generate a forward current for inspection (Step 1020). Thereafter, the voltage measuring device 204 is caused to measure the forward voltage (Step 1030). Although omitted in the flow, it is better to stop the generation of current after measurement. This is to reduce the burden on the power supply when moving to the next measurement. The number of the applied p-side electrode probe needle 212 and the current value and voltage value at that time are managed as one set of measurement values.

  When the resistance measurement between one p-side electrode probe needle 212 and the n-side electrode probe needle 210 is finished, it is confirmed whether there is a combination of the untested p-side electrode probe needle 212 and the n-side electrode probe needle 210 (Step 1040). ) If there is, select the probe needle. When all the inspections are completed, the inspection for the inspection target chip ends.

  The current leak point is determined when the forward voltage value is lower than a predetermined value in the obtained set of measured values. The position of the p-side electrode 105 determined to have a current leak point is recorded, and is referred to when a bump is formed later. The measurement routine shown here is an example, and the present invention is not limited to this. For example, instead of inspecting the p-side electrodes 105 one by one, the forward voltage values are collectively measured, and the individual p-side electrodes 105 are inspected for the first time if the forward voltage value is smaller than a predetermined value. Good.

  For example, in the case of a semiconductor light emitting device made of a GaN-based material, the presence or absence of a current leak point can be determined by whether the forward voltage when a forward current of about 10 microamperes is applied is higher or lower than about 2 volts. If it is lower than about volt, it can be determined that there is a current leak point.

  As described above, the method for determining the current leakage by applying the forward current and measuring the forward voltage generated at that time has been described. However, in addition to this, the reverse voltage is applied to the pn junction. There are a method of measuring and judging the flowing reverse current, and a method of measuring and judging the forward current flowing at that time by applying a forward voltage to the pn junction.

FIG. 5A shows a state in which the n-side electrode 104 and the p-side electrode 105 are applied to the chip and mounted on the submount 120 via the bumps 106. The submount 120 is mainly made of a Si Zener diode or a ceramic such as AlN (aluminum nitride) or Al ₂ O ₃ (alumina). The purpose is mainly to extract terminals from the n-side electrode 104 and the p-side electrode 105 to the power source. Accordingly, the submount 120 includes a p-side wire bond lead electrode 304 that takes out the p-side electrode 105 together and an n-side wire bond lead electrode 302 that takes out the n-side electrode 104. These extraction electrodes are produced by depositing a thin film of Al or the like on the submount 120.

  FIG. 5B shows a state in which the submount 120, the n-side wire bond lead electrode 302, the p-side wire bond lead electrode 304, and the bump 106 are viewed from the chip side. The alternate long and short dash line indicates the position where the chip is mounted. The positions where the bumps 106 are provided are indicated by dotted lines.

  As shown in FIG. 5B, the n-side wire bond lead electrode 302 and the p-side wire bond lead electrode 304 are regions where the bumps 106 are formed (one-dot chain line portion) and a power source (other than the one-dot chain line). ).

  The bumps 106 for connection to the n-side wire bond lead electrode 302 and the p-side wire bond lead electrode 304 are provided as follows. First, a base is provided on the n-side wire bond lead electrode 302 and the p-side wire bond lead electrode 304, and the bumps 106 are formed thereon.

  As a method for forming the bump 106, a plating method, a vacuum deposition method, a screen printing method, a droplet ejection method, a wire bump method, or the like can be used. As the bump material, Au, Au—Sn, solder, In alloy, polymer, or the like can be used.

  In the present embodiment, one end of the Au wire is bonded to the bump forming region on the submount with a bonder, and then the Au bump is formed by cutting the wire. The droplet injection method is a method in which fine nanoparticles such as gold are dispersed in a volatile solvent, printed using a method similar to inkjet printing, and the solvent is removed by volatilization to form bumps as an aggregate of nanoparticles. How to do.

  At this time, the bump 106 corresponding to the p-side wire bond lead electrode 304 that is determined to have a current leak point with reference to the result of the current leak test is not provided on the submount 120. Then, a chip on which the p-side electrode 105 is formed is mounted and bonded to the submount 120 on which the bumps 106 are formed. By doing so, only the p-side electrode 105 capable of making a pn junction without a current leak point is bonded to the bump 106, and light emission is possible as a semiconductor light emitting device.

  FIG. 6 shows the submount 120, the bump 106, and the chip when it is determined that one part of the p-side electrode 105 has a current leak point. A location indicated by 320 is the p-side electrode 105 without the bump 106. This portion is a portion in which bumps are not formed on the submount on which this chip is mounted, as determined by the current leak inspection described above that there is a current leak point.

  FIG. 7 is a cross-sectional view of the portion indicated by the one-dot chain line in FIG. 320 does not have a bump 106, so no current is applied from the corresponding p-side electrode 105.

  In the semiconductor light emitting device, a current flows from the p-type semiconductor layer to the n-type semiconductor layer, and light emission occurs in an active layer therebetween. In particular, in a semiconductor light emitting device made of a GaN-based material, since the resistivity of the p-type semiconductor layer is generally high, the current hardly spreads in the lateral direction in the plane of the p-type semiconductor layer, and the activity just below the p-side electrode 105 is obtained. Luminescence occurs only in the layer. Therefore, no light emission occurs in a portion where no current is supplied from the bump 106. In the case of the chip in FIG. 6, light emission occurs only at 14 of the 15 p-side electrodes 105.

However, when a current is supplied to an electrode having a current leak point via a bump, the resistance of the electrode is remarkably low, so that most of the current supplied to the p-side wire bond lead electrode flows to the electrode. Since the pn junction is broken at the current leak point, no light is emitted. As a result, the light emission of the semiconductor light emitting element itself becomes extremely weak or no light is emitted.
Therefore, as in this embodiment, after inspecting the current leak point, it is possible to avoid the case where no light is emitted or the light emission becomes extremely weak unless a bump corresponding to the p-side electrode is formed. .

(Embodiment 2)
In the present embodiment, a method for inspecting a current leak point different from that in the first embodiment will be described. FIG. 8 shows the state of the n-side electrode probe needle 210 and the p-side electrode probe needle 212 of the n-side electrode 104 and the p-side electrode 105, respectively. Although the n-side electrode probe needle 210 remains in contact with the n-side electrode 104, the p-side electrode probe needle 212 performs an inspection while sequentially scanning the p-side electrode 105. In the scan, the p-side electrode probe needle 212 is brought into contact with one p-side electrode 105, a current leak test is performed, and then the p-side electrode probe needle 212 is lifted and moved to the next electrode to be inspected. The act of lowering the probe needle 212 and bringing it into contact with the electrode is continued one after another.

  This inspection method eliminates the need for a probe switch and simplifies the inspection apparatus accordingly. However, a mechanism for scanning the probe needle along the electrode is required. Information obtained as a result of the inspection is the same as that in the first embodiment, and is referred to in a later process.

(Embodiment 3)
In the present embodiment, the formation of the n-type semiconductor layer 101 and the p-type semiconductor layer 103 on the substrate and the current leakage inspection are the same as those in the first embodiment.

  A feature of this embodiment is that all the bumps 106 are formed on the submount 120, and the bump 106 corresponding to the electrode having the current leak point is crushed, thereby preventing current from flowing into the current leak point.

  FIG. 9 shows the destruction device and operation of the bump 106. The submount (not shown in the figure) on which the bumps 106 are formed is arranged at a predetermined position below the hammer 380 by moving means (not shown). The hammer 380 has a cross-sectional area larger than that of the bump 106 and is not so large as to crush the adjacent bump 106. The hammer 380 can be moved to a position corresponding to the place where the bump 106 exists. Therefore, it can come on any bump 106 formed on the submount 120.

  When the submount 120 is disposed under the hammer 380, the hammer 380 moves above the bump 106 corresponding to the electrode including the current leak point with reference to the result of the current leak inspection described above (FIG. 9A )), And the bump 106 is crushed (FIGS. 9B to 9C).

  FIG. 10 is a cross-sectional view when a chip is bonded to the submount 120 having the bumps 322 crushed as described above. Since the bump 322 corresponding to the electrode having the current leakage point is crushed by the hammer 380, the bump 322 does not come into contact with the p-side electrode 105, and current inflow to this electrode is avoided.

  According to the present embodiment, bump formation can be performed at once, and the efficiency at the time of bump formation can be increased.

(Embodiment 4)
FIG. 11A shows the semiconductor light emitting device of this embodiment viewed from the side, and FIG. 11B shows the semiconductor light emitting device viewed from the p direction. In this embodiment, the case where the substrate itself is an n-type semiconductor is shown. That is, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are formed on an n-type semiconductor substrate to produce a semiconductor light emitting device. The n-type semiconductor substrate 99 is made of n-type by adding a donor to GaN. Of course, it is not limited to this. The pn junction layer 111 is formed by stacking an n-type semiconductor layer 101, an active layer 102, and a p-type semiconductor layer 103 on an n-type semiconductor substrate 99.

  The n-type semiconductor layer 101, the active layer 102, and the p-type semiconductor layer 103 are the same as those in the first embodiment. Since the substrate of this semiconductor light emitting device is an n-type semiconductor, the n-side electrode 104 is formed on the surface opposite to the surface on which the p-type semiconductor layer 103 is formed. Then, only the p-side electrode 105 is formed on the p-type semiconductor layer 103. By doing in this way, a light emission area can be enlarged.

  FIG. 12A shows a state where this chip is mounted on the submount 120 through the bump 106. Although the light emitting area can be increased, the n-side electrode 104 must be provided in the s direction, which is the light emitting direction of the semiconductor light emitting element. A wiring 390 for energization is connected to the n-side electrode 104.

  FIG. 12B shows a state viewed from the s direction. Since the submount 120 only needs to perform extraction from the p-side electrode 105, only the p-side wire bonding extraction electrode 304 is provided. A portion indicated by 320 shows a portion where there is a current leak point by the current leak test and the bump 106 is not provided.

  FIG. 13 shows a chip inspection apparatus used in this embodiment. Since the n-side electrode 104 is formed on the opposite surface of the p-side electrode 105 in the tip of this embodiment, the stage 222 when the tip is placed can also be used as an n-side electrode probe needle. Therefore, since the p-side electrode probe needles 212 can be freely arranged, a plurality of p-side electrode probe needles 212 are prepared and scanned while inspecting each column or row of the p-side electrode 105 on the chip. You can also

  As the inspection procedure in this case, a procedure for inspecting each electrode while sequentially switching the p-side electrode probe needles 212, energizing all the prepared p-side electrode probe needles 212, and if there is a current leak point, Either of the inspection methods for each electrode can be used. Needless to say, the method shown in Embodiment Mode 1 or 2 can be used by being appropriately changed, and the inspection procedure is not limited.

  Although the bump 106 is formed on the submount 120 here, the bump 106 may be formed directly on the mounting surface of the package on which the semiconductor light emitting element is mounted without using the submount 120.

  Since the electrodes formed on the chip cut out from the wafer are divided electrodes, and bumps are not bonded to the electrodes including current leak points existing on the wafer, the yield of semiconductor light emitting devices using semiconductor light emitting elements having a relatively large area It is effective for improvement. Therefore, there is industrial applicability as a suitable method for manufacturing a semiconductor light emitting device.

The figure which shows the structure of a semiconductor light-emitting device It is a figure which shows the mode of the electrode formed in the semiconductor light-emitting element, (a) is the figure which looked at the chip | tip which formed the electrode from the side, (b) is the figure seen from the p direction. The figure which shows the outline of the test | inspection apparatus which performs the resistance value test | inspection of the chip | tip which attached the electrode. The figure which shows the operation | movement flow of the current leak test | inspection which a control apparatus performs The figure which shows the state which mounted the chip | tip on the submount, (a) is a figure which shows the state which gave the electrode to the chip | tip and mounted in the submount, (b) looked at the submount, the extraction electrode, and the bump from the chip | tip side. Diagram showing the state The figure which shows the semiconductor light-emitting device which has the part which did not form bump The figure which shows the cross section of the semiconductor light-emitting device which has the part which did not form bump The figure which shows resistance value inspection by other methods It is a figure which shows operation | movement of the apparatus which crushes a bump with a current leak point, (a) is a figure before crushing a bump, (b) is a figure which crushes a bump, (c) is a figure after crushing a bump The figure which shows the semiconductor light-emitting device which has crushed bump The figure which shows the chip | tip from which the position of an n side electrode differs, (a) is the figure seen from the side, (b) is the figure seen from the p direction 11A and 11B are diagrams in which the chip of FIG. 11 is a semiconductor light emitting device, in which FIG. 11A is a diagram illustrating a state where the chip is mounted on a submount, and FIG. 11B is a diagram illustrating a state viewed from the p direction. The figure which shows the measurement outline | summary in the case of performing resistance value test | inspection of the chip | tip of FIG. The figure which shows the general structure of a semiconductor light-emitting device 2A and 2B are diagrams illustrating the presence of a current leakage point on a wafer, where FIG. 1A is a diagram in the case of cutting out a chip with a small area, and FIG. 2B is a diagram in the case of cutting out a chip with a large area.

Explanation of symbols

100 GaN substrate 101 n-type semiconductor layer 102 active layer 103 p-type semiconductor layer 104 n-side electrode 105 p-side electrode 106 bump 107 p-side wire bond lead electrode 108 n-side wire bond lead electrode 110 pn junction 120 sub Mount 202 Controller 204 Voltage measuring device 206 Probe switch 208 Current source 210 Probe needle for n-side electrode 212 Probe needle for p-side electrode 302 Extraction electrode for n-side wire bond 304 Extraction electrode for p-side wire bond 320 No bump is formed Electrode 322 Bumped electrode 380 Hammer

Claims (3)

P-type and n-type semiconductors stacked on a substrate;
A plurality of p-side electrodes provided on the p-type semiconductor;
A semiconductor light-emitting device having at least one n-side electrode provided on the n-type semiconductor, the p-side electrode, and a bump bonded to the n-side electrode,
A semiconductor light-emitting device in which the bump is not bonded to the p-side electrode in a current leak state with the n-side electrode. Stacking an n-type semiconductor and a p-type semiconductor on a substrate;
Providing an n-side electrode on the n-type semiconductor and a p-side electrode on the p-type semiconductor;
Checking current leakage between the n-side electrode and the p-side electrode;
Bumps are not provided on the submount corresponding to the p-side electrode that is in a current leak state with the n-side electrode, and on the submount and the n-side electrode corresponding to the p-side electrode that is not in a current leak state. Providing a bump;
A method of manufacturing a semiconductor light emitting device, comprising: joining a submount provided with the bump and a substrate provided with the n-side and p-side electrodes. Stacking an n-type semiconductor and a p-type semiconductor on a substrate, providing an n-side electrode on the n-type semiconductor, and providing a p-side electrode on the p-type semiconductor;
Checking current leakage between the n-side electrode and the p-side electrode;
Forming bumps on the submount; and
Crushing bumps on the submount corresponding to the p-side electrode in a current leak state with the n-side electrode;
A method of manufacturing a semiconductor light emitting device, comprising: joining a submount provided with the bump and a substrate provided with the n-side and p-side electrodes.

Images