201120460 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種訊號測試系統及方法，尤其關於一種低 壓差分訊號時序測試系統及方法。 【先前技術】 [0002] 低壓差分訊號（Low Voltage Di f ferential Signal ，LVDS)是一種低擺幅的訊號傳輸技術，LDVS具有高速 度、低功耗、低雜訊、低成本等優點，在高速資料傳輸 A 上得到了廣泛的應用。 ❹ [0003] 低壓差分訊號時序關係的正確性是資料可靠傳輸的重要 保證。目前，低壓差分訊號時序測試需要依靠作業員的 . +.. .. .... . 手工操作。手工操作的測試_方法木僅金_率:儒而且容易 出錯，已不能滿足快速高品質生產的競爭需求。 【發明内容】 [0004] 鑒於以上内容，有必要提供一種低壓差分訊號時序測試 系統及方法’能夠快速準碟地測試低壓差分訊號的時序 〇 關係。 [0005] —種低壓差分訊號時序測試系統’所述低壓差分訊號包 括資料訊號及時脈訊號，該系統包括：波形獲取模組， 用於獲取所述資料訊號及時脈訊號的波形；波形識別模 組，用於從時脈訊號的波形中選擇時脈週期，從資料訊 號的波形中識別該選擇的時脈週期内傳送的各個位元的 起始時間，時序分析模組，用於計算各個位元的起始時 間與選擇的時脈週期起點的時間差；統計模組，用於根 據多次計异得到的各個位元的起始時間與選擇的時腺週 098141266 表單編號 A0101 第 3 頁/共 21 頁 0982070775-0 201120460 期起點的時間差，計算各個位元的起始時間與選擇的時 脈週期起點的時間差的最小值及最大值；及輸出模組，’ 用於輪出各個位元的起始時間與選擇的時脈週期起點的 時間差的最小值及最大值。 [0006] [0007] [0008] 098141266 一種低壓差分訊號時序測試方法，所述低壓差分訊號包 括資料訊號及時脈訊號，該方法包括步驟：獲取所述資 料訊號及時脈訊號的波形；從時脈訊號的波形中選擇時 脈週期；從資料訊號的波形中識別該選擇的時脈週期内 傳送的各個位元的起始時間；計算各個位元的起始時間 《 與選擇的時脈週期起點的時間差；根據多次計算得到的 各個位元的起始時間與選擇的時脈週期起點的時間差， 計算各個位元的起始時間與選择的時脈週期起點的時間 差的最小值及最大值；及輸出各個位元的起始時間與選 擇的時脈週期起點的時間差的最小值及最大值。 本發明低壓差分訊號時序測試系統及方法，可以快速準 確地對低壓差分訊號的時序關係實施測試。 【實施方式】 參閱圖1所示’係本發明低壓差分訊號時序測試系統較佳 實施例的應用環境示意圖。低壓差分訊號〗3包括資料訊 號14及時脈訊號15，低壓差分訊號13的時序關係即資料 訊號14相對於時脈訊號15的時間關係。所述低壓差分訊 號時序測試系統1 〇運行於電腦Π中。該電腦丨丨與示波器 12及顯示設備16通訊連接。示波器12透過測試探頭探測 低壓差分訊號13的資料訊號14與時脈訊號15。 參閱圖2所示，係圖1中低壓差分訊號時序測試系統1 〇的 表單編號A0101 第4頁/共21頁 0982070775-0 [0009] 201120460 功能模組圖。所述低壓差分訊號時序測試系統10包括波 形獲取模組200、波形識別模組210、時序分析模組220 、判斷模組230、統計模組240及輸出模組250。 [0010] 所述波形獲取模組200用於獲取資料訊號14以及時脈訊號 15的波形。在本實施例中，波形獲取模組2〇〇發送波形捕 獲命令給示波器12。根據該波形捕獲命令，示波器12捕 獲資料訊號14以及時脈訊號15的波形，並將捕獲的資料 訊號14以及時脈訊號丨5的波形返回電腦丨丨。如圖4所示， 〇 曲線41為資料訊號14的波形，曲線40為時脈訊號15的波 形。 [0011] 所述波形識別模組210用於從獲取的時脈訊號丨5的波形中 選擇時脈，針對每—選獅雜咖，&資料訊號 14的波形中識別該時脈週期内傳送的各個位元的起始時 間。在本實施例中，波形識別模組210透過識別數值發生 轉變的位元來確定各個位元的起始時間。一般來說，資 肖訊號14的各個位元根據其電壓值的高低取值為1或者〇 ，通常尚電壓取值為1，低電壓取值為0。若某一位元的 數值與前-位it的數值不同，則該位元的數值發生轉變 。例如’若第一位元傳送0，第二位元傳送卜則第二位 元的數值發生轉變。或者，若第-位元傳送1，第二位元 傳送0 ’則第一位疋的數值發生轉變。此時，數值發生轉 變的時間點就是第二位元的起始時間。在本實施例中， 每—時脈週期傳送7位元（blt〇_bit6)。如圖4所示， 波形識別模組210選擇時脈週期42，時脈週期42的起點是 τ〇終點疋η ’波形識別模組21〇識別該時脈週期“内 098141266 表單編號Α0101 0982070775-0 第5頁/共21頁 201120460 傳送的 7 位元為 1100101 ’ 即 bit0 = l，bitl = l , bit2 = C ，bit3 = 〇，bit4 = l，bit5 = 0，bit6 = l。由於上一時脈 週期傳送的最後一個位元是〇，因此，數值發生轉變的位 元是bitO、bit2、bit4、bit5與bit6，其相對應的起 始時間分別是10、12、14、15與16。 [0012] 所述時序分析模組220用於計算識別的各個位元的起始時 間與選擇的時脈週期起點的時間差。在本實施例中參 閱圖5所示，每一時脈週期傳送7位元（bit〇_bit6)， 第一位元的起始時間與時脈週期起點的時間差記為Tp_ P〇s0，第二位元的起始時間與時脈週期起點的時間差記 為Tpp〇sl.......，第七位元的起始時間與時脈週期起點 的時間差記為Tpp0S6。Tpp0S〇-TpD〇S6代表了低壓差分 訊號13的時序關係。根據識別的各個位元的起始時間， 可以計算識別的各個位元與選擇的時脈週期起點的時間 差。舉例來說，如圖4所示，數值發生轉變的位元是bu〇 bit2 bit4、bit5與bit6，其相對應的起始時間分 另J疋t0 U、t4、t5與t6 ’該時脈週期42的起始時間是 T0 ，則Tpp〇s0=t0-T0 ， Tpp〇s2=t2-T0 ， Tp-P〇s4 = t4-T0，TPP〇S5 = t5-TO，TppOS6 = t6-T0。又如 ，若數值發生轉變的位元是bit〇、bitl、…“與^” ，其相對應的起始時間分別是切' tl、。與“，則Tp — P〇s0=t0-T0 > Tpp〇sl=tl-T0 - Tpp〇s3=t3-T0 > Tp-pos5=t5-TO 〇 所述判斷模組230用於判斷是否已獲得指定數量的各個位 凡的起始時間與選擇的時脈週期起點的時間差。在本實 098141266 表單編號Α0ΗΠ 第6頁/共21頁 0982070775-0 [0013] 201120460 施例中，對於每一位元（例如：bit〇_bit6)，需要至 少1 0個該位元的起始時間與選擇的時脈週期起點的時間 差，判斷模組230判斷計算得到的每—位元的起始時間與 選擇的時脈週期起點的時間差是否均已達到1〇個。 [0014] 所述統计模組240用於什算各個位元的起始時間與選擇的 時脈週期起點的時間差的最小值及最大值。例如，對於 低壓差分讯號13，§十鼻得到1 〇個Tpp0si，分別是1 〇. 55 、10. 64、10. 58、10. 73、10. 65、ι〇· 52、1〇 65、 Ο 10· 75、10. 87、10. 73，單位納秒（ns)，則統計模組 240算得Tpposl的最小值是1〇. 52ns，最大值是1〇. 87ns 。在本實施例中，統計模組240還用於分析計算得到的各 個位元的起始時間與選擇的時脈週期起點的時間差的最 小值及最大值疋否捋合技術規範。圖6給出了低壓差分訊 號時序關係的技術規範。根據該技術規範，第一位元脈 衝位置的最小值是（T/7-0.2)ns，最大值是 (T/7 + 0. 2)ns ’其中T表示時脈週期。例如，若T = 75ns ... ：. . ’則技術規範中的最小值是1〇.. 514ns，最大值是 W· 914ns。因此’若統計模組240計算得到某個時脈週 期為75ns的低壓差分訊號13的Tpposl的最小值是1〇. 52 ’表大值是10.87，則計算得到的Tpposl符合技術規範 [0015] 所述輪出模組250用於輸出各個位元的起始時間與選擇的 時脈週期起點的時間差的最小值及最大值。在本實施例 中’輪出模組250將各個位元的起始時間與選擇的時脈週 '月起點的時間差的最小值及最大值顯示在與電腦11相連 098141266 表單編號A0101 第7頁/共21頁 0982070775-0 201120460 的顯示設備1 6上。此外，所述輸出模組2 5 0還輸出各個位 元的起始時間與選擇的時脈週期起點的時間差的最小值 及最大值符合技術規範的情況。 [0016] 參閱圖3所示，是本發明低壓差分訊號時序測試方法較佳 實施例的流程圖。 [0017] 步驟S301，波形獲取模組200獲取低壓差分訊號13的資 料訊號14及時脈訊號15的波形。在本實施例中，波形獲 取模組200發送波形捕獲命令給示波器12。根據該波形捕 獲命令，示波器12捕獲資料訊號14以及時脈訊號15的波 形，並將捕獲的資料訊號14以及時脈訊號15的波形返回 電腦11。如圖4所示，曲線41為資料訊號14的波形，曲線 40為時脈訊號15的波形。 [0018] 步驟S302，波形識別模組210從獲取的時脈訊號15的波 形中選擇一個時脈週期，並且從資料訊號14的波形中識 別該時脈週期内傳送的各個位元的起始時間。在本實施 例中，波形識別模組210透過識別數值發生轉變的位元來 確定各個位元的起始時間。一般來說，資料訊號14的各 個位元根據電壓值的高低取值為1或者0，通常高電壓取 值為1，低電壓取值為0。若某一位元的數值與前一位元 的數值相異，則該位元的數值發生轉變。例如，若第一 位元傳送0，第二位元傳送1，則第二位元的數值發生轉 變。或者，若第一位元傳送1，第二位元傳送0，則第二 位元的數值發生轉變。此時，數值發生轉變的時間點就 是第二位元的起始時間。在本實施例中，每一時脈週期 傳送7位元（b i 10 - b i 16 )。如圖4所示，波形識別模組 098141266 表單編號A0101 第8頁/共21頁 0982070775-0 201120460 210選擇時脈週期42，時脈週期42的起點是TO，終點是 丁1，波形識別模組21〇識別該時脈週期42内傳送的7位元 為 1100101，即bitO = l，bitK，bit2 = 0，bit3 = 0， bit4 = l，bit5 = 0，bit6 = l。由於上一時脈週期傳送的 最後一個位元是〇，因此，數值發生轉變的位元是、 bit2、bit4、bit5與bit6，其相對應的起始時間分別 是t0、t2、t4、t5與t6。 [0019]步驟S303，時序分析模組220計算識別的各個位元的起始 0 時間與選擇的時脈週期起點的時間差。在本實施例中， 參閱圖5所示’每一時脈週期傳送7位元（bit〇_bit6) ，第一位元的起始時間與時脈週期起點的時間差記為Tp_ posO，第二位元的起始時間與時脈週斯起點的時間差記 為Tpposl.......，第七位元的起始時間與時脈週期起點 的時間差記為Tppos6。Tppos〇-Tppos6代表了低壓差分 訊被13的序關係。根據識別的各個位元的起始時間， 可以计鼻識別的各個位元為選擇的時脈週期起點的時間 〇 差。舉例來說’如圖4所示，數值發生轉變的位元是bit〇 .、bit2、bit4、bit5與bit6，其相對應的起始時間分 別是t0、t2、t4、t5與t6，該時脈週期42的起始時間是 TO，則丁卩卩〇3〇 = 1;0-1'0，丁？？〇52 = 12-1'0，丁卩- P〇s4 = t4-T0，Tppos5 = t5-T0，Tppos6 = t6-T0。又如 ，若數值發生轉變的位元是bitO、bitl、bit3與bit5 ，其相對應的起始時間分別是t0、tl、t3與t5，則丁卩-pos0=t0-T0 * Tpposl=tl-T0 * Tppos3=t3~T〇 » Tp-P〇s5=t5-T0 。 098141266 表單編號A0101 第9頁/共21頁 0982070775-0 201120460 [0020] 步驟S304，判斷模組230判斷是否已獲得指定數量的各個 位元的起始時間與選擇的時脈週期起點的時間差。在本 實施例中，對於每一位元（例如：bit0-bit6)，需要 至少1 〇個該位元的起始時間與選擇的時脈週期起點的時 間差’判斷模組230判斷計算得到的每一位元的起始時間 與選擇的時脈週期起點的時間差是否均已達到1〇個。若 未獲得指定數量的各個位元的起始時間與選擇的時脈週 期起點的時間差，則返回步驟S302，從獲取的時脈訊號 15的波形中選擇另一個時脈週期，並且從資料訊號14的 波形中識別該時脈週期内傳送的各個位元的起始時間。 需要說明的是，若獲取的時脈訊號15的波形中沒有其他 的時脈週期，則返回步驟S301，重新獲取低壓差分訊號 13的資料訊號14以及時脈訊號15的波形。 [0021] 若已獲得指定數量的各個位元的起始時間與選擇的時脈 週期起點的時間差，則步驟S305，統計模組240計算各個 位元的起始時間與選擇的時脈週期起點的時間差的最小 值及最大值。例如，對於低壓差分訊號13，計算得到1〇 個Tpposi，分別是 1 0 55、10 64、1〇. 58、1 0 73、 10. 65、1〇. 52、1〇. 65、10. 75、10. 87、10. 73，單位 納秒（ns)，則統計模組240算得Tpposl的最小值是 10· 52ns，最大值是ι〇· 87ns。在本實施例中，統計模組 240還用於分析計算得到的各個位元的起始時間與選擇的 時脈週期起點的時間差的最小值及最大值是否符合技術 規範。圖6給出了低壓差分訊號時序關係的技術規範。根 據該技術規範，第一位元脈衝位置的最小值是 098141266 表單編號A0101 第10頁/共21頁 0982070775-0 201120460 (Τ/7-0 〇χ ，〇ns，最大值是（T/7 + 0.2)ns，其中Τ表示時脈 週期。例如 ST=75ns，則技術規範中的最小值是 上& 4nS，最大值是1〇· 914ns。因此，若統計模組240 &于引某個時脈週期為75ns的低壓差分訊號13的Tp- 的最小值是1 〇. 52，最大值是1 〇. 87，則計算得到的 TPP〇sl符合技術規範。 [0022] Ο [0023] G [0024] [0025] [0026]201120460 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a signal testing system and method, and more particularly to a low voltage differential signal timing testing system and method. [Prior Art] [0002] Low Voltage Dif ferential Signal (LVDS) is a low-swing signal transmission technology. LDVS has the advantages of high speed, low power consumption, low noise, low cost, etc. Data transmission A has been widely used. ❹ [0003] The correctness of the low-voltage differential signal timing relationship is an important guarantee for reliable data transmission. At present, the low-voltage differential signal timing test needs to rely on the operator's. +.. .. .... . Manual operation. Manually operated test _ method wood only gold _ rate: Confucianism and easy error, can not meet the competitive needs of fast high quality production. SUMMARY OF THE INVENTION [0004] In view of the above, it is necessary to provide a low-voltage differential signal timing test system and method' capable of quickly and accurately testing the timing relationship of low-voltage differential signals. [0005] A low-voltage differential signal timing test system 'the low-voltage differential signal includes a data signal and a pulse signal, the system includes: a waveform acquisition module, configured to acquire a waveform of the data signal and a pulse signal; and a waveform recognition module For selecting a clock cycle from the waveform of the clock signal, identifying a start time of each bit transmitted in the selected clock cycle from the waveform of the data signal, and a timing analysis module for calculating each bit The difference between the start time and the start of the selected clock cycle; the statistical module is used to start the time of each bit according to multiple calculations and the selected time gland 098141266 Form No. A0101 Page 3 of 21 Page 0982070775-0 201120460 The time difference between the starting points of the period, the minimum and maximum values of the time difference between the start time of each bit and the start of the selected clock cycle; and the output module, 'for the start of each bit The minimum and maximum time difference between the time and the start of the selected clock cycle. [0007] [0007] 098141266 A low-voltage differential signal timing test method, the low-voltage differential signal includes a data signal and a pulse signal, the method comprising the steps of: acquiring a waveform of the data signal and a pulse signal; and a clock signal from the clock signal Selecting the clock period in the waveform; identifying the start time of each bit transmitted in the selected clock period from the waveform of the data signal; calculating the start time of each bit "time difference from the start of the selected clock period" Calculating the minimum and maximum values of the time difference between the start time of each bit and the start of the selected clock cycle based on the time difference between the start time of each bit and the start of the selected clock cycle; The minimum and maximum values of the time difference between the start time of each bit and the start of the selected clock cycle are output. The low-voltage differential signal timing test system and method of the invention can quickly and accurately test the timing relationship of the low-voltage differential signals. [Embodiment] Referring to Figure 1, a schematic diagram of an application environment of a preferred embodiment of the low voltage differential signal timing test system of the present invention is shown. The low-voltage differential signal 〖3 includes the data signal 14 and the time pulse signal 15, and the timing relationship of the low-voltage differential signal 13 is the time relationship of the data signal 14 with respect to the clock signal 15. The low voltage differential signal timing test system 1 is operated in a computer. The computer is in communication with the oscilloscope 12 and the display device 16. The oscilloscope 12 detects the data signal 14 and the clock signal 15 of the low voltage differential signal 13 through the test probe. Refer to Figure 2 for the low-voltage differential signal timing test system in Figure 1. Form No. A0101 Page 4 of 21 0982070775-0 [0009] 201120460 Functional Module Diagram. The low-voltage differential signal timing test system 10 includes a waveform acquisition module 200, a waveform recognition module 210, a timing analysis module 220, a determination module 230, a statistics module 240, and an output module 250. [0010] The waveform acquisition module 200 is configured to acquire waveforms of the data signal 14 and the clock signal 15. In the present embodiment, the waveform acquisition module 2 sends a waveform capture command to the oscilloscope 12. According to the waveform capture command, the oscilloscope 12 captures the waveforms of the data signal 14 and the clock signal 15 and returns the waveforms of the captured data signal 14 and the clock signal 丨 5 to the computer. As shown in FIG. 4, the 〇 curve 41 is the waveform of the data signal 14, and the curve 40 is the waveform of the clock signal 15. [0011] The waveform recognition module 210 is configured to select a clock from the acquired waveform of the clock signal 丨5, and identify the transmission in the clock cycle for each waveform of the lion coffee & data signal 14 The start time of each bit. In the present embodiment, the waveform recognition module 210 determines the start time of each bit by identifying the bit in which the value has changed. Generally speaking, each bit of Zixiao 14 is taken as 1 or 根据 according to the level of its voltage value. Usually, the voltage is 1 and the low voltage is 0. If the value of a bit differs from the value of the pre-bit it, the value of the bit changes. For example, if the first bit transmits 0, the second bit transfers the value of the second bit. Alternatively, if the first bit transmits 1 and the second bit transmits 0 ', the value of the first bit changes. At this time, the time point at which the value changes is the start time of the second bit. In the present embodiment, 7 bits (blt〇_bit6) are transmitted every clock cycle. As shown in FIG. 4, the waveform recognition module 210 selects the clock period 42, and the start point of the clock period 42 is τ〇 end point 疋 'The waveform recognition module 21 identifies the clock period "inside 098141266 form number Α0101 0982070775-0 Page 5 of 21 201120460 The transmitted 7-bit is 1100101' ie bit0 = l, bitl = l, bit2 = C, bit3 = 〇, bit4 = l, bit5 = 0, bit6 = l. Due to the previous clock cycle The last bit transmitted is 〇, so the bits whose values are changed are bitO, bit2, bit4, bit5, and bit6, and their corresponding start times are 10, 12, 14, 15, and 16. [0012] The timing analysis module 220 is configured to calculate a time difference between the start time of each identified bit and the start of the selected clock cycle. In this embodiment, as shown in FIG. 5, 7 bits are transmitted per clock cycle (bit). 〇_bit6), the time difference between the start time of the first bit and the start of the clock cycle is recorded as Tp_P〇s0, and the time difference between the start time of the second bit and the start of the clock cycle is recorded as Tpp〇sl... ...., the time difference between the start time of the seventh bit and the start of the clock cycle is recorded as Tpp0S6 Tpp0S〇-TpD〇S6 represents the timing relationship of the low voltage differential signal 13. Depending on the starting time of each identified bit, the time difference between each identified bit and the selected clock cycle start point can be calculated. As shown in Fig. 4, the bit whose value is changed is bu〇bit2 bit4, bit5 and bit6, and the corresponding start time is divided into another J疋t0 U, t4, t5 and t6 'the start time of the clock cycle 42 is T0, then Tpp〇s0=t0-T0, Tpp〇s2=t2-T0, Tp-P〇s4 = t4-T0, TPP〇S5 = t5-TO, TppOS6 = t6-T0. Another example is if the value changes The bits are bit 〇, bitl, ... "and ^", and their corresponding start times are respectively 'ttl, . and ', then Tp — P〇s0=t0-T0 > Tpp〇sl=tl- T0 - Tpp 〇 s3 = t3 - T0 > Tp - pos5 = t5 - TO 判断 The determination module 230 is configured to determine whether the time difference between the start time of the specified number of bits and the start of the selected clock cycle has been obtained. . In this embodiment 098141266 Form No. ΗΠ0ΗΠ Page 6/Total 21 Page 0982070775-0 [0013] In the example 2020, for each bit (eg: bit〇_bit6), at least 10 starts of the bit are required. The time difference between the time and the start of the selected clock cycle, the determining module 230 determines whether the calculated time difference between the start time of each bit and the start of the selected clock cycle has reached one. [0014] The statistics module 240 is configured to calculate the minimum and maximum values of the time difference between the start time of each bit and the start of the selected clock cycle. For example, for the low-voltage differential signal 13, § ten noses get 1 Tpp0si, which are 1 〇. 55, 10.64, 10.58, 10.73, 10.65, ι〇·52, 1〇65, Ο 10· 75, 10. 87, 10.73, in nanoseconds (ns), the statistical module 240 calculates that the minimum value of Tpposl is 1〇. 52ns, and the maximum value is 1〇. 87ns. In this embodiment, the statistic module 240 is further configured to analyze the minimum value and the maximum value of the calculated time difference between the start time of each bit and the start of the selected clock cycle. Figure 6 shows the technical specifications for the low-voltage differential signal timing relationship. According to this specification, the minimum value of the first bit pulse position is (T/7-0.2) ns, and the maximum value is (T/7 + 0.2) ns ' where T represents the clock period. For example, if T = 75ns ... :. . . ' then the minimum value in the specification is 1 〇 514 ns, and the maximum value is W 914 ns. Therefore, if the statistical module 240 calculates that the minimum value of the Tppos1 of the low-voltage differential signal 13 with a clock period of 75 ns is 1 〇. 52 'the table value is 10.87, the calculated Tpposl conforms to the technical specification [0015] The round-out module 250 is used to output the minimum and maximum values of the time difference between the start time of each bit and the start of the selected clock cycle. In the present embodiment, the 'round-out module 250 displays the minimum value and the maximum value of the time difference between the start time of each bit and the selected clock cycle 'month start point in the computer 11 098141266 Form No. A0101 Page 7 / A total of 21 pages of 0982070775-0 201120460 display devices 1 6 on. In addition, the output module 250 outputs a case where the minimum value and the maximum value of the time difference between the start time of each bit and the start of the selected clock cycle are in accordance with the specifications. [0016] Referring to FIG. 3, it is a flow chart of a preferred embodiment of the low voltage differential signal timing test method of the present invention. [0017] Step S301, the waveform acquisition module 200 acquires the waveform of the data signal 14 and the pulse signal 15 of the low voltage differential signal 13. In the present embodiment, the waveform acquisition module 200 sends a waveform capture command to the oscilloscope 12. According to the waveform capture command, the oscilloscope 12 captures the waveforms of the data signal 14 and the clock signal 15, and returns the captured data signal 14 and the waveform of the clock signal 15 to the computer 11. As shown in FIG. 4, the curve 41 is the waveform of the data signal 14, and the curve 40 is the waveform of the clock signal 15. [0018] Step S302, the waveform recognition module 210 selects a clock cycle from the waveforms of the acquired clock signal 15, and identifies the start time of each bit transmitted in the clock cycle from the waveform of the data signal 14. . In the present embodiment, the waveform recognition module 210 determines the start time of each bit by identifying the bit in which the value has changed. Generally, each bit of the data signal 14 takes a value of 1 or 0 depending on the voltage value. Generally, the high voltage value is 1 and the low voltage value is 0. If the value of a bit differs from the value of the previous bit, the value of that bit changes. For example, if the first bit transmits 0 and the second bit transmits 1, the value of the second bit changes. Alternatively, if the first bit transmits 1 and the second bit transmits 0, the value of the second bit changes. At this time, the time point at which the value changes is the start time of the second bit. In the present embodiment, 7 bits (b i 10 - b i 16 ) are transmitted every clock cycle. As shown in FIG. 4, the waveform identification module 098141266 form number A0101 page 8 / 21 page 0992070775-0 201120460 210 selects the clock cycle 42, the starting point of the clock cycle 42 is TO, the end point is D1, the waveform recognition module 21〇 Identifies that the 7-bit transmitted in the clock cycle 42 is 1100101, that is, bitO = l, bitK, bit2 = 0, bit3 = 0, bit4 = l, bit5 = 0, and bit6 = l. Since the last bit transmitted in the previous clock cycle is 〇, the bits whose values are changed are bit2, bit4, bit5, and bit6, and their corresponding start times are t0, t2, t4, t5, and t6, respectively. . [0019] In step S303, the timing analysis module 220 calculates the time difference between the start 0 time of each identified bit and the start of the selected clock cycle. In this embodiment, referring to FIG. 5, each bit cycle transmits 7 bits (bit〇_bit6), and the time difference between the start time of the first bit and the start of the clock cycle is recorded as Tp_posO, the second bit. The time difference between the start time of the element and the start of the clock cycle is denoted as Tpposl......., and the time difference between the start time of the seventh bit and the start of the clock cycle is denoted as Tppos6. Tppos〇-Tppos6 represents the order relationship of the low-voltage differential signal 13 . Depending on the start time of each bit identified, the individual bits identified by the nose can be the time lag of the start of the selected clock cycle. For example, as shown in FIG. 4, the bits whose values are changed are bit〇., bit2, bit4, bit5, and bit6, and the corresponding start times are t0, t2, t4, t5, and t6, respectively. The start time of the pulse period 42 is TO, then Ding 卩卩〇 3 〇 = 1; 0-1 '0, D? ? 〇52 = 12-1'0, 卩卩- P〇s4 = t4-T0, Tppos5 = t5-T0, Tppos6 = t6-T0. For another example, if the bit of the value transition is bitO, bitl, bit3, and bit5, the corresponding start times are t0, tl, t3, and t5, respectively, then Ding-pos0=t0-T0 * Tpposl=tl- T0 * Tppos3=t3~T〇» Tp-P〇s5=t5-T0. 098141266 Form No. A0101 Page 9 of 21 0982070775-0 201120460 [0020] Step S304, the determining module 230 determines whether the time difference between the start time of the specified number of individual bits and the start of the selected clock cycle has been obtained. In this embodiment, for each bit (eg, bit0-bit6), at least one time difference between the start time of the bit and the start of the selected clock cycle is required. The determination module 230 determines each calculated calculation. Whether the time difference between the start time of one bit and the start of the selected clock cycle has reached one. If the time difference between the start time of the specified number of individual bits and the start of the selected clock cycle is not obtained, then returning to step S302, another clock cycle is selected from the waveform of the acquired clock signal 15 and the data signal 14 is received. The start time of each bit transmitted during the clock cycle is identified in the waveform. It should be noted that if there is no other clock cycle in the waveform of the acquired clock signal 15, the process returns to step S301 to reacquire the waveforms of the data signal 14 and the clock signal 15 of the low voltage differential signal 13. [0021] If the time difference between the start time of the specified number of individual bits and the start of the selected clock cycle has been obtained, then in step S305, the statistics module 240 calculates the start time of each bit and the start of the selected clock cycle. The minimum and maximum time difference. For example, for the low-voltage differential signal 13, one Tpposi is calculated, which is 1 0 55, 10 64, 1〇. 58, 1 0 73, 10. 65, 1〇. 52, 1〇. 65, 10.75 10.87, 10.73, in nanoseconds (ns), the statistical module 240 calculates that the minimum value of Tpposl is 10·52 ns, and the maximum value is ι〇·87 ns. In this embodiment, the statistic module 240 is further configured to analyze whether the calculated minimum value and maximum value of the start time of each bit and the start time of the selected clock cycle meet the technical specifications. Figure 6 shows the technical specifications for the low-voltage differential signal timing relationship. According to this technical specification, the minimum value of the first bit pulse position is 098141266 Form No. A0101 Page 10 / Total 21 Page 0982070775-0 201120460 (Τ/7-0 〇χ , 〇 ns, the maximum value is (T/7 + 0.2) ns, where Τ denotes the clock period. For example, ST=75ns, the minimum value in the technical specification is upper & 4nS, and the maximum value is 1〇· 914ns. Therefore, if the statistical module 240 & The minimum value of Tp- of the low-voltage differential signal 13 with a clock period of 75 ns is 1 〇. 52, and the maximum value is 1 〇. 87, then the calculated TPP 〇sl conforms to the technical specification. [0022] Ο [0023] G [ 0024] [0026] [0026]
步 ^ Π C ，輪出模組250輸出各個位元的起始時間與選擇 的時脈週期起點的時間差的最 小值及最大值。在本實施 】中輪出模組2 50將各個位元的起始時間與選擇的時脈 週期起點的時間差的最小值及最大值顯示在與電腦11相 連的顯示設備16上。此外，所述輸出模組250還輸出各個 位70的起始時間與選擇的時脈週期起點的時間差的最小 值及最大值符合技術規範的情況。 良丁'上所述’本發明符合發明專利要件，爰依法提出專利 申請。惟’以上所述者僅為本發明之較佳實施例，本發 明之範圍並不以上述實施例為限，舉凡熟悉本案技藝之 人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本發明低壓差分訊號時序測試系統較佳實施例的應 用環境示意圖。 圖2係圖1中低壓差分訊號時序測試系統的功能模組圖。 圖3係本發明低壓差分訊號時序測試方法較佳實施例的流 程圖。 098141266 表單煸號Α0101 第11頁/共21頁 0982070775-0 201120460 [0027] 圖4係低壓差分訊號的資料訊號及時脈訊號的波形圖。 [0028] 圖5係低壓差分訊號時序關係的示意圖。 [0029] 圖6係低壓差分訊號時序關係的技術規範的示意圖。 【主要元件符號說明】 [0030] 低壓差分訊號時序測試系統10 [0031] 電腦11 [0032] 示波器12 [0033] 低壓差分訊號 i 13 [0034] 資料訊號14 [0035] 時脈訊號15 [0036] 顯示設備16 [0037] 波形獲取模組 200 [0038] 波形識別模組 210 [0039] 時序分析模組 220 [0040] 判斷模組230 [0041] 統計模組2 4 0 [0042] 輸出模組2 5 0 [0043] 獲取資料訊號及時脈訊號的波形S301 [0044] 選擇時脈週期 始時間S302 ，識別該時脈週期内傳送的各個位元的起 098141266 表單編號A0101 第 12 頁/共 21 頁 0982070775-0 201120460 [0045] [0046] [0047] [0048] ❹ 計算各個位元的起始時間與選擇的時脈週期起點的時間 差 S303 是否達到指定數量S304 計算各個位元的起始時間與選擇的時脈週期起點的時間 差的最小值及最大值S305 輸出各個位元的起始時間與選擇的時脈週期起點的時間 差的最小值及最大值S306 ❹ 098141266 表單編號A0101 第13頁/共21頁 0982070775-0Step ^ Π C, the round-out module 250 outputs the minimum value and the maximum value of the time difference between the start time of each bit and the start of the selected clock cycle. In the present embodiment, the middle wheel module 2 50 displays the minimum and maximum values of the time difference between the start time of each bit and the start of the selected clock cycle on the display device 16 connected to the computer 11. In addition, the output module 250 also outputs a minimum value and a maximum value of the time difference between the start time of each bit 70 and the start of the selected clock cycle in accordance with the specifications. The invention is in accordance with the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing the application environment of a preferred embodiment of the low voltage differential signal timing test system of the present invention. Figure 2 is a functional block diagram of the low voltage differential signal timing test system of Figure 1. Fig. 3 is a flow chart showing a preferred embodiment of the low voltage differential signal timing test method of the present invention. 098141266 Form Α Α 0101 Page 11 of 21 0982070775-0 201120460 [0027] Figure 4 is a waveform diagram of the data signal and pulse signal of the low voltage differential signal. [0028] FIG. 5 is a schematic diagram of a low voltage differential signal timing relationship. [0029] FIG. 6 is a schematic diagram of a technical specification of a low voltage differential signal timing relationship. [Main Component Symbol Description] [0030] Low Voltage Differential Signal Timing Test System 10 [0031] Computer 11 [0032] Oscilloscope 12 [0033] Low Voltage Differential Signal i 13 [0034] Data Signal 14 [0035] Clock Signal 15 [0036] Display device 16 [0037] waveform acquisition module 200 [0038] waveform recognition module 210 [0039] timing analysis module 220 [0040] determination module 230 [0041] statistical module 2 4 0 [0042] output module 2 5 0 [0043] Obtaining the waveform of the data signal and the pulse signal S301 [0044] Selecting the clock period start time S302, identifying the individual bits transmitted during the clock cycle 098141266 Form No. A0101 Page 12 of 21 0982070775 [0048] [0048] [0048] ❹ Calculate whether the time difference S303 between the start time of each bit and the start of the selected clock cycle reaches the specified number S304. Calculate the start time and selection of each bit. Minimum value and maximum value of the time difference of the start of the clock cycle S305 The minimum value and maximum value of the time difference between the start time of each bit and the start of the selected clock cycle are output S306 ❹ 098141266 Form No. A010 1 Page 13 of 21 0982070775-0