TW201418992A - Data transmission control method and device of serial peripheral interface master device - Google Patents

Abstract

A data transmission control method of serial peripheral interface (SPI) master device includes: providing a clock signal, which includes a plurality of cycles, and each cycle includes a leading edge and a trailing edge; sampling data at a sampling data point, wherein the sampling data point is arranged between the leading edge and the trailing edge of current cycle in the cycles; and changing data in a changing data point, wherein the changing data point is arranged between the trailing edge of the current cycle and the leading edge of a next cycle of the current cycle. The above-mentioned data transmission control method can meet four data transmission mode defined by SPI specifications simultaneously. A data transmission control device of SPI master device is also disclosed.

Description

Data transmission control method and device for serial peripheral interface main device

The invention relates to a data transmission control method and device, in particular to a data transmission control method and device for a serial peripheral interface main device.

The serial peripheral interface (SPI) defines a clock polarity (CPOL) bit and a clock phase (CPHA) bit for the user to set the desired data transmission mode. Referring to FIG. 1, when CPOL=0, in the clock SCK generated by the SPI master device, the rising edge is the leading edge and the falling edge is the trailing edge of the period ( Trailing edge). When CPOL=1, in the clock SCK generated by the SPI master device, the falling edge is the leading edge of the cycle, and the rising edge is the trailing edge of the cycle.

Referring again to FIG. 1, when CPHA=0, the master device changes the data MOSI outputted by the master device at the trailing edge of the cycle, as indicated by the dotted arrow; and samples the data output from the slave device at the leading edge of the cycle. As shown by the solid arrow. Referring to FIG. 2, when CPHA=1, the master device changes the data MOSI outputted by the master device at the leading edge of the cycle, as indicated by the dotted arrow; and samples the data MISO output from the slave device at the edge of the cycle, such as the solid arrow. Shown. Therefore, a total of four data transmission modes are defined in the sequence peripheral interface, that is, CPOL=0, CPHA=0; CPOL=1, CPHA=0; CPOL=0, CPHA=1, and CPOL=1, CPHA=1. In order to meet the above specifications, the complexity of the circuit design of the SPI device is increased.

In summary, how to simplify the circuit design of the SPI device is currently the goal of great efforts.

The invention provides a data transmission control method and device for a serial peripheral interface main device It is a four-data transmission mode defined by the SPI specification in a single data transmission mode, so the SPI master can be realized with a relatively simple circuit design.

The data transmission control method of the sequence peripheral interface main device according to an embodiment of the present invention includes: providing a clock signal including a plurality of periods, and each period includes a leading edge and a trailing edge; sampling data at a sampling data point, Wherein the sampled data points are between the leading edge and the trailing edge of the current cycle of one of the plurality of cycles; and the data is changed at a change point, wherein the change of the data point is between the trailing edge of the current cycle and the leading edge of the current cycle .

A data transmission control device for a serial peripheral interface host device according to another embodiment of the present invention includes a clock generator and a data controller. The clock generator is configured to provide a clock signal including a plurality of periods, and each period includes a leading edge and a trailing edge. The data controller is configured to sample data at a sampling data point and change data at a change data point, wherein the sampling data point is between the leading edge and the trailing edge of one of the plurality of cycles; and changing the data point after the current cycle And between the leading edge of the current cycle below the current cycle.

The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the appended claims.

The data transmission control method and device of the sequence peripheral interface main device of the present invention can satisfy the four data transmission modes defined by the SPI specification in a single data transmission mode, so that the SPI master device can be realized with a simplified circuit design. It will be understood that the relevant technical content not described in detail below may follow the SPI specification.

Referring to FIG. 3 and FIG. 4, a data transmission control method for a serial peripheral interface master device according to an embodiment of the present invention is described. First, a clock signal SCK is provided, which includes a plurality of periods, and each period includes a leading edge and a trailing edge (S31). It can be understood that if the clock signal SCK is CPLO=0, the leading edge is the rising edge of the cycle, and the trailing edge is the falling edge of the cycle. If the clock signal SCK is CPLO=1, the leading edge is the falling edge of the cycle, after The edge is the rising edge of the cycle. Then, sampling data at a sampling data point (S32) or changing data at a change point (S33), wherein the sampling data point is between the leading edge and the trailing edge of one of the plurality of cycles; and changing the data point It is between the trailing edge of the current cycle and the leading edge of the current cycle.

Referring to FIG. 4, the SPI master device generates a signal MOSI according to the clock signal SCK (CPLO=0; CPLO=1). First, cycle 1 changes the data between the trailing edge of the start cycle and the front edge of cycle 1, and cycle 2 changes the data between the trailing edge of cycle 1 and the front edge of cycle 2, as indicated by the dashed arrow, and so on. In this way, the SPI master can generate the signal MOSI to be output. According to the clock signal SCK and the signal MOSI outputted by the master device shown in FIG. 4, the slave device can obtain the correct sampling regardless of the cycle leading edge (CPHA=0) or the trailing edge (CPHA=1) of the clock signal SCK. Information, as indicated by the arrow of the solid line. Referring to FIG. 5, according to the clock signal SCK output by the master device, the slave device changes the data (shown by the arrow of the dotted line) at the front edge of the cycle (CPHA=1) or the trailing edge (CPHA=0) to generate Signal MISO, the main device can also obtain the correct data by sampling between the leading edge and the trailing edge of the cycle, as indicated by the arrow of the solid line.

In an embodiment, in order to correctly sample the data, the sampled data points may be at an intermediate point between the leading edge and the trailing edge of the cycle, as shown in FIG. Similarly, changing the data point can be at the middle point between the trailing edge of the current cycle and the leading edge of the next cycle, as shown in Figure 5. It is to be noted that the embodiments shown in Figures 4 and 5 are merely illustrative and are not intended to limit the invention.

Referring to FIG. 6, a data transmission control apparatus for a serial peripheral interface main device according to an embodiment of the present invention includes a clock generator 61 and a data controller 62. The clock generator 61 is configured to provide a clock signal SCK, including a plurality of periods, and each period includes a leading edge and a trailing edge. The data controller 62 is configured to sample data at a sampling data point and change data at a change data point, wherein the sampling data point is between a front edge and a trailing edge of one of the plurality of cycles; and changing the data point in the current cycle The trailing edge and the leading edge of the current cycle below the current cycle. The data transmission control device of the sequence peripheral interface master device of the present invention has been sampled and changed data as described above, and will not be described herein.

Combining the above, the data transmission control method of the serial peripheral interface main device of the present invention The device can meet the four data transfer modes defined by the SPI specification in a single data transfer mode, so the SPI master can be implemented with a simplified circuit design.

The embodiments described above are only intended to illustrate the technical idea and the features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

61‧‧‧ Clock Generator

62‧‧‧ data controller

SCK‧‧‧ clock signal

MOSI‧‧‧ signal

MISO‧‧‧ signal

Data transmission control method for S31~S33‧‧‧ sequence peripheral interface main device

Figure 1 is a timing diagram showing the data transfer modes of CPOL = 0 or 1 and CPHA = 0 as defined by the SPI specification.

Figure 2 is a timing diagram showing the data transfer modes of CPOL = 0 or 1 and CPHA = 1 as defined by the SPI specification.

3 is a flow chart showing the steps of a data transmission control method for a serial peripheral interface master device according to an embodiment of the present invention.

4 and FIG. 5 are timing diagrams showing data transmission modes of a data transmission control method for a serial peripheral interface master device according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a data transmission control apparatus for a serial peripheral interface master device according to an embodiment of the present invention.

Data transmission control method for S31~S33‧‧‧ sequence peripheral interface main device

Claims (10)

A data transmission control method for a sequence peripheral interface main device includes: providing a clock signal including a plurality of periods, and each period includes a leading edge and a trailing edge; Point sampling data, wherein the sampling data point is between the leading edge and the trailing edge of one of the plurality of cycles; and changing data at a change data point, wherein the changing data point is in the current cycle The trailing edge and the leading edge of a cycle below the current cycle. The data transmission control method of the sequence peripheral interface master device of claim 1, wherein the sample data point is at an intermediate point between the leading edge and the trailing edge of the current period. The data transmission control method of the sequence peripheral interface master device of claim 1, wherein the change data point is at an intermediate point between the trailing edge of the current period and the leading edge of the next period. The data transmission control method of the sequence peripheral interface master device according to claim 1, wherein the leading edge is a rising edge. The data transmission control method of the sequence peripheral interface master device according to claim 1, wherein the leading edge is a falling edge. A data transmission control device for a serial peripheral interface main device includes: a clock generator for providing a clock signal, the clock signal includes a plurality of periods, and each period includes a leading edge and a a trailing edge; and a data controller for sampling data at a sampling data point and changing data at a change data point, wherein the sampling data point is before the current period of one of the plurality of cycles And between the trailing edge; and the change data point is between the trailing edge of the current period and the leading edge of a period below the current period. The data transmission control device of the sequence peripheral interface master device of claim 6, wherein the sample data point is at an intermediate point between the leading edge and the trailing edge of the current cycle. The data transmission control device of the sequence peripheral interface main device according to claim 6, wherein the data transmission control device The intermediate point between the trailing edge of the current period and the leading edge of the next period is changed. The data transmission control device of the sequence peripheral interface master device of claim 6, wherein the leading edge is a rising edge. The data transmission control device of the sequence peripheral interface main device of claim 6, wherein the leading edge is a falling edge.