TW200921399A - Method of a single-step logic analyzer processing multi-step trigger by using software - Google Patents

Abstract

The present invention is related to a method of a single-step logic analyzer processing multi-step trigger by using software, in particular a method of connecting the single-step logic analyzer and a computer installed with the software. The software is capable of actuating a multi-step function and setting a multi-step trigger condition. The logic analyzer uses the first step trigger condition to detect a signal and capture a data and store the data which meet the first step trigger condition into memory. The data is then transmitted to the software to match the multi-step trigger condition. The correspondence data are marked by the software and plotted as waveforms on a screen. Due to the lower cost of software research and manufacturing, the production cost of the product is reduced. Furthermore, by using the trigger marking function, data matching the trigger condition can be shown on the computer screen to reduce the measuring time.

Description

200921399 IX. INSTRUCTIONS · · Technical Fields of the Invention The present invention provides a method for multi-step electric shock using a software for a single-stage logic analyzer, especially a single-stage analyzer and a computer equipped with software. After the connection = use software to carry on the multi-step pain of the data transmitted by the single-stage logic analyzer __, Shuna low product cost. [Prior Art] Crying has become more and more digital in today's electronic products, resulting in the traditional oscilloscope-deficient summer measurement of 8 to 16 channels to = τ digits, the necessary amount _ two: = mobile users It is convenient to tune the timing between digital circuits and analyze the characteristics of the circuit.

Today's logic analyzers are both pure and H (Asyn... succinct, - for non-synchronous mode analysis), and the other is the same cow model ^Us M〇de) also known as "time series 疋 疋 疋 pull (S y M〇de) is also called "single energy 〇n〇US used sampling clock is different ^ due to timing analysis and state analysis of a certain channel signal when sampling clock == medium, we are Among them, __合* is in the time series analysis mode 2:::: 200921399, the first type is "continuous storage assignment", the logic analyzer will have a fixed sampling clock inside it. The second type is the "sampling mode". It allows us to use the memory effectively. It does not exist in the flat slant. (4), only the county-time detection state will save the phase. (4) and the distance between the first and the fourth (four), if the notice number is not _ long time, you can improve the resolution and save memory ^ Another function of the logic analyzer is the qualifier (qua丨ifi ^ ) Q limited gamma, - the species For the trigger qualifier (τ丄二: 1 fier), the other is called the clock qualifier (

Qu a11f1e r), the meaning of the trigger qualifier 乇 you have _ plus condition, that is, the simultaneous triggering with the condition of the word recognition will occur, the trigger qualifier will add - turn _ condition, 35 trigger The external pulse m job & sub-language limit the sampling time when the temple qualifier, the user can enter the data 1 to 叾 &; _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ [The side of the work room can be effective _• ==::= In addition to the _ certificate, you can 杓5, which is convenient for the user to find the required signal in a short time T to become the logic analyzer of the factory. It is a single-order, which can only be used in the test and stored in the memory. It will appear as a problem that does not meet the user's needs. Therefore, there is a multi-level logic analyzer. 'The multi-level logic analyzer can set the touch of the piece, and when it is turned over, it will be stored in the memory when the condition is sent." The logic analyzer can sample the user's needs. . However, the multi-level logic analyzer is the logic of adding two more-order trigger conditions to the data judgment. Because of the riding of the logic, the speed of the I C is increased, and! The capacity of C also needs to be improved, which not only increases the difficulty of which technology, but also increases the cost of production and R&D, which leads to the lack of expensive multi-level logic analyzers. This is the inventor and engaged in six days. The goal of this industry is to improve. [Summary of the Invention] Ancient, therefore, (4) In view of the above-mentioned shortcomings, the people turned to relevant information, and through multiple evaluations and considerations, the Butterfly (4) (four) shirts were designed to reduce the cost of the product. The patented single-stage logic analyzer uses the software to perform multi-level triggering methods. The main purpose of Ming is that it is connected to the computer, the electric w version comes to the multi-level trigger condition 'and the logic analyzer automatically sets the first part of the software - the touch condition is a single-order trigger condition, and the logic analyzer is After the data is retrieved, ^^ and _ _ 疋 符合 符合 符合 符合 符合 符合 符合 符合 符合 符合 符合 符合 符合 符合 符合 θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ θ The data of the multi-level trigger condition 200921399 is drawn into a waveform, because the cost of software development and manufacturing is less, ~ the logic analyzer is expensive to manufacture, and i is the purpose of the name. The quiet cost can achieve the reduction of product cost. The second purpose of the present invention is that when the software is provided with the triggering object to judge that the data meets the multi-level triggering condition, the software will owe and mark the data until the data is judged; Bi Cai stopped, and because the software is the order of the mosquitoes, the counts of the county and the trigger conditions are displayed on the screen of the computer, that is, the comprehensive detection of the circuit, because the user enters the trigger condition. The data, the time of the search again search for other [implementation] and then (4) the time spent detecting. For the purpose and function of the present invention, the technical means of the present invention and the following are well understood. 4, special features and functions, please refer to the first, one by one, &one; block, S -, scales, three-dimensional appearance, series 2: block diagram, it can be clearly seen from the figure that the invention includes a logic knife The analyzer 1, the % brain 2 is composed of: = logic analyzer i is provided with (four) Wei U, and the control circuit u is secondary: the memory 12 and at least one of the measuring components 丄 3, 1 the heartpiece U There is a plurality of _131, and a central device 13 2 is provided at the end of _131^200921399, and the control circuit 24 is provided. 1Electrically connected with a transmission interface 5 Hai computer 2 is equipped with can be installed, its software 2:::= and on the transmission surface 2 2 2, decoding judgment module: 疋22 1 'input and There is another _== in the computer 2, and the four components are composed of '= each component is connected to the material, the system is connected with the computer 2, and then the logic is divided into the transmission line 1 line... the end of the fixture 132 and side to side =: 13 turn circuit detection side. J enters the connection, which can be shown in the figure. It is a flow chart of the steps of the present invention. As shown in the figure, it is seen that the logic U of the single order is made by the order] and is installed in the computer 2 ;, computer 2 connection, (1.) boot software = part settings. External trigger function, enter the trigger bar (1〇1) f The analyzer 1 or the start button of the software 22 is pressed to start the logic. a) cut 2 2 start _ series analysis sequence, then the first trigger condition forming signal is sent to the logical point / will be - order " called logic analysis (four) received the first meeting of the first-order trigger condition set to single order Trigger bar: After, 200921399 (10 4) logic analyzer i side of the treatment side is continuously stored in the memory 12 ^; remaining 'will detect the data h then _ test data meets the first-order trigger condition, if A 3 right Feng Wei The logic analyzer 1 is convenient for storing the predetermined memory i 2 capacity and measuring the poor material, stopping = material 'and transferring the coffee 12 (10). (10 5) After the software 2 2 receives the test data, it will judge according to the W code. If the test data meets the trigger condition, do not take the bamboo 1Q6. If the test data does not meet the trigger condition, the software 2 2 Just fit ', step ι〇4.曰 ~ domain to logic analyzer! And carry out (ι〇6)=22 jingjing version of her mark, then change = no _ the data for multi-level trigger condition comparison judgment, combined trigger condition, then the software 2 2 will be the body again? 9 ah, after the completion of all the data, the software will stop the soft comparison. (10 7) Use 敕 _ " 2 to become _, and mark each line <$ transfer to electricity ^ Please refer to the second county 2 1 for display. As shown in the block diagram and the sagittal figure, it is the block diagram of the present invention and the input interface 2 2 235. It can be clearly seen from the financial system that the functions of the logic analyzer 1 and the software 22 are utilized, and the trigger is 10 200921399 Condition or other money slave, and the input interface 2 2 2 domain memory unit 2 2 1 access to the recording and the memory unit 2 2 1 can transmit the parameters to the logic analyzer 2 through the transmission interface 14 The logic analysis-like detection data is also transmitted to the memory unit 2 through the transmission interface i 4 , and the memory unit transmits the detection data to the decoding determination module 2 2 3 , and the detection determination module 2 2 3 can perform the detection (4). The judgment processing of the multi-condition condition and the trigger flag 'and the detection after the processing (four) is decoded into the waveform data data 'and the decoding __2 2 3 reading the job «materials into the memory single ΐ> 2 2 1 , the memory The unit 2 2 1 outputs the wave data (4) to the screen 2 through the output interface 2 2 4, or outputs the wave data to the storage device 2 of the computer 2 for storage. The single-stage logic analyzer 1 utilizes the plurality of wires 131 and fixtures provided on the measurement unit 丄3! 3 2 form a plurality of measurement channels (as shown in the first figure), and the trigger conditions of each measurement channel have any signal (D 〇n, t C are), rising edge (Raising Edge), falling edge (Fa 1 1 ing Edge), High + L eve 1 , low level (l 〇w L eve 1 ), ^1Slng or Falling Edge, Trigger Width Time, Waiting for (T rigger Wa it ) and trigger interval (

Trigger Space Time), and when the logic analysis 200921399 单 single-order trigger condition automatic setting software 2 2 the first-order trigger condition, the side delay, the trigger-like trigger count ship _, and if the starter is defined, the lag analysis It seems that the setting of the stator ship will capture the data. 8. The logic analysis seems to set the storage capacity of the memory 12, and the logic analyzer will continue to store when the logical miscellaneous materials are continuously stored in the memory i 2 and judged to detect the first-order trigger condition of the bedding material. The data 'until the storage capacity of the set memory 12 is stored again, the operation will stop. If the storage capacity of the memory i 2 is set to 5 (10), the logic analyzer will judge the condition of the first__ condition. Take and bribe 50% of the & / / The above steps can be known, the logic is divided into four parts, and the data is transmitted to the software 2 2, and the data is transmitted to the software. More _ condition, software 2 ^ will transmit the signal to make the logic analyzer 1 carry out again - the data training, because of the logic: the analyzer 1 in every money line #料娜作#之在在停停取的,使相相The neighboring data is not a continuous signal. Therefore, if the software changes the trigger module, the sampling function can be disabled. The fifth month is not referred to as the waveform diagram of the preferred embodiment of the present invention. The figure 'is clearly seen from the financial, which is the waveform after the IIC analysis. IIC is the synchronization of serial transmission. The transmission interface, due to the serial trigger 200921399 - the data is continuous, then the f_trigger waits for the chopping line (SDA) and the string (the heart two (3) line, its content has the beginning th H tL) two signals), read / Please...~, his Ud吣... :Γ Confirm (ACK/NAc:):::::ta; , side IC bus address trigger t〇P)

The number of bits, the order is the start of the judgment; = the number is based on the high level of the address, the judgment address _ take time, print: ==_~ set true - when set to confirm (ACK), sda ^ L rising edge .

If the software does not turn off the trigger wait function, when the data of the multi-level triggering level occurs (trigger completion), each level may contain data that does not meet the conditions of the face-to-face condition, so that the triggered data does not conform to the continuous Sexually pure' and the software 2 2 depends on the trigger wait, if the data is subjected to the eve trigger condition and the current data does not meet the trigger condition, the data will be re-triggered, such as the first-order match. Trigger bar ^ 'But if the second-order data is not met, it will re-find the data that meets the first-order, and then make the second-order judgment on the data. The multi-step setting set when the above-mentioned fe/fl I c bus address is triggered, 13 200921399 2: The number can be increased or decreased according to the change of the number of bits of the address. _ Others are included in the patent model _ of the present invention, and the _ is logically analyzed by 'software 2 2 as the triggering condition of logic analysis like s 卩 、 +, '4, S CL high level' Instrument 1 judges whether the data symbol 2 2 Π- J1 2 _ heart 2 2 will meet the multi-condition condition, and ::Γ22 will trigger the trigger on the 0th, 9th or both. The conditional judgment g::2:::: is not judged. After the judgment of the data placement of each payment trigger condition is completed, the marker waveform is displayed and displayed on the screen 2 of the computer 2, if the data is not matched, the logic is The analyzer 1 performs the signal detection again, and the straight-through material is touched by the step==^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 0 In addition, 'because of the general logic analyzer 1 after judging that the trigger condition is completed, / to make scales - surgery bribes - a piece of the piece, and this t Ming Body 22 is completely marked with a mark, and it can be used. It can be used in accordance with the conditions of the t-recognition (4). The user does not need to spend any other time. It can save the detective 14 200921399 human limbs. 2 2 is a mark that can be based on the number of Zhao Zizu's a number, so that the user can easily follow the order and repeat the case. If the user knows that the circuit is detected between each trigger level. The range of the interval time is not triggered (minimum ^, can also increase the accuracy of 峨 _. - take a large value) as the trigger condition, because the single-order _ analysis ^ financial error logic body 2 2 is installed in _ 2, the logic and 'and' can be calculated by the computer 2 ^ after the computer 2 is limited by the order limit, because ... / her analyzer 1 does not cost, you can make the single-stage logic analyzer The equipment that can be seen everywhere in life can achieve the purpose of reducing the cost of the sixth and seventh figures. The data sampling diagram, and the embodiment, the other examples, show that the UART (U diagram' can be cleared from the figure.

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>"'l waveform after analysis, U is the asynchronous transmission interface of the serial transmission, data transmission, and the data contains the phase, f material ^ line for Party check) and 佟: , .5 The method of __ hair, .14 = analysis _ with the same speed T) mosquito sampling position, turn scale (data transfer field sampling position 増 plus 1/2 Bao: 15 200921399 'can make the sampling point At the central level of each class, since the sampling point of the software 2 2 can be compared with the actual data (four), the sampling position can be changed to avoid the data of the sampling analysis being located at the change point of the actual data, and the error is detected. In addition, the accuracy of sampling can be improved. In addition, if the waveform of UAR Ding only has 6 changes in level, it is easy to generate false triggers due to too few judgments (four), and the waveform width and the trigger level are different. In the wrong trigger system, the trigger width time of each layer is added. The trigger width time is the maximum value and the minimum value of the set trigger width. The trigger width can improve the accuracy of the tilt sampling. The above multi-level trigger condition can be set. Trigger interval time The location of the sample and the time of the singularity are not limited to the use of the synchronous transmission interface or the non-synchronous transmission interface, which can only be used to increase the trigger and error. The non-Z is limited to the patent scope of the present invention, such as using other Modifications and equivalent structures should be included in the scope of the patent of the present invention, and combined with Chen Ming. One of the other 'software 2 2 can also enter the step with the reverse level Wei, in the case of Bellow During the analysis, 'the reverse level can be turned on, so that the logic is captured. If the reading is high, the actual data will be regarded as low level. The UART and the UART should be single-chip and programmable. When the controller interface communicates, it is necessary to convert the level of the square to convert to each other, and the logic analyzer uses the reverse-level ship to distinguish between the fresh and the control (4) on the signal 16 200921399. 'Using the differential signal to transmit data UArt signal, the opposite signal line is in the pole.】 When using the two-way level function paste, the analyzer 1 uses the signal lines of the two reverse levels mentioned above. Mainly for single-stage logic analyzer 1 using software 2 ? The step of triggering, the software 22 can be set in the computer 2; 2 is connected with the single-stage logic analyzer 1, and the software 22 is used to set the condition of the d2 to the trigger condition of the single-stage logic analyzer 1 Sampling, and then sampling the sample stored in the memory 丄2 to the software 2 2, using the software 2 2 can perform multi-level trigger condition judgment on the data 'and the corresponding data is drawn into a waveform and displayed on the computer 2 On the screen 21, because the development and manufacturing cost of the software 22 is small, the cost of the product can be reduced. However, the above-mentioned inventions of the invention are more than the case of the invention. Therefore, the use of the present invention _ books and drawings as a simple silk decoration and equivalent structural changes 'all should be included in the patent scope of the present invention, combined with Chen Ming. The above-mentioned single-stage analysing device of the present invention is a method for performing multi-step triggering in the soft body, and in order to achieve its efficacy and purpose, the present invention is an invention excellent in practicality. In accordance with the requirements of the invention patents, I love to apply in accordance with the law, and I hope that the trial committee will grant the case as soon as possible to protect the hard work of the inventor. If there is any doubt in the audit committee, please do not hesitate to instruct the inventor to make every effort to cooperate. To the sense of virtue. 17 200921399 [Simple description of the drawings] The first figure is a three-dimensional appearance of the present invention. The second figure is a block diagram of the present invention. The third figure is another block diagram of the present invention. The fourth figure is a flow chart of the steps of the present invention. The fifth drawing is a waveform diagram of a preferred embodiment of the present invention. The sixth figure is a schematic diagram of data sampling according to another embodiment of the present invention. The seventh figure is a waveform diagram of still another embodiment of the present invention. [Description of main component symbols] 1. Logic analyzer 1 1. Control circuit 12, memory 13, measuring component 2, computer 2 1, screen 2, software 2 21, memory unit 131, wire 13 2, jig 14, transmission Interface 2 2 3, decoding determination module 2 2 4, output interface 2 3, storage device 18 200921399 2 2 2, input interface 3, side to side

Claims (1)

200921399, the scope of the patent: 1 '-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The method of detecting the signal of Mao, the half shovel is, (1) the multi-step touch of the soft body, and the smuggling is . /, 丄 touch 1 force this to make the wrong trigger condition... (2) Logic analyzer or 敕 ...... White (four) edge and 疋, line start \ & f continue to be scaled, the software will enter the logic analyzer program; (3) when the software starts the logic analyzer program, it will form The signal is transmitted to the logic analyzer. _ er, 4) The logic analyzer receives the condition of the tth condition, and then the _ rabbit conditional slave is a single _ condition. 5) The logic analyzer measures the side object and will remember In the body, squatting and recognizing ^ Bing in the inch hunting, only the tank deposit called the test tribute meets the first-order trigger bar = ^ logic fine ship after _ dare to remember the capacity of the ship 'stop _ data, and memory _Check the μ material for transmission; 6) After the software receives the test data, judge; ... + money According to the multi-issue condition, the data corresponding to the trigger condition will be marked than the seven-eighth W; the software will be used to prepare the data, and the data will be uploaded to the computer and the waveform of each mark will be transmitted 20 200921399 ρ τ Shen Qing's method of multi-level triggering of software for single-stage logic analysis described in item i of the patent program, in which the trigger mode of the ^ can be changed after the software is started, and the money continues to change the Wei A-like function. The ability to trigger the software, such as the single-stage logic analyzer described in the patent application l_i, utilizes the soft surface _ 夕 阶 trigger method. After the logic analyzer sets the single-order trigger condition, the trigger can delay and trigger. The page and trigger count functions are turned off. 4. As claimed in the patent application, the single-stage logic analyzer _soft-in, and-order-trigger method described in the item i, wherein the logic analyzer can be further provided with a qualifier = energy, if the stator function is activated, The logic is divided into rhymes. The time is measured and the data is captured according to the setting of the dice function. 5. The single-stage logic analyzer described in item i of the patent scope utilizes a method of multi-level triggering of a software age, wherein the single-stage logic analyzer is provided with at least one measuring 7L piece and the measuring Tt piece is provided. The complex guide 6 capable of forming a complex quantity measuring channel, the single-stage logic analyzer described in the scope of the patent application, wherein the trigger condition can have any signal, rising edge, falling edge, High level, low level, any edge, trigger width time, waiting time and trigger interval. 7. A method for multi-level triggering by a single-stage logic analyzer according to item 6 of the patent application scope, The trigger width time is a range for setting the maximum value and the minimum value of the trigger width for each trigger level 200921399. 8. The method for multi-level triggering using a software for the single-order logic analyzer according to item 6 of the patent application scope 'The trigger interval is for each trigger stage: set the maximum and minimum values of the trigger interval to form a range. 9 9. As described in claim 1 The logic of the logic analyzer performs multi-level triggering, wherein when the logic analyzer performs signal detection on the asynchronous transmission interface, the position of the sampling point can be set in the multi-level trigger condition. The detailed description of the single-stage logic analyzer is a multi-level trigger method, wherein the logic analyzer can set the memory storage capacity, and after determining that the detection data meets the first-order trigger condition, and then in the memory After storing the data of the set memory storage capacity, the data is stopped. 1 1. The method of multi-level triggering of the single-stage logic analyzer described in item i of the patent scope, wherein the software includes memory The unit, the input interface, the decoding judgment module and the output interface are composed of the memory, the input interface and the function of the decoding judgment module, the trigger condition, the detection data, the waveform or other data, and the input The interface is for the user to set the logic analyzer and software function, trigger condition or other parameters, and the decoding mode, _ can detect the fresh element The multi-level trigger condition and the judging process of the mark, and the detected test data are decoded into a waveform' and the memory unit can output the waveform to the display screen 200921399 through the output interface. 12. As claimed in the first item of the patent scope The single-stage logic light eight-α knife analyzer uses a software to enter the logic analyzer and performs a five-line multi-step trigger method, wherein the software compares the data of the 捡na and then judges the data to meet the job conditions. Will send a signal to r 3, as described in the patent scope of the item! Single-order:: multi-level trigger method, shoot the tilt to the ^^ using the software into the = undecided data for multi-level trigger, conditions, Body 丄 = 'If there is still money to continue - stop the software after the completion of the :::: mark, and in the capital 23