201118951 六、發明說明： 【發明所屬之技術領域】 本發明侧於-種具金屬閘極之半導體結構與形成方法， 種具擴大開口之半導體結構以及其形成方法。 【先前技術】 隨著半導體製程之線寬不斷縮小.，半導體元件之尺寸 地朝微型化發展。在半導體產業中，由於多晶頻料= 熱性質，因此通常會使用多㈣材料來製作半導體科料 =構’特別是例如在金屬氧化物半導體電晶體之閘= =公另外，又由於在適當的佈植能量下’ 植製程的換質進入通道區域，2 == 又能夠承受高溫退火處理，以使 Γ3Γ形成自行對準的源極區域與沒極區域。相對 地，夕Ba矽閘極尚存在許多至今無法 、 以多晶彻與大多數金屬材料相比較，多晶:材 阻值的半導體材料，以致於具高阻値的多/呵電 作速率相對於金屬導、_低。為 I ^極之操 低操作速率，以多晶石夕材料作為門電阻與其相應之較 大量的魏金屬處理步驟，進而需要額外採用 目標4此，本發㈣祕錢難：期 述問題之重要作法。 ㈣-構乃成為解決上 201118951 然而’由於目前半導㈣程之線寬微小化至程 具金屬_之半導體結構的整合製程亦浮現出更多挑戰與^ 頸。請參照第！圖至第2圖，第i圖至第2圖為習知具金屬 半導體結構之形成方法示意圖。如第丨圖所示，首先，提供二半^ 體基板10。接著形成一閑極結構12於半導體基板1〇上 結構U包含虛置圖案化多晶则12a以及圖案化間極介電層 接績形成-輕摻騎極祕13於半導縣板ig上。錢於 結構12外卿賴位側壁子14與嫩子％。隨後形成—=區 域18a與-汲極區域18b。最後形成一層間介電質層17，並利用化 學磨(CMP)製程去除虛置圖案化多晶石夕層以上方之部份層 間介電質層17’使得曝露出來的虛置圖案化多晶硬層以如同設置 於偏位側壁子14以及圖案化閘極介電層12b所定義出的溝槽^中。 接著如第2圖所示，侧虛置圖案化多晶石夕層12a以曝露出溝 槽19，再依序直接沉積一功函數調整層21與一閘極導電層如於溝 槽19中，如此可透過閘極導電層2〇作為金屬閘極而與其它金屬内 連線電性相連接，以形成閘極電訊號之傳送路徑。不過，隨著未來 半導體，纟σ構之閘極結構12的溝槽19之寬高比（aSpect rati〇)之狹 乍限制，尤其是縮小到28奈米(nm)製程後，現行金屬閘極導電層的 /儿積方式’勢必無法提供良好的階梯覆蓋率（stepcoverage) ，而會 出現突懸（overhang)或孔洞（v〇id)等瑕疵，嚴重影響沉積閘極導 電層時之填洞品質。 201118951 有鑑於此，習知具金相極之半導體結構 沉積品質並不理想之缺點，以及日。地導電層存在 解決溝槽填洞時所產生的突懸或孔洞的問月題。長技“無法順利 【發明内容】 本發明之主要目㈣提供—種形成具金相極之半導體結 構以及形成方法’以改善上述習知之問題。 為達上述目的’本發賴供—種形成具金相極之半導體結構 之方法，且方法至少包含下列步驟。首先，提供—半導體基板。 接著形成至少結構於半導體基板上。然後，形成一側壁 子結構於閘極結構之關㈣。接續形成—層間介電質層。 接著’平坦化層間介電質層。然後，去除部份閉極犧牲層至一 初始银刻深度，形成—開口並曝露部份之侧壁子結構。再去除部 2之暴露的側壁子結構，以擴大開口。隨後，、經由該開口以完 全去除閑極犧牲層。最後，形成―閘極導電層，填滿該開口。 為達上述目的，本發明提供—種具金屬閑極 且 金屬開極之半導體結構至少包含—半導體基板、—閘極結構、二 其側J子mu壁子。其中1極結觀置於半導體 土板上，且閘極結構至少包含—閘極介電層與1極導電層，而 閑極導電層包含一第一金屬以及一第二金屬，且第二金屬覆蓋 201118951 於第一金屬之上◦此外，第一側壁子設置於第—金屬周圍側 壁，且第二金屬覆蓋第一側壁子之上方。以及一第二側壁 子’設置於第一側壁子周圍側壁周圍。 本發明具金屬閘極之半導體結構與形成方法，其主要係 利用部份去除第-側壁子後所產生之擴大開σ，再經由此擴 大開口接續完成閘極導電層之製作。本發明利用具金屬問極之 半，體結構與形成方法可有效改善f知製作金屬閘極時之階梯 覆蓋率不佳的問題’藉以使閘極結構内壁連續且均勻地覆策問極 導電層，並—併解決溝槽出現突懸或孔洞的問題。 【實施方式】 =第3圖至第9圖，第3圖至第9圖為本發明具彳 ^間極之半導體結構之形成方法示意圖。如第3圖所示，, 半導體基板3°，且半導體基板3G之材質可選用i ΓΓ導則、物或鍺等材細基底。接著 上依序形成一介電層”與-多晶_201118951 VI. Description of the Invention: [Technical Field] The present invention is directed to a semiconductor structure and a method for forming a metal gate, a semiconductor structure having an enlarged opening, and a method of forming the same. [Prior Art] As the line width of semiconductor processes continues to shrink, the size of semiconductor components has progressed toward miniaturization. In the semiconductor industry, due to the polycrystalline material = thermal properties, it is common to use multiple (four) materials to make semiconductor materials = structure, especially for example, in the gate of metal oxide semiconductor transistors = = public, and because of the appropriate Under the implant energy, the process of the planting process enters the channel area, and 2 == can withstand the high temperature annealing process, so that the Γ3Γ forms a self-aligned source region and a non-polar region. In contrast, there are still many semiconductor materials that have not been able to be compared with most metal materials, polycrystalline materials, and so on, so that the rate of high-resistance is relatively high. In the metal guide, _ low. For the low operation rate of I ^ pole, the polycrystalline stone material as the gate resistance and its corresponding larger amount of Wei metal processing steps, and then need to additionally use the target 4, this (4) secret money is difficult: the importance of the problem practice. (4) - The structure has become a solution to the above-mentioned 201118951. However, due to the current semi-conductor (four) process, the line width is miniaturized to the semiconductor structure of the process metal, and the integration process of the semiconductor structure also presents more challenges and necks. Please refer to the first! 2 to 2 are schematic views showing a conventional method of forming a metal semiconductor structure. As shown in the figure, first, a two-half body substrate 10 is provided. Then, a dummy structure 12 is formed on the semiconductor substrate 1 . The structure U includes a dummy patterned polycrystalline layer 12a and a patterned inter-electrode dielectric layer is formed. The light-doped polar layer 13 is formed on the semi-conducting plate ig. Money in the structure of 12 Wai Qing Lai side wall 14 with tenderness%. Then, the -= region 18a and the - drain region 18b are formed. Finally, an interlayer dielectric layer 17 is formed, and the dummy patterned polycrystalline layer is removed by a chemical etching (CMP) process to remove the exposed dummy patterned polycrystalline layer from the upper interlayer dielectric layer 17'. The hard layer is as defined in the trenches defined by the offset sidewalls 14 and the patterned gate dielectric layer 12b. Then, as shown in FIG. 2, the polysilicon layer 12a is patterned by the side dummy to expose the trench 19, and a work function adjusting layer 21 and a gate conductive layer are directly deposited in the trench 19, respectively. Thus, the gate conductive layer 2 is electrically connected to other metal interconnects through the gate conductive layer 2 to form a gate transmission path. However, with the future semiconductor, the aspect ratio (aSpect rati〇) of the trench 19 of the gate structure 12 of the 纟σ structure is limited, especially after the process is reduced to 28 nm (nm), the current metal gate The conductivity pattern of the conductive layer is bound to provide a good step coverage, and there will be overhangs or voids (v〇id), which seriously affect the quality of the filling hole when depositing the gate conductive layer. . 201118951 In view of this, it is a shortcoming that the deposition quality of semiconductor structures with gold phase is not ideal, and the day. The ground conductive layer has a problem of solving the overhang or hole generated when the trench is filled. The long-term technology "cannot be smooth" [invention] The main object (4) of the present invention provides a method for forming a semiconductor structure with a gold phase and a method for forming the above-mentioned problems to improve the above-mentioned problems. A method of metallographic semiconductor structure, and the method comprises at least the following steps. First, a semiconductor substrate is provided. Then, at least a structure is formed on the semiconductor substrate. Then, a sidewall substructure is formed on the gate structure (4). Interlayer dielectric layer. Then 'flattening the interlayer dielectric layer. Then, removing part of the closed-pole sacrificial layer to an initial silver engraving depth, forming an opening and exposing a portion of the sidewall substructure. Exposed sidewall substructure to expand the opening. Then, through the opening to completely remove the sacrificial sacrificial layer. Finally, a gate conductive layer is formed to fill the opening. To achieve the above object, the present invention provides a metal The semiconductor structure of the idle pole and the metal opening includes at least a semiconductor substrate, a gate structure, and a side wall of the J submu. On the conductor earth plate, and the gate structure comprises at least a gate dielectric layer and a first conductive layer, and the idle electrode conductive layer comprises a first metal and a second metal, and the second metal covers 201118951 in the first metal In addition, the first side wall is disposed on the side wall of the first metal, and the second metal covers the upper side of the first side wall, and a second side wall is disposed around the side wall around the first side wall. The semiconductor structure and the formation method of the pole mainly utilize the enlarged opening σ generated after the partial removal of the first sidewall, and then the fabrication of the gate conductive layer is completed through the enlarged opening. The invention utilizes the half of the metal pole The body structure and the formation method can effectively improve the problem that the step coverage of the metal gate is not good, so that the inner wall of the gate structure continuously and uniformly covers the pole conductive layer, and the groove is formed. The problem of the suspension or the hole. [Embodiment] = Fig. 3 to Fig. 9, Fig. 3 to Fig. 9 are schematic views showing the formation method of the semiconductor structure having the interelectrode of the present invention. As shown in Fig. 3,Conductor substrate 3 °, and the semiconductor material of the substrate can be selected 3G i ΓΓ other guidelines, or germanium thin sheet on the substrate followed by sequentially forming a dielectric layer "and the - _ Polycrystalline
•4=ρΙ之材料可林具有任何I :=^的_料所構成。接續於… 未二Γ示)’並利用-圖案化光阻層。 未不）當作4罩進行一圖案化轉 遮罩層36,而圖案化遮罩層36則|=，以絲成一圖& 化石夕（SiN)、碳切（sic)或 〜氧Μ (崎)、丨 乳化矽（SiON)等所構成 201118951 如第4圖所示，再利用圖案化遮罩層妬將介電層以與 多晶矽層34蝕刻形成閘極介電層32a與虛置圖案化多晶石夕、 層，而得到一閘極結構38。値得留意，在本實施例中，㈤由於 虛置圖案化多晶碎層並#本實關之最㈣極電極，故虛置 圖案化多晶矽層係亦可稱為一閘極犧牲層3如，而可為^他 财高溫材㈣換之。隨後去除圖案化解層36。在本實施例 中，形成閘極結構38之問極介電層32a之材質可選用包含氧 化物、氧化石夕、氮氧化石夕（Si0N)、氮化石夕（秘4)、氧化叙（小 結（A1)、氧化給（Hf〇）、含氮氧化物、氮化氧化物、含給氧錄、 含鈕氧化物、含絲錄、高介電倾(κχκ>5)·等，或上述材 料之組合，而並未加以侷限’且閘極介電層仏較佳需滿足低閉 極漏電之材料特性。 在形成閘極結構38之後，隨即進行所需之摻雜製程。 例如遥擇性進行一淺摻雜離子佈植製程，將N型或p型摻質 進行植入半導體基板3〇 _，以於閘極結構38相對的半導體 基板30中各形成一輕摻雜源極區域4〇a與汲極區域牝b。隨 1依序形成一第一側壁子42於閘極結構38之側壁周圍以及 一第二側壁子43於第-侧壁子42之側壁周圍。在本實施例 中，第-側壁子42可為單-材料層，或包含複數個子結構層，較 佳為矽氧層或氣化石夕層交替排列形成，例如是由石夕氧層、氮矽 層或石夕氧層（ΟΝΟ)來構成子結構層心、子結構層伽二及子結 201118951 構層42c專二層結構，但並未加以偏限，而各子結構層之厚度實質 上可分別介於1奈米至5奈米之間。 在完成第一側壁子42與第二側壁子43後，緊接著進行 另一重摻雜離子佈植製程，將N型或P型摻質進行植入半導 體基板3〇，以於第二側壁子43周圍各形成一源極區域44a 與一汲極區域44b ,需注意的是，上述源極區域4牦與汲極 •區,:4b的製程亦可再整合選擇性磊晶成長等應變矽製程， 以提同通道區域之载子的遷移率，且相關製程的進行順序可 依製^求改變調整，在此不多贅述。隨後進行-快速升溫 退火製程’利用9〇〇至1〇5〇。〇的高溫來活化源極區域4如與 及極區域44b内的掺雜質，並同時修補各離子佈植製程中為 才貝之半導體基板30.表面的晶格結構。 又 接續形成-層間介電質層46’覆蓋於閘極結構％、源 極區域他、及極區域视、第一側壁子42以及第二側壁子4: ^其中相介電質層46可包含氮化物、氧化物、碳化物、 低N電係數材料之一或多者。 檨m士圖所示，再進行一平坦化步驟，用以去除閘極為 止，之邹份層間介電質層46’直至曝露閘極犧牲層34a# ’且使曝”之閘極犧牲層施實質上 46之表面，发由、丁 曰”丨电貝赝 '、千平坦化步驟可使用例如化學機械研磨製程 201118951 (Chemical Mechanical Polishing/Planarization，CMP)、乾式蝕刻製浐 或濕式蝕刻製程或其組合。 接著進行將曝露之閘極犧牲層34a去除之步驟，需注咅， 閘極犧牲層34a之去除可採用乾式蝕刻製程或濕式蝕刻製程 或其組合。在本實施例中，閘極犧牲層34a之去除較佳乃採取二 階段钮刻製程來進行去除’如第5圖所示，第一階段乃先去除部 份閘極犧牲層34a至一初姶蝕刻深度d，以於閘極結構％中形 成一第一開口 52並曝露部份之第一侧壁子42,需注意的是，初始 蝕刻深度d較佳至少大於原本閘極犧牲層34a高度的二分之一以 上。舉例來說，第一階段可採取濕式蝕刻製程來進行去除，例如利 用氨水（ammonium hydroxide, NH40H )或氫氧化四甲鍵 (Tetramethylammonium Hydroxide，TMAH)等餘刻溶液並配 合較佳時間參數以及溫度參數來去除由多晶矽所構成的部份閘 極犧牲層34a，以使原本閘極結構38形成一第—開口 52，但 蝕刻溶液選用並不加以限制，而可為任何適當之蝕刻液。惟需注 意的是，在本實施例中，由於所選定的蝕刻溶液對於閘極犧牲 層34a與第一側壁子42具有較高蝕刻選擇比，因此僅去除 部份閘極犧牲層34a而保留第一側壁子42。 然後’如第6圖所示，於第二階段乃接著去除部份曝露於 第一開口 52之第一側壁子42，以擴大第一開口 &而形成一第二 開口 54。惟需注意的是，由於本實施例中之第一側壁子42 201118951 可由具有氧化層與氮化石夕層交錯排列之多層結構所組成，故去除部 伤曝路於第-開口 52之第—侧壁子42亦即可選擇性触刻具多 層結構之第一侧壁子4 2之至少一層以上結構，例如，移除 了氧化層以及-部份的氮化♦層，或者，於本發明另一實施 例中，也可以部份移除暴露於第一開口 52的第一側壁子42 至初始蝕刻深度d，將初始蝕刻深度d以上的第一側壁子42 完全移除。 ® 請參考第6圖，去除部份曝露於第一開口 52之第一側壁子 42可選擇性去除第一側壁子42之子結構層似、4%、^等，然 .而餘刻之子結構層數目並未加以侷限，且蝕刻各子結構層之深度可 依元件設計加以調整。在此需特別說明的是，舉例而言，若以選擇 性蝕刻具多層結構之第一側壁子42之第一子結構層42a 時’第一側壁子42之第一子結構層42a之蝕刻深度可定義 為第一蚀刻長度（圖未示），而第一儀刻長度需小於或等於 籲前述初始蝕刻深度d。同樣地，若以選擇性蝕刻第一側壁子42 之第二子結構層42b時，第一側壁子42之第二子結構層42b 之蝕刻深度定義為第二蝕刻長度（圖未示），而第二蝕刻長 度需小於或等於前述第一蝕刻長度。同理，若以選擇性蝕刻 具多層結構之第一側壁子42之複數層結構時將可依此類 推，而不在此贅述。當然’若初始蝕刻深度d、第一蝕刻長 度、第二蝕刻長度等全部相同時，將會移除第一側壁子42 之部份直至初始蝕刻深度d。藉由上述非等長或等長蝕刻各子• The material of 4=ρΙ can be composed of any material with I :=^. Continued from... not shown) and used - patterned photoresist layer. No, the pattern is turned into a mask layer 36 as a 4 mask, and the patterned mask layer 36 is |=, and is patterned into a picture & a SiN, a carbon sic or a oxime ( As shown in FIG. 4, the dielectric layer is etched with the polysilicon layer 34 to form the gate dielectric layer 32a and the dummy pattern is formed as shown in FIG. The polycrystalline stone is tiered and layered to obtain a gate structure 38. It should be noted that in the present embodiment, (5) the dummy patterned polycrystalline germanium layer may also be referred to as a gate sacrificial layer 3 due to the dummy patterning of the polycrystalline layer and the most (four) pole electrode of the present embodiment. , but can be replaced by ^Tai Cai high temperature material (four). The patterned solution layer 36 is subsequently removed. In this embodiment, the material of the gate dielectric layer 32a forming the gate structure 38 may be selected from the group consisting of oxide, oxidized stone, yttrium oxynitride (Si0N), nitrided stone (secret 4), and oxidized (A1), oxidizing (Hf〇), nitrogen oxides, oxynitride oxides, oxygen-containing oxides, button-containing oxides, silk-containing recordings, high dielectric tilting (κχκ>5), etc., or the like The combination is not limited and the gate dielectric layer preferably needs to meet the material characteristics of the low closed drain. After the gate structure 38 is formed, the desired doping process is performed. A shallow doping ion implantation process is performed to implant an N-type or p-type dopant into the semiconductor substrate 3?, to form a lightly doped source region 4a in the semiconductor substrate 30 opposite to the gate structure 38. And the drain region 牝b. A first sidewall 42 is sequentially formed around the sidewall of the gate structure 38 and a second sidewall 43 is around the sidewall of the sidewall spacer 42. In this embodiment, The first side wall 42 may be a single-material layer or comprise a plurality of sub-structure layers, preferably a silicon oxide layer or a gas fossil The layers are alternately arranged, for example, a Sihu oxygen layer, a Niobium oxide layer or a Xiyang oxygen layer (ΟΝΟ) to form a substructure layer core, a substructure layer Gamma and a substructure 201118951 layer 42c special layer structure, but Without limitation, the thickness of each sub-structure layer may be substantially between 1 nm and 5 nm. After completing the first side wall 42 and the second side wall 43, another heavy doping is performed. In the ion implantation process, the N-type or P-type dopant is implanted into the semiconductor substrate 3 to form a source region 44a and a drain region 44b around the second sidewall 43 respectively. It should be noted that the source is In the polar region 4牦 and the bungee region, the 4b process can also be integrated with the selective epitaxial growth strainer process to increase the mobility of the carrier in the channel region, and the order of the related processes can be determined. The change adjustment is not described here. Then, the rapid temperature annealing process is performed using 9 〇〇 to 1 〇 5 〇. The high temperature of 〇 is used to activate the dopant in the source region 4 such as the sum region 44b, and simultaneously Repairing the crystal lattice of the surface of the semiconductor substrate 30 in each ion implantation process The structure is further formed - the interlayer dielectric layer 46' covers the gate structure %, the source region, and the polar region, the first sidewall 42 and the second sidewall 4: ^ wherein the dielectric layer 46 It may include one or more of nitride, oxide, carbide, and low-N electrical-coefficient material. As shown in the diagram, a planarization step is performed to remove the gate electrode. The layer 46' is exposed to the gate sacrificial layer 34a#' and the exposed sacrificial layer of the sacrificial layer is applied to the surface of the substantially 46, and the singularity of the sputum is used. For example, chemical mechanical polishing can be used. Process 201118951 (Chemical Mechanical Polishing/Planarization, CMP), dry etching or wet etching process or a combination thereof. Next, the step of removing the exposed gate sacrificial layer 34a is performed. Note that the gate sacrificial layer 34a may be removed by a dry etching process or a wet etching process or a combination thereof. In this embodiment, the removal of the gate sacrificial layer 34a is preferably performed by a two-stage button engraving process. As shown in FIG. 5, the first stage removes a portion of the gate sacrificial layer 34a to a preliminary etching. The depth d is such that a first opening 52 is formed in the gate structure % and a portion of the first sidewall portion 42 is exposed. It should be noted that the initial etching depth d is preferably at least greater than the height of the original gate sacrificial layer 34a. More than one. For example, the first stage can be removed by a wet etching process, such as using ammonia hydroxide (NH40H) or Tetramethylammonium Hydroxide (TMAH), etc., with better time parameters and temperature. The parameter is used to remove a portion of the gate sacrificial layer 34a composed of polysilicon so that the original gate structure 38 forms a first opening 52, but the etching solution is selected and is not limited, and may be any suitable etching liquid. It should be noted that, in this embodiment, since the selected etching solution has a higher etching selectivity ratio for the gate sacrificial layer 34a and the first sidewall sub-42, only a portion of the gate sacrificial layer 34a is removed and the first portion is retained. A side wall 42. Then, as shown in Fig. 6, in the second stage, a portion of the first side wall 42 exposed to the first opening 52 is removed to enlarge the first opening & a second opening 54 is formed. It should be noted that, since the first sidewall member 42 201118951 in this embodiment may be composed of a multilayer structure having a staggered arrangement of an oxide layer and a nitride layer, the removal portion is exposed on the first side of the first opening 52. The wall 42 can also selectively etch at least one or more layers of the first sidewall sub-layer 4 2 having a multi-layer structure, for example, removing the oxide layer and the - part of the nitride layer, or In one embodiment, the first sidewall 42 exposed to the first opening 52 may be partially removed to an initial etch depth d to completely remove the first sidewall 42 above the initial etch depth d. ® Please refer to FIG. 6 to remove a portion of the first sidewall 42 exposed to the first opening 52 to selectively remove the sub-structure layer of the first sidewall 42, 4%, ^, etc., and the remaining sub-structure layer The number is not limited, and the depth of etching each sub-structure layer can be adjusted according to the component design. Specifically, here, for example, if the first sub-structure layer 42a of the first sidewall sub-layer 42 having the multilayer structure is selectively etched, the etching depth of the first sub-structure layer 42a of the first sidewall sub-42 is etched. It may be defined as a first etched length (not shown), and the first sizing length needs to be less than or equal to the aforementioned initial etch depth d. Similarly, if the second sub-structure layer 42b of the first sidewall sub-42 is selectively etched, the etching depth of the second sub-structure layer 42b of the first sidewall sub-42 is defined as a second etched length (not shown), and The second etch length needs to be less than or equal to the aforementioned first etch length. Similarly, if a plurality of layers of the first side wall member 42 having a multi-layered structure are selectively etched, the same can be said, and the details are not described herein. Of course, if the initial etching depth d, the first etching length, the second etching length, and the like are all the same, a portion of the first side wall portion 42 will be removed up to the initial etching depth d. Etching each of the above by non-equal length or equal length
11 201118951 結構層以產生擴大開口結構 質。 以利後續形成$電金屬層 夕 口 口口 二第7圖所示，第7 _示接續第5圖之另—較佳變化實 ，例中’值棚注’去除部份曝露於第—. 仙擴大第-開口 54而形成一第二開σ54第^^ 二階段_，除了上述__般_或_的方式外亦=+ 送擇性替換4增加-子絲（iGnb。咖d_t)=， 例如在第二階段侧時，使祕刻步驟並加上—物理性離子躲牛 驟，或者直接使用物理性離子轟擊步驟來取代一般的_步驟，二 對子結構層42a、42b、42c同時進行-非等向性姓刻步驟，進而形 成-斜面結構，藉此使第二開口 54圓角化而更為向外擴大。 如第8圖所示，接著，乃採取濕式蝕刻製程並經由第二開口 ％ 以元全去除剩餘之部份閘極犧牲層34a，形成一第三開口⑽，在 空間關係上，第二開口 54之寬度實質上大於第—開口 52與第三開 口 80之寬度。需注意的是，在形成第三開口 時會同時暴露 出設置於第三開口 80底部的閘極介電層32a。緊接著，利用 有機金屬化學氣相沈積法（metal organic chemical vapor deposition, MOCVD)、分子束蠢晶法（Molecular Beam Epitaxial)、化學氣相沈 積（Chemical Vapor Deposition )製程或物理氣相沉積（Physical Vap〇r DqDosition)製程等來加以形成一功函數調整層82覆蓋於閘極介電 層32a與第一側壁子42表面。在本實施例中，功函數調整層82 12 201118951 5又置之目的乃為了使半導體之閘極電極與閘極介電層32a間 能階狀態接續以滿足功函數（work function )匹配調整之用， 而此功函數調整層82可依據半導體的型態可由n型功函數調 整層82所構成或由p型功函數調整層82所構成。舉例來說， 若後讀欲製備的半導體為N型電晶體’功函數調整層可選擇 採用例如是氮化鈦（TiN)、碳化鈕（TaC)、氮化鈕（TaN)、 氮化石夕组（TaSiN)、鋁（A1)、钽（Ta)、鈦（Ti)、銘化鈦 鲁 （TiAl)、氮化鋁鈦(TiAIN)或铪（Hf)等材料，或其組合等N 型金屬所構成。然而，若所製備的電晶體為P型電晶體，功 函數調整層可選擇採用例如是氮化鈦（TiN)、鎢、氮化 鶴（WN)、鉑（Pt)、鎳（Ni)、釕（Ru)、碳氮化钽（TaCN) 或碳氮氧化鈕（TaCNO)等材料所構成。在本實施例中，功 函數調整層較佳係採用超薄的氮化鈦（TiN)，且可配合選擇 性離子佈植等的處理，以同時分別滿足N型電晶體或p型電 晶體之功函數匹配需求，且氮化鈦層之厚度實質上介於5奈 米至15奈米之間。又，超薄的氮化鈦（TiN)較佳係利用原 子層沈積法（atomic layerdeposition，ALD)來製作，藉以控制鍍膜 厚度的精確性，以達到高品質階梯覆蓋率及極佳的厚度均勻性。補 充說明的是，本發明氮化鈦層（TiN)除採用單層結構外，亦 可依半導體結構設計而具有數種變化實施例，可再細分為一層、二 層或多層結構。舉例來說，氮化鈦層可以為Ti/TiN/Ti三層堆爲結 構，亦可為而兩層之TiNTi/TiN之兩層堆疊結構，堆疊方式可以排 列組合而未加以揭限。11 201118951 Structural layer to create an enlarged opening structure. Eli followed by the formation of the electric metal layer 夕口口口2 shown in Figure 7, the seventh _ shows the continuation of Figure 5, the other is better, in the case of the 'value shed' removed part of the exposure. The fairy enlarges the opening-opening 54 to form a second opening σ54, the second stage _, in addition to the above-mentioned __like _ or _ mode, also = + alternative replacement 4 - sub-filament (iGnb. coffee d_t) = For example, on the second stage side, the secret step is added with a physical ion doping step, or the physical ion bombardment step is used directly instead of the general step, and the two pairs of substructure layers 42a, 42b, 42c are simultaneously A non-isotropic step of engraving is performed to form a beveled structure whereby the second opening 54 is rounded to expand outward. As shown in FIG. 8, the wet etching process is followed by removing the remaining portion of the gate sacrificial layer 34a via the second opening % to form a third opening (10), in a spatial relationship, the second opening The width of 54 is substantially greater than the width of the first opening 52 and the third opening 80. It should be noted that the gate dielectric layer 32a disposed at the bottom of the third opening 80 is simultaneously exposed when the third opening is formed. Then, using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (Molecular Beam Epitaxial), chemical vapor deposition (Chemical Vapor Deposition) process or physical vapor deposition (Physical Vap) A work function adjustment layer 82 is formed over the surface of the gate dielectric layer 32a and the first sidewall member 42 by a process such as Dr DqDosition. In the present embodiment, the work function adjustment layer 82 12 2011 18951 5 is again provided for the purpose of aligning the energy level between the gate electrode of the semiconductor and the gate dielectric layer 32a to meet the work function matching adjustment. The work function adjustment layer 82 may be formed by the n-type work function adjustment layer 82 or by the p-type work function adjustment layer 82 depending on the type of the semiconductor. For example, if the semiconductor to be prepared is a N-type transistor 'work function adjustment layer, for example, titanium nitride (TiN), carbonization button (TaC), nitride button (TaN), and nitride nitride group may be selected. N-type metal such as (TaSiN), aluminum (A1), tantalum (Ta), titanium (Ti), indium titanium (TiAl), titanium nitride (TiAIN) or hafnium (Hf), or a combination thereof Composition. However, if the prepared transistor is a P-type transistor, the work function adjusting layer may be selected, for example, titanium nitride (TiN), tungsten, nitrided (WN), platinum (Pt), nickel (Ni), tantalum. (Ru), tantalum carbonitride (TaCN) or carbon oxynitride (TaCNO) materials. In this embodiment, the work function adjusting layer is preferably made of ultra-thin titanium nitride (TiN), and can be combined with selective ion implantation to simultaneously satisfy the N-type transistor or the p-type transistor. The work function matches the requirements, and the thickness of the titanium nitride layer is substantially between 5 nm and 15 nm. Moreover, ultra-thin titanium nitride (TiN) is preferably fabricated by atomic layer deposition (ALD) to control the accuracy of the coating thickness to achieve high quality step coverage and excellent thickness uniformity. . In addition, the titanium nitride layer (TiN) of the present invention may have several variations of the semiconductor structure design in addition to the single layer structure, and may be further subdivided into one, two or more layers. For example, the titanium nitride layer may be a Ti/TiN/Ti three-layer stack structure, or a two-layer TiNTi/TiN two-layer stacked structure, and the stacking manner may be arranged in combination without being limited.
13 201118951 如第9圖所示，接著，形成一閘極導電層90填滿第三開口 80以及第一開口 54。在本實施例中’閘極導電層90較佳係採 用铭（A1)金屬’但亦可採用由低電阻材料例如是鶴（％ )、敎 铭合金（TiAl)或始鶴磧化物（c〇bait tungSten ph〇Sphide CoWP)所構成。隨後，可選擇性採用另一平坦化製程以去除部份 覆蓋於層間介電質層46上之閘極導電層9〇與功函數調整層82，而 使處理後之閘極導電層9〇實質上切齊於層間介電質層妬之表面， . 以元成具金屬閘極之半導體結構94。 由於第9圖鱗示本發明具金屬閘極之半導體結構之形 方法之最終完成圖’故第9圖亦可作為本發明具金屬_ / 例示意圖。如第9圖所示，本發明具金屬閉: 之+導體、Μ冓包含-半導體基板3G_結構92、 壁子42、—第二·子43以及—功函數調整層82。其一中1 閘極結構92，設置於半導體基板3()上，且閘極結構％至少包人 閘極介電層323與-閘極導電層9〇,而第一側壁子勺: 數個子結構層，而各子結之厚度實f上介於丨奈米至$ 間。_導電層90包含一第一金屬部份9〇a以及^^ 部份幾，且第二金屬部份90b覆蓋於第一金屬部份 上:惟需留意的是，在本實施例中，—功函數調整層8 覆盍設置於第一側壁子42與閘極介電層％上，且 _介電層32a以及第-金屬部份9Ga之間，而閘極導;層^ 201118951 乃先覆蓋於功函數調整層82之上。關於本發明且 之半導體結構材料選用上，半導體基板3〇之材質包=(=、 石夕錯⑽）、娜鳩晶錯。又，閘極介電層仏之材料包 錄化物、祕梦、氮氧切（Si⑽）、氮切（秘小氧化如 (Ta2〇5)、乳化銘（Al2〇5)、氧化給（励）、含氮氧化物、含給氧 化物、含组氧化物、含魄化物或高介電常數（Μ)材料等，或 上述材料之組合。在本實施例中，功函數調整層幻包含Ν型功 函數金屬材料或Ρ型功函數金屬材料，而功函數調整層幻設 置之目的乃為了使半導體之閘極導電層9〇與間極介電層仏 間月bP白接續狀態以滿^功函數（WQrkftj⑽㈣匹配調整之用。 在功函數調整層82之材料選用方面，舉例來說，N裂功函數 材料包含氮化鈦（TiN)、碳化鈕（TaC)、氮化组（倾）、 氮化石夕纽（TaSiN)、銘（A1)、组（Ta)、鈦⑺）、銘化鈦(TiAi)、 氮化紹鈦(TiAIN)或铪（Hf)等。舉例來說，p型功函數金屬 材料包含氮化鈦（TiN)、鎢（w)、氮化鎢（WN)、鉑（扒）、 錄（Ni)、釘（RU)、碳氮化组（TaCN)或碳氮氧化组（TaCN〇) 等。値得注意，功函數調整層82較佳係為一氮化鈦層，且氮化 鈦層之厚度實質上介於5奈米至15奈米之間。在半導體結 構空間分佈方面，第一側壁子42設置於第一金屬部份9〇a 之周圍側壁，且位於第二金屬部份9〇b之下方。又，第二側 壁子43，設置於第二金屬部份9〇b與第一側壁子42之周圍 侧壁。請再參考第1〇圖，第1〇圖為本發明具金屬閘極之半導體 結構之另一較佳實施例示意圖。第1〇圖與第9圖不同之處僅在於第 S1 15 201118951 10圖之第-側壁子42鄰近閘極導電層90之側壁具有斜面結構， 功函數調整層82係延第，壁子42進行覆蓋，而第—金屬部 份90a係延第-側壁子π設置，以及第二金屬部份_覆蓋於 第一金屬部份90a與第一側壁子42上，故在本實施例中，第一 側壁子42提供-向外擴大開口以容納閘極導電層Μ。此外，本實 施例之相同元件部份以於前述第9圖繪相及說明，在此不多賛述。 综上所述 本發明具至屬閘極之半導體結構與形成方 法，其主要係利用去除部份第一側壁子後所產生之擴大開 口’再經由擴大開口接續完成閘極導電層之製作。本發明具金屬 閘極之半導體結構與職方法不僅解決了 f知具金屬閘極之半導 體結構之Μ極結構溝槽_之寬高嫌制，進而提供傳統沉積製程 尚無法達成之映階碰蓋率，以及克服習㈣極結構溝槽於塞 極導電層所出現突赋孔鱗贼，大幅改善形成閘極導電: 的品質。 曰π 以上所述僅為本發明之難實施例，凡依本發明申請專利 所做之均㈣化與修飾’皆闕本發明<涵蓋範圍。 【圖式簡單說明】 第1圖至第2圖為習知具金屬閘極之半導體結構之形成方法示 第3圖至第9圖為本發明具金屬閉極之半導體結構之形= 法示意圖。 β 16 201118951 Γ圖為本㈣具金屬難之轉體結構之—較佳實補示意圖。 10圖為本發明具金屬閘極之半導體結構之另—較佳實施例示意 圖。 【主要元件符號說明】 10 半導體基板 12a 13 16 18a 19 21 32 34 虛置圖案化多晶石夕層 輕摻雜汲極 側壁子 36 • 40a 42 42b 43 44b 52 源極區域 溝槽 功函數調整層 介電層 多晶碎層 圖案化遮罩層 源極區域 第一側壁子 子結構層 第二侧壁子 汲極區域 第一開口 .第三開口 12 閘極結構 12b 閘極介電層 14 偏位侧壁子 17 層間介電質層 18b 〉及極區域 20 閘極導電層 30 半導體基板 32a 閘極介電層 34a 閘極犧牲層 38 閘極結構 40b 汲極區域 42a 子結構層 42c 子結構層 44a 源極區域 46 層間介電質層 54 第二開口 82 功函數調整層 [s 17 80 201118951 90 閘極導電層 90a 90b 第二金屬部份 92 94 半導體結構 d 第一金屬部份 閘極結構 初始蝕刻深度 1813 201118951 As shown in FIG. 9, next, a gate conductive layer 90 is formed to fill the third opening 80 and the first opening 54. In the present embodiment, the gate conductive layer 90 is preferably made of the metal of the first type (A1), but may also be made of a low-resistance material such as a crane (%), a eucalyptus alloy (TiAl) or a samarium compound (c〇). Bait tungSten ph〇Sphide CoWP). Subsequently, another planarization process can be selectively employed to remove the gate conductive layer 9 and the work function adjustment layer 82 partially covering the interlayer dielectric layer 46, so that the processed gate conductive layer 9 is substantially The upper surface is tangent to the surface of the interlayer dielectric layer, and the semiconductor structure 94 having a metal gate is formed. Since the ninth scale shows the final completion of the method for forming a semiconductor structure having a metal gate of the present invention, the ninth diagram can also be used as a schematic diagram of the metal of the present invention. As shown in Fig. 9, the present invention has a metal-closed + conductor, and includes a semiconductor substrate 3G_structure 92, a wall 42, a second sub-43, and a work function adjusting layer 82. The first gate structure 92 is disposed on the semiconductor substrate 3 (), and the gate structure % includes at least a gate dielectric layer 323 and a gate conductive layer 9 〇, and the first sidewall sub-spoon: several The structural layer, and the thickness of each sub-junction is between 丨 nanometer and $. The conductive layer 90 includes a first metal portion 9a and a portion, and the second metal portion 90b covers the first metal portion: it should be noted that, in this embodiment, The work function adjusting layer 8 is disposed on the first sidewall 42 and the gate dielectric layer %, and between the dielectric layer 32a and the first metal portion 9Ga, and the gate is conductive; the layer ^ 201118951 is first covered Above the work function adjustment layer 82. Regarding the semiconductor structural material of the present invention, the material of the semiconductor substrate 3 = (=, Shi Xi wrong (10)), Na Nao crystal. In addition, the material of the gate dielectric layer is recorded, secret dream, oxynitrid (Si(10)), nitrogen cut (small oxidation such as (Ta2〇5), emulsified (Al2〇5), oxidation (excitation) , a nitrogen-containing oxide, an oxide-containing oxide, a group-containing oxide, a telluride-containing or a high dielectric constant (Μ) material, or the like, or a combination of the above materials. In this embodiment, the work function adjusting layer is illusively contained. The work function metal material or the 功 type work function metal material, and the purpose of the work function adjustment layer phantom setting is to make the semiconductor gate conductive layer 9 〇 and the interpolar dielectric layer 仏 月 b b white continuous state with a full work function ( WQrkftj (10) (4) matching adjustment. In the material selection of the work function adjustment layer 82, for example, the N-crack function material includes titanium nitride (TiN), carbonization button (TaC), nitride group (dip), and nitrite New Zealand (TaSiN), Ming (A1), Group (Ta), Titanium (7), Indium Titanium (TiAi), Titanium or Niobium (Hf), etc. For example, p-type work function metal material Containing titanium nitride (TiN), tungsten (w), tungsten nitride (WN), platinum (扒), Ni (Ni), nail (RU), carbonitriding group (T aCN) or a carbonitride group (TaCN〇), etc. It is noted that the work function adjusting layer 82 is preferably a titanium nitride layer, and the thickness of the titanium nitride layer is substantially between 5 nm and 15 nm. In terms of spatial distribution of the semiconductor structure, the first sidewall 42 is disposed on the surrounding sidewall of the first metal portion 9〇a and below the second metal portion 9〇b. Further, the second sidewall 43 is The second metal portion 9〇b and the sidewall of the first sidewall 42 are disposed. Referring to FIG. 1 again, FIG. 1 is another preferred embodiment of the semiconductor structure having a metal gate according to the present invention. The first and second figures differ from the ninth figure only in that the side wall of the first side wall 42 of the S1 15 201118951 10 has a bevel structure adjacent to the sidewall of the gate conductive layer 90, and the work function adjusting layer 82 is extended. 42 is covered, and the first metal portion 90a is disposed on the first side wall π, and the second metal portion is overlaid on the first metal portion 90a and the first side wall portion 42, so in this embodiment, The first side wall 42 provides an outwardly enlarged opening to accommodate the gate conductive layer Μ. In addition, the same element of the embodiment The description and description of the above-mentioned Figure 9 are not mentioned here. In summary, the present invention has a semiconductor structure and a method for forming a gate, which mainly utilizes a part of the first sidewall after removing The generated enlarged opening 'further completes the fabrication of the gate conductive layer through the enlarged opening. The semiconductor structure and the working method with the metal gate of the present invention not only solves the trench structure of the semiconductor structure with the metal gate of the metal gate_ The wide and high suspicion, which provides the coverage rate of the conventional deposition process, and the overcoming hole thieves in the conductive layer of the (4) pole structure, greatly improved the formation of the gate conduction: quality.曰π The above description is only a difficult embodiment of the present invention, and all of the inventions and modifications made in accordance with the present invention are in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 2 are diagrams showing a method of forming a semiconductor structure having a metal gate. FIGS. 3 to 9 are schematic views of a semiconductor structure having a metal closed pole according to the present invention. β 16 201118951 The picture is based on (4) the structure of the metal with difficulty in rotating structure - the best practical compensation diagram. Figure 10 is a schematic view of another preferred embodiment of the semiconductor structure having a metal gate of the present invention. [Major component symbol description] 10 Semiconductor substrate 12a 13 16 18a 19 21 32 34 Virtual patterned polycrystalline lithi layer lightly doped drain sidewall 36 • 40a 42 42b 43 44b 52 Source region trench work function adjustment layer Dielectric layer polycrystalline layer patterned mask layer source region first sidewall sub-substructure layer second sidewall sub-drain region first opening. third opening 12 gate structure 12b gate dielectric layer 14 bias Sidewall 17 Interlayer dielectric layer 18b> and pole region 20 Gate conductive layer 30 Semiconductor substrate 32a Gate dielectric layer 34a Gate sacrificial layer 38 Gate structure 40b Gate region 42a Substructure layer 42c Substructure layer 44a Source region 46 interlayer dielectric layer 54 second opening 82 work function adjustment layer [s 17 80 201118951 90 gate conductive layer 90a 90b second metal portion 92 94 semiconductor structure d first metal portion gate structure initial etching Depth 18