TWI476838B - Semiconductor device haivng a metal gate and method of forming the same - Google Patents

Description

Semiconductor structure with metal gate and formation method

The present invention relates to a semiconductor structure and a method for forming a metal gate, and more particularly to a semiconductor structure having an enlarged opening and a method of forming the same.

As the line width of semiconductor processes continues to shrink, the size of semiconductor components continues to evolve toward miniaturization. In the semiconductor industry, since polycrystalline germanium materials have heat resistance properties, polycrystalline germanium materials are commonly used to fabricate conductor structures for semiconductor devices, particularly, for example, in the fabrication of gate electrodes for metal oxide semiconductor transistors. In addition, due to the proper implantation energy, the polysilicon as the gate electrode can block the dopant of the ion implantation process from entering the channel region, and in the high temperature environment, the polysilicon gate can withstand the high temperature annealing treatment to make the cloth. The implanted dopants form self-aligned source and drain regions. In contrast, polycrystalline germanium gates still have many shortcomings that have not been overcome so far. First, if a polycrystalline germanium material is compared to most metallic materials, the polycrystalline germanium material is a high resistance semiconductor material such that the operating rate of the high resistance polysilicon gate electrode is still low relative to the metal wiring. In order to compensate for the high resistance and its corresponding lower operating rate, the use of a polysilicon material as a gate electrode typically requires an additional large amount of deuterated metal processing steps, thereby increasing its operating rate to the desired target. Therefore, the formation of a semiconductor structure having a metal gate in the present invention is an important solution to the above problems.

However, due to the miniaturization of the line width of the semiconductor process to a certain extent, the integration process of the semiconductor structure with the metal gate also presents more challenges and bottlenecks. Please refer to FIG. 1 to FIG. 2 . FIG. 1 to FIG. 2 are schematic diagrams showing a method for forming a semiconductor structure having a metal gate. As shown in Fig. 1, first, a semiconductor substrate 10 is provided. A gate structure 12 is then formed on the semiconductor substrate 10, wherein the gate structure 12 includes a dummy patterned polysilicon layer 12a and a patterned gate dielectric layer 12b. A lightly doped source drain 13 is formed on the semiconductor substrate 10. A biasing sidewall 14 and a sidewall 16 are then formed on the periphery of the gate structure 12. A source region 18a and a drain region 18b are then formed. Finally, an interlayer dielectric layer 17 is formed, and a portion of the interlayer dielectric layer 17 above the dummy patterned polysilicon layer 12a is removed by a chemical mechanical polishing (CMP) process, so that the exposed dummy patterned polysilicon layer 12a is like It is disposed in the trench 19 defined by the offset sidewalls 14 and the patterned gate dielectric layer 12b.

Then, as shown in FIG. 2, the dummy patterned polysilicon layer 12a is etched to expose the trench 19, and a work function adjusting layer 21 and a gate conductive layer 20 are directly deposited in the trench 19, so as to be transparent. The gate conductive layer 20 is electrically connected to other metal interconnections as a metal gate to form a transmission path of the gate electrical signal. However, with the narrowness of the aspect ratio of the trench 19 of the gate structure 12 of the semiconductor structure in the future, especially after the reduction to the 28 nm process, the current metal gate conductive layer is deposited. It is bound to provide good step coverage, and there will be overhangs or voids, which seriously affect the quality of the hole filling when depositing the gate conductive layer.

In view of this, it is known that the gate conductive layer of the semiconductor structure having the metal gate has the disadvantage that the deposition quality is not ideal, and the problem of the overhang or the hole generated when the trench is filled in the hole cannot be solved smoothly according to the current process technology. .

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor structure having a metal gate and a method of forming the same to improve the above-mentioned problems.

To achieve the above object, the present invention provides a method of forming a semiconductor structure having a metal gate, and the method includes at least the following steps. First, a semiconductor substrate is provided. At least one gate structure is then formed on the semiconductor substrate. A sidewall substructure is then formed on the sidewalls surrounding the gate structure. An interlayer dielectric layer is formed. Next, the interlayer dielectric layer is planarized. Then, a portion of the gate sacrificial layer is removed to an initial etch depth to form an opening and expose portions of the sidewall substructure. A portion of the exposed sidewall substructure is then removed to enlarge the opening. Subsequently, the gate sacrificial layer is completely removed through the opening. Finally, a gate conductive layer is formed to fill the opening.

To achieve the above object, the present invention provides a semiconductor structure having a metal gate. The semiconductor structure having a metal gate includes at least a semiconductor substrate, a gate structure, a first sidewall and a second sidewall. The gate structure is disposed on the semiconductor substrate, and the gate structure comprises at least a gate dielectric layer and a gate conductive layer, and the gate conductive layer comprises a first metal and a second metal, and the second metal Covered on the first metal. In addition, the first sidewall is disposed on the sidewall surrounding the first metal, and the second metal covers the first sidewall. And a second sidewall disposed around the sidewall around the first sidewall.

The semiconductor structure and method for forming a metal gate of the present invention mainly utilizes an enlarged opening formed by partially removing the first sidewall, and then completing the fabrication of the gate conductive layer through the enlarged opening. The invention utilizes a semiconductor structure and a forming method with a metal gate to effectively improve the problem of poor step coverage when manufacturing a metal gate, so that the inner wall of the gate structure continuously and uniformly covers the gate conductive layer, and Together, the problem of overhanging or holes in the groove is solved.

Please refer to FIG. 3 to FIG. 9 . FIG. 3 to FIG. 9 are schematic diagrams showing a method for forming a semiconductor structure with a metal gate according to the present invention. As shown in FIG. 3, first, a semiconductor substrate 30 is provided, and the material of the semiconductor substrate 30 may be selected from a material including, for example, germanium, germanium (SiGe), epitaxial germanium or germanium. Then, a dielectric layer 32 and a polysilicon layer 34 are sequentially formed on the semiconductor substrate 30, and the material of the polysilicon layer 34 may be undoped or composed of polycrystalline germanium material having N+ or P+ dopants. . A masking material layer (not shown) is formed on the polysilicon layer 34, and a patterned photoresist layer (not shown) is used as a mask to perform a pattern transfer process to form a patterned mask. Layer 36, and patterned mask layer 36 may be composed of cerium oxide (SiO ₂ ), cerium nitride (SiN), tantalum carbide (SiC) or cerium oxynitride (SiON).

As shown in FIG. 4, the dielectric layer 32 and the polysilicon layer 34 are further etched using the patterned mask layer 36 to form a gate dielectric layer 32a and a dummy patterned polysilicon layer to obtain a gate structure 38. It should be noted that in the present embodiment, since the dummy patterned polysilicon layer is not the final gate electrode of the embodiment, the dummy patterned polysilicon layer may also be referred to as a gate sacrificial layer 34a, but may be other resistant. Replace with high temperature materials. The patterned mask layer 36 is then removed. In this embodiment, the material of the gate dielectric layer 32a forming the gate structure 38 may be selected from the group consisting of oxide, cerium oxide, cerium oxynitride (SiON), tantalum nitride (Si ₃ N ₄ ), and tantalum oxide (Ta). ₂ O ₅ ), aluminum (Al), hafnium oxide (HfO), nitrogen oxides, nitrided oxides, niobium-containing oxides, niobium-containing oxides, aluminum-containing oxides, high dielectric constant (K) (K >5) Materials, etc., or a combination of the above materials, without limitation, and the gate dielectric layer 32a preferably needs to satisfy the material characteristics of low gate leakage.

After the gate structure 38 is formed, the desired doping process is then performed. For example, a shallow doping ion implantation process is selectively performed, and an N-type or P-type dopant is implanted into the semiconductor substrate 30 to form a lightly doped source region in each of the semiconductor substrates 30 opposite to the gate structure 38. 40a and the bungee region 40b. Subsequently, a first sidewall 42 is formed around the sidewall of the gate structure 38 and a second sidewall 43 is formed around the sidewall of the first sidewall 42. In this embodiment, the first sidewalls 42 may be a single material layer or comprise a plurality of substructure layers, preferably an alternating layer of tantalum oxide or tantalum nitride, for example, a silicon oxide layer, a nitrogen layer or The oxide layer (ONO) constitutes a three-layer structure such as the substructure layer 42a, the substructure layer 42b, and the substructure layer 42c, but is not limited, and the thickness of each substructure layer may be substantially 1 nm to Between 5 nanometers.

After the first sidewall 42 and the second sidewall 43 are completed, another heavily doped ion implantation process is performed to implant the N-type or P-type dopant into the semiconductor substrate 30 so as to surround the second sidewall 43. Each of the source region 44a and the drain region 44b is formed. It should be noted that the process of the source region 44a and the drain region 44b may further integrate a strain-increasing process such as selective epitaxial growth to improve the channel region. The mobility of the carriers, and the order of the related processes can be adjusted according to the process requirements, and will not be repeated here. Subsequently, a rapid thermal annealing process is performed, and the high temperature of 900 to 1050 ° C is used to activate the doping in the source region 44a and the drain region 44b, and simultaneously repair the crystal on the surface of the damaged semiconductor substrate 30 in each ion implantation process. Grid structure.

An interlayer dielectric layer 46 is formed to cover the gate structure 38, the source region 44a, the drain region 44b, the first sidewall portion 42 and the second sidewall portion 43. The interlayer dielectric layer 46 may comprise nitrogen. One or more of a material, an oxide, a carbide, or a low dielectric constant material.

As shown in FIG. 5, a planarization step is performed to remove a portion of the interlayer dielectric layer 46 over the gate structure 38 until the gate sacrificial layer 34a is exposed, and the exposed sacrificial layer is exposed. 34a is substantially aligned with the surface of the interlayer dielectric layer 46, wherein the planarization step may use, for example, a Chemical Mechanical Polishing/Planarization (CMP), a dry etching process, or a wet etching process, or a combination thereof.

Next, the step of removing the exposed gate sacrificial layer 34a is performed. It should be noted that the gate sacrificial layer 34a may be removed by a dry etching process or a wet etching process or a combination thereof. In the present embodiment, the gate sacrificial layer 34a is preferably removed by a two-stage etching process. As shown in FIG. 5, the first stage removes a portion of the gate sacrificial layer 34a to an initial etching depth d. A first opening 52 is formed in the gate structure 38 and a portion of the first sidewall 42 is exposed. It should be noted that the initial etching depth d is preferably at least one-half greater than the height of the original gate sacrificial layer 34a. the above. For example, the first stage can be removed by a wet etching process, such as using an ammonia hydroxide (NH ₄ OH) or a tetramethylammonium Hydroxide (TMAH) etching solution in combination with better time parameters and The temperature parameter is used to remove a portion of the gate sacrificial layer 34a composed of polysilicon so that the original gate structure 38 forms a first opening 52. However, the etching solution is selected and is not limited, and may be any suitable etching liquid. It should be noted that, in this embodiment, since the selected etching solution has a higher etching selectivity ratio for the gate sacrificial layer 34a and the first sidewall sub-42, only a portion of the gate sacrificial layer 34a is removed and the first portion is retained. A side wall 42.

Then, as shown in FIG. 6, in the second stage, a portion of the first sidewall 42 exposed to the first opening 52 is removed to enlarge the first opening 52 to form a second opening 54. It should be noted that, since the first sidewall 42 in this embodiment may be composed of a multilayer structure having a staggered arrangement of an oxide layer and a tantalum nitride layer, the removed portion of the first sidewall 42 exposed to the first opening 52 is removed. Optionally, at least one or more structures of the first sidewalls 42 having a multi-layer structure may be selectively etched, for example, the oxide layer and a portion of the tantalum nitride layer are removed, or, in another embodiment of the present invention, The first sidewall 42 exposed to the first opening 52 may be partially removed to an initial etch depth d to completely remove the first sidewall 42 above the initial etch depth d.

Referring to FIG. 6, the first sidewalls 42 exposed to the first opening 52 are removed to selectively remove the sub-structure layers 42a, 42b, 42c and the like of the first sidewalls 42. However, the number of etched sub-structure layers is not limited. And the depth of etching each sub-structure layer can be adjusted according to the component design. Specifically, for example, if the first sub-structure layer 42a of the first sidewall 42 having a multi-layer structure is selectively etched, the etching depth of the first sub-structure layer 42a of the first sidewall 42 is etched. It may be defined as a first etch length (not shown), and the first etch length needs to be less than or equal to the aforementioned initial etch depth d. Similarly, if the second sub-structure layer 42b of the first sidewall 42 is selectively etched, the etching depth of the second sub-structure 42b of the first sidewall 42 is defined as a second etched length (not shown), and The second etch length needs to be less than or equal to the aforementioned first etch length. Similarly, if a plurality of layers of the first side wall member 42 having a multi-layer structure are selectively etched, the same can be omitted, and will not be described herein. Of course, if the initial etching depth d, the first etching length, the second etching length, and the like are all the same, a portion of the first sidewall portion 42 will be removed up to the initial etching depth d. Each of the substructure layers is etched by the non-equal length or the same length to create an enlarged opening structure to facilitate the subsequent formation of the quality of the conductive metal layer.

As shown in FIG. 7, FIG. 7 illustrates another preferred embodiment of the continuation of FIG. 5, and it is worth noting that the first side wall 42 exposed in the first opening 54 is removed to enlarge the first The step of forming a second opening 54 by the opening 54, that is, the second-stage etching, in addition to the above-mentioned general dry etching or wet etching, optionally replacing or adding a physical ion bombardment step. For example, in the second stage etching, an etching step is applied and a physical ion bombardment step is added, or a physical ion bombardment step is directly used instead of the general etching step to simultaneously perform the substructure layers 42a, 42b, 42c. The non-isotropic etching step further forms a beveled structure whereby the second opening 54 is rounded to expand outward.

As shown in FIG. 8, next, a wet etching process is performed and a remaining portion of the gate sacrificial layer 34a is completely removed through the second opening 54 to form a third opening 80. In a spatial relationship, the second opening 54 The width is substantially greater than the width of the first opening 52 and the third opening 80. It should be noted that the gate dielectric layer 32a disposed at the bottom of the third opening 80 is simultaneously exposed when the third opening 80 is formed. Then, using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, chemical vapor deposition (CVD) or physical vapor deposition (Physical Vapor) A process or the like is formed to form a work function adjustment layer 82 covering the gate dielectric layer 32a and the surface of the first sidewall member 42. In the present embodiment, the purpose of the work function adjustment layer 82 is to connect the energy level between the gate electrode of the semiconductor and the gate dielectric layer 32a to meet the work function matching adjustment. The function adjustment layer 82 may be composed of the N-type work function adjustment layer 82 or the P-type work function adjustment layer 82 depending on the type of the semiconductor. For example, if the semiconductor to be prepared is an N-type transistor, the work function adjusting layer may be selected, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum nitride ( A material such as TaSiN), aluminum (Al), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) or hafnium (Hf), or a combination thereof. However, if the prepared transistor is a P-type transistor, the work function adjusting layer may select, for example, titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni). ), ruthenium (Ru), tantalum carbonitride (TaCN) or tantalum oxynitride (TaCNO). In this embodiment, the work function adjusting layer is preferably made of ultra-thin titanium nitride (TiN), and can be combined with selective ion implantation to simultaneously satisfy the N-type transistor or the P-type transistor. The work function matches the requirements, and the thickness of the titanium nitride layer is substantially between 5 nm and 15 nm. Moreover, ultra-thin titanium nitride (TiN) is preferably fabricated by atomic layer deposition (ALD) to control the thickness of the coating to achieve high-quality step coverage and excellent thickness uniformity. Sex. It should be noted that, in addition to the single layer structure, the titanium nitride layer (TiN) of the present invention may have several variations according to the semiconductor structure design, and may be further subdivided into one layer, two layers or a plurality of layers. For example, the titanium nitride layer may be a Ti/TiN/Ti three-layer stack structure, or a two-layer TiNTi/TiN two-layer stack structure, and the stacking manner may be arranged in combination without being limited.

As shown in FIG. 9, next, a gate conductive layer 90 is formed to fill the third opening 80 and the second opening 54. In the present embodiment, the gate conductive layer 90 is preferably made of aluminum (Al) metal, but may also be made of a low resistance material such as tungsten (W), titanium aluminum alloy (TiAl) or cobalt tungsten phosphide (cobalt tungsten). Phosphide, CoWP). Subsequently, another planarization process may be selectively employed to remove the gate conductive layer 90 and the work function adjustment layer 82 partially covering the interlayer dielectric layer 46, so that the processed gate conductive layer 90 is substantially cut. The surface of the interlayer dielectric layer 46 is aligned to complete the semiconductor structure 94 having a metal gate.

FIG. 9 is a schematic view showing a preferred embodiment of a semiconductor structure having a metal gate according to the present invention. FIG. 9 is a schematic view showing a final structure of a semiconductor structure having a metal gate according to the present invention. As shown in FIG. 9, the semiconductor structure having a metal gate of the present invention comprises a semiconductor substrate 30, a gate structure 92, a first sidewall portion 42, a second sidewall portion 43 and a work function adjusting layer 82. The gate structure 92 is disposed on the semiconductor substrate 30, and the gate structure 92 includes at least a gate dielectric layer 32a and a gate conductive layer 90, and the first sidewall member 42 includes a plurality of substructure layers, and each of the plurality of substructure layers The thickness of the substructure layer is substantially between 1 nm and 5 nm. The gate conductive layer 90 includes a first metal portion 90a and a second metal portion 90b, and the second metal portion 90b covers the first metal portion 90a. It should be noted that, in this embodiment, a work function adjusting layer 82 is first disposed on the first sidewall 42 and the gate dielectric layer 32a, and is disposed on the gate dielectric layer 32a and the first metal portion. Between the portions 90a, the gate conductive layer 90 is overlaid on the work function adjusting layer 82. Regarding the semiconductor structural material having the metal gate of the present invention, the material of the semiconductor substrate 30 includes bismuth (Si), germanium (SiGe), epitaxial germanium or epitaxial germanium. Further, the material of the gate dielectric layer 32a includes an oxide, cerium oxide, cerium oxynitride (SiON), cerium nitride (Si ₃ N ₄ ), cerium oxide (Ta ₂ O ₅ ), and aluminum oxide (Al ₂ O _{5 ).} ), cerium oxide (HfO), nitrogen oxides, cerium-containing oxides, cerium-containing oxides, aluminum-containing oxides or high dielectric constant (K>5) materials, or combinations thereof. In the present embodiment, the work function adjusting layer 82 includes an N-type work function metal material or a P-type work function metal material, and the work function adjusting layer 82 is disposed for the purpose of dielectrically shielding the gate conductive layer 90 and the gate of the semiconductor. The level between the layers 32a is connected to the work function to match the work function matching adjustment. In terms of material selection of the work function adjusting layer 82, for example, the N-type work function metal material includes titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum nitride (TaSiN), Aluminum (Al), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) or hafnium (Hf). For example, the P-type work function metal material includes titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), tantalum carbonitride ( TaCN) or tantalum oxynitride (TaCNO). It should be noted that the work function adjusting layer 82 is preferably a titanium nitride layer, and the thickness of the titanium nitride layer is substantially between 5 nm and 15 nm. In terms of spatial distribution of the semiconductor structure, the first sidewall 42 is disposed on the surrounding sidewall of the first metal portion 90a and below the second metal portion 90b. Moreover, the second side wall portion 43 is disposed on the side wall of the second metal portion 90b and the first side wall portion 42. Please refer to FIG. 10 again. FIG. 10 is a schematic view showing another preferred embodiment of the semiconductor structure having a metal gate according to the present invention. 10 is different from FIG. 9 only in that the first sidewall 42 of FIG. 10 has a sloped structure adjacent to the sidewall of the gate conductive layer 90, and the work function adjusting layer 82 extends the first sidewall 42 to cover the first sidewall 42 A metal portion 90a is disposed on the first sidewall portion 42 and the second metal portion 90b covers the first metal portion 90a and the first sidewall portion 42. Therefore, in the embodiment, the first sidewall portion 42 is provided. An opening is enlarged outward to accommodate the gate conductive layer 90. In addition, the same component parts of the embodiment are illustrated and described in the foregoing FIG. 9 and will not be further described herein.

In summary, the semiconductor structure and method for forming a metal gate of the present invention mainly utilizes an enlarged opening formed by removing a portion of the first sidewall, and then completing the fabrication of the gate conductive layer via the enlarged opening. The semiconductor structure and formation method with metal gate of the invention not only solves the limitation of the aspect ratio of the narrow gate structure of the semiconductor structure with the metal gate, but also provides a good step coverage which cannot be achieved by the conventional deposition process. And overcoming the occurrence of protrusions or holes in the gate conductive layer of the conventional gate structure trenches, and greatly improving the quality when forming the gate conductive layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Semiconductor substrate

12. . . Gate structure

12a. . . Virtual patterned polycrystalline layer

12b. . . Gate dielectric layer

13. . . Lightly doped bungee

14. . . Biased side wall

16. . . Side wall

17. . . Interlayer dielectric layer

18a. . . Source area

18b. . . Bungee area

19. . . Trench

20. . . Gate conductive layer

twenty one. . . Work function adjustment layer

30. . . Semiconductor substrate

32. . . Dielectric layer

32a. . . Gate dielectric layer

34. . . Polycrystalline layer

34a. . . Gate sacrificial layer

36. . . Patterned mask layer

38. . . Gate structure

40a. . . Source area

40b. . . Bungee area

42. . . First side wall

42a. . . Substructure layer

42b. . . Substructure layer

42c. . . Substructure layer

43. . . Second side wall

44a. . . Source area

44b. . . Bungee area

46. . . Interlayer dielectric layer

52. . . First opening

54. . . Second opening

80. . . Third opening

82. . . Work function adjustment layer

90. . . Gate conductive layer

90a. . . First metal part

90b. . . Second metal part

92. . . Gate structure

94. . . Semiconductor structure

d. . . Initial etch depth

1 to 2 are schematic views showing a method of forming a semiconductor structure having a metal gate.

3 to 9 are schematic views showing a method of forming a semiconductor structure having a metal gate according to the present invention.

FIG. 9 is a schematic view showing a preferred embodiment of a semiconductor structure having a metal gate according to the present invention.

Figure 10 is a schematic view of another preferred embodiment of a semiconductor structure having a metal gate of the present invention.

30. . . Semiconductor substrate

32a. . . Gate dielectric layer

40a. . . Source area

40b. . . Bungee area

42. . . First side wall

43. . . Second side wall

44a. . . Source area

44b. . . Bungee area

46. . . Interlayer dielectric layer

54. . . Second opening

80. . . Third opening

82. . . Work function adjustment layer

90a. . . First metal part

90b. . . Second metal part

90. . . Gate conductive layer

92. . . Gate structure

94. . . Semiconductor structure

Claims (24)

A method of forming a semiconductor structure having a metal gate, the method comprising the steps of: providing a semiconductor substrate; forming at least one gate structure on the semiconductor substrate, and the gate structure comprises a gate dielectric layer and a gate a sacrificial layer; forming a sidewall substructure on both sides of the gate structure; forming an interlayer dielectric layer overlying the gate structure and the sidewall substructure; planarizing the interlayer dielectric layer until the gate is exposed a sacrificial layer; removing a portion of the gate sacrificial layer to an initial etch depth to form an opening and exposing a portion of the sidewall substructure; removing a portion of the sidewall substructure exposed to the opening to expand the opening; completely removing a gate sacrificial layer; forming a gate conductive layer to fill the opening; and performing a planarization step on the gate conductive layer to make a top surface of the gate conductive layer and a top of the interlayer dielectric layer The face is aligned, and a portion of the gate conductive layer is located directly above the sidewall substructure. The method of claim 1, wherein the step of expanding the opening comprises an etching step. The method of claim 1, wherein the step of expanding the opening Contains a physical ion bombardment step. The method of claim 1, wherein the sidewall substructure comprises a first sidewall and a second sidewall, wherein the first sidewall is located on opposite sides of the gate structure, and the second sidewall On both sides of the first side wall. The method of claim 4, wherein the step of expanding the opening comprises partially removing the first sidewall exposed to the opening to the initial etch depth. The method of claim 4, wherein the first sidewall includes at least one layer of germanium oxide and at least one layer of tantalum nitride. The method of claim 6, wherein the step of expanding the opening removes the silicon oxide layer and a portion of the tantalum nitride layer. The method of claim 6, wherein the thickness of each of the silicon oxide layer and each of the tantalum nitride layers is substantially between 1 nm and 5 nm. The method of claim 1, wherein in the step of removing a portion of the gate sacrificial layer to the initial etch depth, the initial etch depth is at least greater than one-half the height of the gate sacrificial layer. The method of claim 1, wherein a work function adjusting layer is formed before the gate conductive layer is formed. The method of claim 10, wherein the work function adjustment layer comprises an N-type work function metal material or a P-type work function metal material. The method of claim 11, wherein the N-type work function metal material comprises titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum nitride (TaSiN), aluminum. (Al), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) or hafnium (Hf). The method of claim 11, wherein the P-type work function metal material comprises titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), Ruthenium (Ru), tantalum carbonitride (TaCN) or tantalum carbonitride (TaCNO). The method of claim 10, wherein the work function adjusting layer is preferably a titanium nitride layer. The method of claim 14, wherein the titanium nitride layer has a thickness substantially between 5 nm and 15 nm. A semiconductor structure having a metal gate, comprising: a semiconductor substrate; a gate structure is disposed on the semiconductor substrate, the gate structure includes a gate dielectric layer and a gate conductive layer, wherein the gate conductive layer comprises a first metal and a second metal, and the gate a second metal covering the first metal; an interlayer dielectric layer on the semiconductor substrate, and a top surface of the interlayer dielectric layer is aligned with a top surface of the second metal layer; a first sidewall And disposed on the two sides of the first metal, and the second metal covers the first side of the first sidewall; and a second sidewall disposed on opposite sides of the first sidewall. The structure of claim 16, wherein the first sidewall includes a plurality of substructure layers. The structure of claim 17, wherein the thickness of each of the substructure layers is substantially between 1 nm and 5 nm. The structure of claim 16 further comprising a work function adjusting layer disposed between the gate dielectric layer and the first metal. The structure of claim 19, wherein the work function adjusting layer comprises an N-type work function metal material or a P-type work function metal material. The structure of claim 20, wherein the N-type work function metal material comprises titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), Tantalum nitride (TaSiN), aluminum (Al), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) or hafnium (Hf). The structure of claim 20, wherein the P-type work function metal material comprises titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), Ruthenium (Ru), tantalum carbonitride (TaCN) or tantalum carbonitride (TaCNO). The structure of claim 19, wherein the work function adjusting layer is preferably a titanium nitride layer. The structure of claim 23, wherein the thickness of the titanium nitride layer is substantially between 5 nm and 15 nm.