201113958 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明是有關-種功率半導體晶片之無打線封 法及其製成品，尤指一種同時適用於倒置晶片 、 晶 (flip-chip)及打線（WIRE_B咖）等二種排列型 片無打線封裴方法及成品。 x之 【先前技術] [0002] 眾所周知’各種晶片之封裝方式對 執 響極大，傳H ^ 果影 〇 將”“ （如：LED)封裝方式，係 2片底。k晶焊之方式輝接於一封裝基座上广 金線將其正、負極㈣連α =熱傳導路線較長，且金線之熱傳導面積：封 影響其整體之Iβ 谓洱限， 發光強度）。 大功率（ [0003] 為此，乃有如中華民國公告第I 2 7 2 7 3 1 發光二極體盔打 3 1說「 Ο .，，、打線之封裝結構」發明專利案所揭矛| 其係將l ε η曰μ 丨构不者， 曰曰片以倒置晶片（FLIP- [0004] 式烊接於一矽晶辅助框架内，形 ，再將此模―心 封袭模組 製PC板上2置晶片表面封裝於具有散熱致果之結 具至少包括：一矽晶輔助框架，於复 形成正、負曾技+ * 、/、正面 罨極之鋅錫凸塊，於其背面則蝕刻 片之U形腔言 曰日 至，以供容納L· Ξ D晶片，利用蝕刻時之自 …遮罩在腔室内蒸鑛正、負電極及反射面；一發 體L· £ D晶片，认好 _ 於其背面設有一透明基板，而其正面則 分別設有一正、各帝』 098133898 負電極；一P C板，具有一陽極氧化層 表單編號A0101 0982058006-0 第3頁/共24頁 201113958 、印刷電路及散熱裝置；將該L E D晶片以倒置晶片方 式焊接該矽晶輔助框架内，L E D晶片之正、負電極形 成疊置封裝模組；將該疊置封裝模組以倒置晶片表面封 裝於該PC板上，在LED晶片表面上形成一微凸透鏡 〇 [0005] 然而，上述專利案所揭示倒置晶片（FLIP-CHIP)排 列之晶片封裝結構其雖可改善熱傳導效率，獲致較佳之 散熱效果，但其光線需穿過透明基板方得以向外發散， 會影響其發光效率，形成一應用上之缺失，因此其與傳 統之打線（WIRE-BOND)排列型式晶片封裝結構相較，二 者各有其優劣，而無法完全互相取代；再者，由於該案 所揭示之加工方式僅係針對倒置晶片（FLIP- [0006] CHIP)排列之晶片封裝結構，並無法應用於傳統打線 (WIRE-BOND)排列型式之晶片封裝結構，故而，就目前 的晶片封裝方式而言，傳統的打線（WIRE- [0007] BOND)排列型式與倒置晶片（FLIP-CHIP)排列型式之晶 片封裝方法完全不同 [0008] ，其整體之製程規劃與設備的設置亦不相同而無法共用 ，如此一來，不但造成生產上之不便，亦難以有效降低 其生產成本。 [0009] 有鑑於習見之晶片封裝方法及其結構有上述缺點， 發明人乃針對該些缺點研究改進之道，終於有本發明產 生。 【發明内容】 098133898 表單編號A0101 第4頁/共24頁 0982058006-0 201113958 [0010] 本發明之主要目的在於提供一種功率半導體晶片之 無打線封裝方法，其以單一加工方法可同時適用於不同 排列型式之封裝需求，可有效簡化加工程序、降低生產 成本。 [0011] [0012] ο Ο [0013] [0014] [0015] 098133898 本發明之另一目的在於提供一種功率半導體晶片之 無打線封裝成品，其可提供良好的熱傳導效果、進而增 進散熱效率。 為達成上述目的及功效，本發明所採行的技術手段 包括：一種功率半導體晶片之無打線封裝方法，其至少 包括：一「形成第一傳導層」步驟，係於一載體上形成 各自具有正、負極接合部之複數第一傳導層；一「晶片 焊接」步驟，將複數半導體晶片之正、負電極各經由一 傳導件分別焊合於該正、負極接合部；一「封裝塑型」 步驟，以封裝材料填充於各半導體晶片周側；一「切割 」步驟，於移除載體後，將各封裝後之半導體晶片分別 切割為個別單一顆粒。. 依上述方法，其中該「封裝塑型」步驟實施前，先 經一「結合反射層」步驟，以將一導線框架結合於該第 一傳導層上，該導線框架並於半導體晶片周側形成一腔 室。 依上述方法，其中該腔室内周侧形成一光線之反射 面。 依上述方法，其令該「封裝塑型」步驟完成後，再 經由一「形成第二傳導層」步驟，以至少於對應各半導 表單編號Α0101 第5頁/共24頁 0982058006-0 201113958 [0016] 體b曰片之部位形成一相吻合之第二傳導層。 本發月所採仃的技術手段另包括：__種功率半導體晶片 之無打線封裝製成品’其至少包括：一半導體晶片，至 少具有正、負二電極，·_第—傳導層，至少具有正、負 極接合部’以供與該半導體晶片之正、負電極形成電連 接□封體，係以封裝材料成型於該半導體晶片周側 [0017] [0018] [0019] [0020] [0021] 098133898 迷、·。構’其中該半導體晶片周側設有-導線框 架’且該導線框架於半導體晶片周側形成一腔室。 依上述結構，其㈣腔室鮮側設有—反射面。 依上述結構’其中至少於鱗導“片臨第一傳導 層之反側另設有一第二傳導層。 為使本發明的上述目的、功效及特徵可獲致更具體 的瞭解，茲依下列附圖說明如下： 【實施方式】 請參第1圖所示，明顯可看出，本發明之第一實施 例主要包括：―「形成第—傳導層」S11步驟、一「 晶片焊接」S 1 2步驟' —「封壯細 封裝塑型」S14步驟及 一切割」S16步驟：以下僅參照第2圖作 明，首先該「形成第一傳導 層j S1 1步驟係於一載體 6上（可利㈣歧層、㈣、機械加卫或雷射加工等 方式）形成各自具有正、負極接合部u、12之複數 第-傳導層1，該「晶片煜I 2之複數 车遙驊 接」s12步驟則係將複數 半‘體曰日片2之正、参雷权々 負電極各經由一傳導件2 i、2 2 第6頁/共24頁201113958 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a wire-free sealing method for a power semiconductor wafer and a finished product thereof, and more particularly to an inverted wafer, a flip-chip. And the line (WIRE_B coffee) and other two types of arrays without wire sealing method and finished products. x [Prior Art] [0002] It is well known that the packaging method of various wafers is extremely versatile, and the transmission of H ^ 影 will be "" (eg LED) package method, which is a two-chip bottom. The method of k crystal welding is connected to a packaged pedestal. The gold wire connects the positive and negative electrodes (4) with α = heat conduction path is long, and the heat conduction area of the gold wire: the sealing affects the overall Iβ threshold, luminous intensity) . High power ([0003] For this reason, it is like the Republic of China Announcement No. I 2 7 2 7 3 1 LED Helmet Helmet 3 1 says "Ο.,,, the packaging structure of the wire" The ε η 曰 曰 丨 , , , , , , 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 倒 FL FL 倒 FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL FL The upper surface of the wafer is packaged on the surface of the wafer having heat dissipation and at least includes: a twin crystal auxiliary frame, which forms a zinc-tin bump of positive and negative prior art +*, /, front bungee, and is etched on the back surface thereof. The U-shaped cavity of the film is used to accommodate the L· Ξ D wafer, and the positive and negative electrodes and the reflecting surface of the ore are vaporized in the chamber by etching; the L·£ D wafer of a hair body is recognized. Good _ has a transparent substrate on the back side, and a positive electrode on each side of the body, 098133898 negative electrode; a PC board with an anodized layer form number A0101 0982058006-0 page 3 / total 24 pages 201113958, a printed circuit and a heat sink; soldering the LED wafer to the twin crystal auxiliary frame in an inverted wafer manner, L The positive and negative electrodes of the ED chip form a stacked package module; the stacked package module is packaged on the PC board with an inverted wafer surface to form a micro convex lens on the surface of the LED chip. [0005] However, the above patent case The disclosed wafer package structure of inverted wafer (FLIP-CHIP) can improve the heat conduction efficiency and achieve better heat dissipation effect, but the light needs to pass through the transparent substrate to be diverged outward, which will affect the luminous efficiency and form an application. The lack of the above, so compared with the traditional wire-wound (WIRE-BOND) array type chip package structure, both have their advantages and disadvantages, and can not completely replace each other; further, because the case disclosed the processing method is only for The wafer package structure of the inverted wafer (FLIP-[0006] CHIP) cannot be applied to the wafer package structure of the conventional wire-wound (WIRE-BOND) arrangement type. Therefore, in the current chip package method, the conventional wire bonding (WIRE) - [0007] BOND) Array type and inverted chip (FLIP-CHIP) arrangement type chip packaging method is completely different [0008], its overall process planning and equipment design It is also different and cannot be shared. As a result, it is not only inconvenient in production, but also difficult to effectively reduce its production cost. [0009] In view of the above-mentioned shortcomings of the chip packaging method and its structure, the inventors have addressed these shortcomings. The present invention has been developed in accordance with the present invention. [0001] The main object of the present invention is to provide a non-wire-wrapping method for a power semiconductor wafer, [0110] It can be applied to different packaging types in a single processing method, which can simplify the processing procedure and reduce the production cost. [0012] [0012] [0015] [0015] Another object of the present invention is to provide a wire-free packaged product of a power semiconductor wafer that provides good heat transfer and thereby increases heat dissipation efficiency. In order to achieve the above object and effect, the technical means adopted by the present invention include: a method for non-wire bonding of a power semiconductor wafer, comprising at least: a step of "forming a first conductive layer", which is formed on a carrier to form a positive a plurality of first conductive layers of the negative electrode joint portion; a "wafer soldering" step of soldering the positive and negative electrodes of the plurality of semiconductor wafers to the positive and negative electrode portions via a conductive member; Filling the peripheral side of each semiconductor wafer with a packaging material; a "cutting" step, after removing the carrier, respectively cutting each packaged semiconductor wafer into individual single particles. According to the above method, before the "packaging and molding" step is performed, a "bonding reflective layer" step is performed to bond a lead frame to the first conductive layer, and the lead frame is formed on the peripheral side of the semiconductor wafer. a chamber. According to the above method, a reflecting surface of the light is formed on the circumferential side of the chamber. According to the above method, after the "packaging and molding" step is completed, the step of "forming the second conductive layer" is performed to at least correspond to each semi-conductive form number Α0101, page 5 / total 24 pages 0982058006-0 201113958 [ 0016] The portion of the body b is formed into a matching second conductive layer. The technical means adopted in this month further includes: __ a power-free semiconductor wafer, a wire-free package finished product, which comprises at least: a semiconductor wafer having at least positive and negative electrodes, and a first conductive layer having at least The positive and negative junctions ' are electrically connected to the positive and negative electrodes of the semiconductor wafer, and are sealed on the semiconductor wafer by the encapsulation material. [0018] [0020] 098133898 Fan,·. The semiconductor wafer is provided with a - lead frame on the peripheral side of the semiconductor wafer and the lead frame forms a chamber on the peripheral side of the semiconductor wafer. According to the above structure, the (4) fresh side of the chamber is provided with a reflecting surface. According to the above structure, the second conductive layer is further disposed on the opposite side of the first conductive layer at least on the scale guide. In order to achieve a more specific understanding of the above objects, functions and features of the present invention, the following drawings are used. The following is a description of the following: [Embodiment] Referring to Figure 1, it can be clearly seen that the first embodiment of the present invention mainly includes: ""forming the first conductive layer" step S11, a "wafer soldering" S 1 2 step '-"Blocking and squeezing and molding" S14 step and one cutting" S16 step: The following only refers to Fig. 2, firstly, the step of forming the first conductive layer j S1 1 is attached to a carrier 6 (Keli (4) a plurality of first-conducting layers 1 each having a positive and negative junction portion u, 12 formed by a dissimilar layer, (4), mechanical reinforcement or laser processing, and the "multiple cars of the wafer 煜I 2 are spliced" s12 step The system is to use a pair of conductive members 2 i, 2 2 Page 6 of 24
(J 表單編號A0101 0982058006-0 201113958 刀別焊合於該第一傳導層J之正、負極接合部1工、工 2上，而「封裝塑型」s 1 4步驟係以封裝材料3 0 ( 可為具透光性）填充於各半導體晶片2周側以形成—固 封體’最後「切割」S ! 6步驟係於移除載體6之後， 將各封裝後之半導體晶片2分別切割為個別單一顆粒。 [0022] [0023] Ο 依上述第一實施例方法所成型之結構，係為一般打 線（WIRE-BOND)之基本排列型式的晶片封裝結構，若該 半導體晶片2為-發光二極體LED晶片，則其電流係 由正極接合部i i通過傳導件21至半導體晶片2，再 由半導體晶片2經傳導件2 2至負極接合部！ 2，其光 線則可由半導體晶片2向麵解層1之反侧直接對外 發散，而該半導體晶片2峨生絲量則可由傳導件2 1、2 2分別導引至第一傳導層i，再由第一傳導層工 向外發散。 請參第3圖所示，可知本發明之第二實施例包括： -「形成第-傳導層」S11步驟、_「晶片焊接」s 1 2步驟、—「結合反射層」S 1 3步驟、一「封裝塑 型」S 1 4步驟及-「切割」s 1 6步驟；與該第一實 施例之方法相較，其僅係於「魏塑型」s i 4步驟之 4圖作-實際說明，首先該「形成第—傳導層」$ 1 1 步驟係於-載體6上形成各自具有正1極接合部U 、12之複數第一傳導層1，該「晶片焊接」S12步 驟則係將複數轉體晶片2之正、負私各經由一傳導 件2 1、22分別焊合於該第一傳導層工之正、負極招 098133898 表單編號A0101 第7更/共24頁 201113958 ° β 1 1、1 2上，.該「結合反射層」s丄3步驟係將 一導線框架4結合於該第―傳導層1上，該導線框架4 並可於半導體晶片2周侧形成一具反射面4 2之腔室4 1，且§亥反射面4 2係由臨第一傳導層^之一側向另一 侧逐漸擴張延伸’而「封裝塑型」s i 4步驟係以具透 光性之封裝材料3 1填纽各半導體晶片2周側以軸 -固封體’最後「切割」S i 6步驟係於移除載體6之 後’將各封裝後之半導體晶片2分別切割為個別單—顆 粒。 [0024] [0025] 依上述第二實施例方法所成型之結構，係為—具有 光線反射裝置之打線（W丨RE -B_)排_式晶片封裝結 構’若該半導體晶片2為一發光二極體LED晶片，則 其電流係由正極接合部i i通過傳導件2 i至半導體晶 片2 ’再由半導體晶片2經傳導件2 2至負極接合部丄 2，其光線除可由半導體晶片2向第一傳導層丄之反側 直接對外發散外，亦有部份光線係由二側經由反射面4 2向外反射，而該半導體晶片2所產生之熱量則由傳導 件2 1、2 2分別導引至第—傳導層丄，再由該第一傳 導層1直接向外發散’或導引至導線框架4向外發散。 請參第5圖所示，可知本發明之第三實施例包括·· -「形成第-傳導層」S 1 i步驟一「晶片焊接」s 1 2步驟、-「結合反射層」s i 3步驟、—「封裝塑 型」S 1 4步驟、-「形成第二傳導層」s丄5步驟及 -「切割」S 1 6步驟；以下僅參照第6圖作一實際說 明’首先該「形成第—傳導層」s丄工步驟係於一載體 098133898 表單編號A0101 第8頁/共24頁 0982058006-0 201113958 Ο 6上（可以蒸鍍與蝕刻方式）形成各自具有正、負極接 合部1 1、1 2之複數第一傳導層1，且該第一傳導層 1於其正、負極接合部11、12之間並留有一鏤空之 投射道1 3，該「晶片焊接」s 1 2步驟係將複數半導 體β曰片2之正、負電極各經由一傳導件2 1、2 2分別 焊合於該第一傳導層1之正、負極接合部丄丄、丄2上 ，該「結合反射層」S 1 3步驟係將一導線框架4 〇結 合於該第一傳導層1上，該導線框架4 〇可於半導體晶 片2周側形成一腔室4 0 1，且於該腔室4 〇 1内周側 形成一光線之反射面4 0 2，而該反射面4 〇 2則係由 臨第一傳導層之一側向另一逐漸縮小延伸，而該「封 裝塑型j S 14步驟係以具透光性之封裝材料32填充 於各半導體晶片2周側以形成一固封體，「形成第二傳 導層」s 1 5步驟係於對應各半導體晶片2 (亦可依需 要同時對應於各導線框架4 〇部位）之部位形成一相吻 合之第二傳導層5 ’最後「_」s i 6步驟係於移除 ❹ [0026] 載體6之後，將各封裝後之半導體晶片2分別切割為個 別單一顆粒。 依上述第二實施例方法所成型之結構，係為一倒置 晶片（FLIP-CHIP)排列型式之晶片封裝結構，若該半導 體晶片2為-發光二極體LED晶片，則其電流係由正 極接合部1 1通過傳導件2 1至半導體晶片2，再由半 導體晶片2經傳導件2 2至負極接合部丄2，其光線除 可由半導體晶片2向第-傳導層χ之投射道i 3、通過: 1亦有部份光線係由二側經 098133898 表單編號A0101 第9頁/共24頁 201113958 由反射面4 ο 2通過封裝材料3 2向外反射，而其半導 體晶片2所產生之大部份熱量則可由第二傳導層5向外 發散。 [0027] 凊參第7圖所示，可知本發明之第四實施例包括： 一「形成第-傳導層」s 1 1步驟、-「晶片焊接」s 1 2步驟、-「結合反射層」S 1 3步驟、-「形成第 二傳導層」S 15步驟、一「封裝塑型」s“步驟及 切割J S 1 6步驟；與該第三實施例之方法相較， 其僅係將該「形成第二傳導層」s工5步驟移至「封裝 塑型」S 1 4步驟之前，並可依需要將該「結合反射層 ( 。，以下僅參照第8圖作一實]^說明，首先該「形成第 —傳導層」S 1 1步驟係於-載體6上（可以蒸鍵與餘 刻方式）形成各自具有正、負極接合部i ii 2之複 數第一傳導層1，且該第-傳導層2於其正、負極接合 1 1、1 2之間並留有一鏤空之投射道丄3，該「晶 片焊接」S 1 2步驟係、將複數半導體晶片2之正、負電 極各經由-料件2 1、2 2分別焊合於該第_傳導層 Ο 1之正、負極接合部上，該「結合反射層」曰 s 1 3步驟係將—導線框架4 Q結合於該第—傳導層工 上’該導線框架4 0可於半導體晶片2周側形成一腔室 401，且於該腔室4〇1内周側形成—光線之反射面 4 0 2，而該反射面4 0 2則係由臨第一傳導層之一侧 向另一側逐漸縮小延伸，「形成第二傳導層」s25步 驟係於對應各半導體晶片2、導線框架4 q之部位形成 098133898 表單編號A0101 第10頁/共24頁 0982058006-0 201113958 一相吻合之第二傳導層5 Ο (於本實施例中，該第二傳 導層5 0亦可依需要而直接成型於該半導體晶片2、導 線框架4 0上），而該「封裝塑型j S 1 4步驟係以具 透光性之封裝材料3 2填充於各半導體晶片2周側以形 成一固封體，最後「切割j S 1 6步驟係於移除載體6 之後，將各封裝後之半導體晶片2分別切割為個別單一 顆粒。 [0028] Ο 依上述第四實施例方法所成型之結構，係為一與第 三實施例相同之倒置晶片（FLIP-CHIP)排列型式的晶片 封裝結構，若該半導體晶片2為一發光二極體L E D晶 片，則其電流係由正極接合部1 1通過傳導件2 1至半 導體晶片2，再由半導體晶片2經傳導件2 2至負極接 合部1 2，其光線除可由半導體晶片2向第一傳導層1 之投射道1 3，並通過封裝材料3 2直接向外發散外， 亦有部份光線由二側經由反射面4 0 2通過封裝材料3 2向外反射，而該半導體晶片2所產生之大部份熱量則 可由第二傳導層5 0向外發散。 ❹ . [0029] 综合以上所述，本發明功率半導體晶片之無打線封 裝方法及其製成品確可達成適用範圍廣泛、降低加工成 本之功效，實為一具新穎性及進步性之發明，爰依法提 出申請發明專利；惟上述說明之内容，僅為本發明之較 佳實施例說明，舉凡依本發明之技術手段與範疇所延伸 之變化、修飾、改變或等效置換者，亦皆應落入本發明 之專利申請範圍内。 【圖式簡單說明】 098133898 表單編號A0101 第11頁/共24頁 0982058006-0 201113958 [0030] 第1圖係本發明之封裝方法第一實施例流程圖。 [0031] 第2圖係依第1圖所示流程之應用實施例圖。 [0032] 第3圖係本發明之封裝方法第二實施例流程圖。 [0033] 第4圖係依第3圖所示流程之應用實施例圖。 [0034] 第5圖係本發明之封裝方法第三實施例流程圖。 [0035] 第6圖係依第5圖所示流程之應用實施例圖。 [0036] 第7圖係本發明之封裝方法第四實施例流程圖。 [0037] 第8圖係依第7圖所示流程之應用實施例圖。 【主要元件符號說明】 [0038] S11...形成第一傳導層 [0039] S12. ·.晶片焊接 [0040] S13...結合反射層 [0041] S14...封裝塑型 [0042] S15. . ·形成第二傳導層 [0043] S16...切割 [0044] 1.....第一傳導層 [0045] 11____正極接合部 [0046] 12____負極接合部 [0047] 13____投射道 [0048] 2.....半導體晶片 098133898 表單編號A0101 第12頁/共24頁 0982058006-0 201113958 [0049] [0050] [0051] [0052] [0053] [0054] [0055] Ο 21、22____傳導件 3、 31、32____封裝材料 4、 40____導線框架 41、 401...腔室 42、 402...反射面 5、 50____第二傳導層 6.....載體 ❹ 098133898 表單編號Α0101 第13頁/共24頁 0982058006-0(J Form No. A0101 0982058006-0 201113958 The blade is soldered to the positive and negative junctions 1 of the first conductive layer J, and the "package molding" s 1 4 step is made of the packaging material 30 ( The light-transmissive layer may be filled on the circumferential side of each of the semiconductor wafers to form a solid-packed body. Finally, the "cut" S is performed. After the carrier 6 is removed, the packaged semiconductor wafers 2 are individually cut into individual pieces. [0023] [0023] The structure formed by the method of the first embodiment is a basic package type of a general wiring type (WIRE-BOND), if the semiconductor wafer 2 is a light-emitting diode The body LED chip, the current is from the positive electrode junction portion ii through the conductive member 21 to the semiconductor wafer 2, and then from the semiconductor wafer 2 through the conductive member 2 2 to the negative electrode junction portion 2, the light can be layered by the semiconductor wafer 2 The opposite side of 1 is directly diverged to the outside, and the amount of green wire of the semiconductor wafer 2 can be respectively guided to the first conductive layer i by the conductive members 2 1 and 2 2, and then diverged outward by the first conductive layer. As shown, it can be seen that the second embodiment of the present invention includes : - "Forming the first conductive layer" S11 step, _ "wafer soldering" s 1 2 step, "combined reflective layer" S 1 3 step, a "packaging molding" S 1 4 step and - "cutting" s 1 6 steps; compared with the method of the first embodiment, it is only in the "Wei plastic type" si 4 step 4 - actual description, first of all, the "formation of the first conductive layer" $ 1 1 step is tied to - The carrier 6 is formed with a plurality of first conductive layers 1 each having a positive 1-pole junction U, 12. The "wafer soldering" step S12 is performed by passing the positive and negative electrodes of the plurality of rotating wafers 2 through a conductive member 2, 22 respectively welded to the first conductive layer of the positive and negative poles 098133898 Form No. A0101 No. 7 / Total 24 pages 201113958 ° β 1 1 , 1 2, the "combined reflective layer" s丄 3 steps will be A lead frame 4 is bonded to the first conductive layer 1, and the lead frame 4 can form a chamber 4 1 having a reflecting surface 42 on the circumferential side of the semiconductor wafer 2, and the reflecting surface 42 is formed by the first One of the conductive layers is gradually expanded toward the other side, and the "package molding" si 4 step is filled with a translucent packaging material 3 1 The peripheral side of the body wafer 2 is axially-sealed, and the final "cut" S i 6 step is followed by removing the carrier 6 to 'cut each packaged semiconductor wafer 2 into individual single-particles, respectively. [0025] The structure formed by the method of the second embodiment is a wire-shaping device (W丨RE-B_) row-type chip package structure. If the semiconductor wafer 2 is a light-emitting diode LED chip, The current is from the positive electrode junction portion ii through the conductive member 2 i to the semiconductor wafer 2' and then from the semiconductor wafer 2 through the conductive member 2 2 to the negative electrode junction portion ,2, the light of which can be reversed by the semiconductor wafer 2 toward the first conductive layer The side directly radiates outward, and some of the light is reflected outward from the two sides via the reflecting surface 42, and the heat generated by the semiconductor wafer 2 is guided to the first conductive layer by the conductive members 2, 2, respectively. Then, the first conductive layer 1 is directly diverged outwardly or guided to the lead frame 4 to diverge outward. Referring to FIG. 5, it can be seen that the third embodiment of the present invention includes the steps of "forming a first conductive layer" S 1 i, a "wafer soldering" s 1 2 step, and a "combining a reflective layer" si 3 step. - "Package Molding" S 1 4 steps, - "Forming a second conductive layer" s 丄 5 steps and - "Cut" S 16 steps; the following only refers to Figure 6 for an actual description 'First of the - Conductive layer" s completion steps are based on a carrier 098133898 Form No. A0101 Page 8 / 24 pages 0982058006-0 201113958 Ο 6 (can be evaporated and etched) to form a positive and negative junction 1 1 , 1 2 of the plurality of first conductive layers 1, and the first conductive layer 1 has a hollow projection track 13 between its positive and negative junctions 11, 12, and the "wafer soldering" s 1 2 step will be plural The positive and negative electrodes of the semiconductor beta wafer 2 are respectively soldered to the positive and negative junction portions 丄丄 and 丄2 of the first conductive layer 1 via a conductive member 2 1 , 2 2 , and the “combined reflective layer” S 1 3 step is to bond a lead frame 4 〇 to the first conductive layer 1 , the lead frame 4 〇 can be semiconductor crystal A chamber 4 0 1 is formed on the 2nd side, and a light reflecting surface 420 is formed on the inner circumference side of the chamber 4 〇1, and the reflecting surface 4 〇2 is formed on one side of the first conductive layer. The tape-forming step S S 14 is filled with a light-transmissive encapsulating material 32 on the peripheral side of each semiconductor wafer 2 to form a solid body, "forming a second conductive layer" The step 1 5 is to form a matching second conductive layer 5 corresponding to each semiconductor wafer 2 (which may also correspond to each of the lead frames of the lead frame as needed). Finally, the "_" si 6 step is removed. After the carrier 6, the packaged semiconductor wafers 2 are individually cut into individual individual particles. The structure formed by the method of the second embodiment is a wafer package structure of an inverted wafer (FLIP-CHIP) arrangement. If the semiconductor wafer 2 is a light-emitting diode LED chip, the current is bonded by the positive electrode. The portion 1 1 passes through the conductive member 2 1 to the semiconductor wafer 2, and then passes through the conductive member 2 2 to the negative electrode junction portion 丄 2 of the semiconductor wafer 2, the light of which can pass through the projection path i 3 of the semiconductor wafer 2 to the first conductive layer : 1 There is also a part of the light system from the two sides through 098133898 Form No. A0101 Page 9 / Total 24 Page 201113958 Reflected by the reflective surface 4 ο 2 through the encapsulation material 3 2, and most of its semiconductor wafer 2 The heat can be diverged outward from the second conductive layer 5. [0027] As shown in FIG. 7, it can be seen that the fourth embodiment of the present invention includes: a "forming a first conductive layer" s 1 1 step, a "wafer soldering" s 1 2 step, and a "bonding reflective layer". S 1 3 step, - "forming a second conductive layer" S 15 step, a "package molding" s "step and cutting JS 16 step; compared with the method of the third embodiment, it is only the " The step of forming the second conductive layer is moved to the step of "packaging and molding" S 1 4, and the "reflecting layer" can be used as needed (hereinafter, only refer to Fig. 8 for a real explanation), first The "forming the first conductive layer" S 1 1 step is formed on the carrier 6 (which can be steamed and left in a manner) to form a plurality of first conductive layers 1 each having a positive and negative electrode junction i ii 2 , and the first The conductive layer 2 has a hollow projection channel 3 between the positive and negative electrodes 1 1 and 1 2, and the "wafer soldering" S 1 2 step passes through the positive and negative electrodes of the plurality of semiconductor wafers 2 respectively. The material members 2 1 and 2 2 are respectively welded to the positive and negative electrode joint portions of the first conductive layer Ο 1 , and the “combined reflective layer” 曰 s 1 3 step will be The lead frame 4 Q is bonded to the first conductive layer. The lead frame 40 forms a cavity 401 on the peripheral side of the semiconductor wafer 2, and forms a light reflecting surface 4 on the inner peripheral side of the chamber 4〇1. 0 2, and the reflecting surface 410 is gradually extended from one side of the first conductive layer to the other side, and the step of forming the second conductive layer s25 is performed on the corresponding semiconductor wafer 2 and the lead frame 4 q The part is formed by 098133898 Form No. A0101 Page 10 / Total 24 page 0982058006-0 201113958 A matching second conductive layer 5 Ο (In this embodiment, the second conductive layer 50 can also be directly formed on the need The semiconductor wafer 2 and the lead frame 40 are mounted on the peripheral side of each semiconductor wafer 2 to form a solid body, and finally the "package molding type j S 14 step" is filled with a light-transmissive encapsulating material 32. The process of cutting the J S 16 is performed by removing the packaged semiconductor wafer 2 into individual single particles, respectively. [0028] The structure formed by the method of the fourth embodiment described above is Inverted wafer (FLIP-CHIP) arrangement type of the third embodiment The chip package structure, if the semiconductor wafer 2 is a light-emitting diode LED chip, the current is from the positive electrode junction 11 through the conductive member 21 to the semiconductor wafer 2, and then from the semiconductor wafer 2 through the conductive member 2 2 The negative electrode joint portion 1 2, except for the light that can be diffused from the semiconductor wafer 2 to the first conductive layer 1 and diffused outwardly through the encapsulating material 3 2 , and some of the light is transmitted from the two sides via the reflecting surface 40 . 2 is outwardly reflected by the encapsulation material 3 2, and most of the heat generated by the semiconductor wafer 2 is diverged outward from the second conductive layer 50. [0029] In summary, the non-wire-wrapping method and the finished product of the power semiconductor wafer of the present invention can achieve a wide range of applications and reduce the processing cost, and is a novel and progressive invention. The invention is filed in accordance with the law; however, the above description is only for the preferred embodiment of the present invention, and any changes, modifications, alterations or equivalent replacements in accordance with the technical means and scope of the present invention should also fall. It is within the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS 098133898 Form No. A0101 Page 11 of 24 0982058006-0 201113958 [0030] Fig. 1 is a flow chart showing a first embodiment of the packaging method of the present invention. [0031] FIG. 2 is a diagram showing an application example of the flow shown in FIG. 1. [0032] FIG. 3 is a flow chart of a second embodiment of the packaging method of the present invention. [0033] FIG. 4 is a diagram showing an application example of the flow shown in FIG. 3. [0034] FIG. 5 is a flow chart of a third embodiment of the packaging method of the present invention. [0035] FIG. 6 is a diagram showing an application example of the flow shown in FIG. 5. 7 is a flow chart of a fourth embodiment of the packaging method of the present invention. [0037] FIG. 8 is a diagram showing an application example of the flow shown in FIG. 7. [Description of main component symbols] [0038] S11...forms a first conductive layer [0039] S12. Wafer soldering [0040] S13...in combination with a reflective layer [0041] S14...package molding [0042] S15.. Forming a second conductive layer [0043] S16...cutting [0044] 1.....first conductive layer [0045] 11____ positive junction [0046] 12____ negative junction [0047] 13___ _Projecting Channel [0048] 2.....Semiconductor Wafer 098133898 Form No. A0101 Page 12 of 24 0982058006-0 201113958 [0049] [0055] [0055] [0055] Ο 21, 22____ Conducting members 3, 31, 32____ encapsulating material 4, 40____ lead frame 41, 401... chambers 42, 402... reflecting surfaces 5, 50____ second conducting layer 6.... . Carrier ❹ 098133898 Form Number Α 0101 Page 13 / Total 24 Page 0982058006-0