201112595 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種電源轉換器，特別是關於一種電源轉 換器的控制器晶片及保護方法。 【先前技術】 圖1係習知的交流對直流電源轉換器，其中供應電源轉 換器的父流電麗VAC經渡波及整流後得到直流電壓vdc， 施加到變壓器T1的一次側線圈Lp，控制器晶片10中的驅動 器18提供控制信號Vgate切換功率開關Q1，將一次侧線圈 Lp上的電壓VDC轉換為輸出電壓v〇。控制器晶片10中的 高壓啟動元件16連接在高壓接腳HV及電源接腳VDD之 間，在交流電壓VAC剛供應給電源轉換器時啟動控制器晶片 10。在控制器晶片10啟動後，輔助線圈Laux產生電流經電 阻R1及二極體D1對電源電容C1充電，因而供應電力給控 制器晶片10。在交流對直流電源轉換器中，為了避免因直流 電壓VDC過低而造成負載電路發生不正讀的操作，因此設有 低壓狀態偵測器12監視直流電壓VDC。低壓狀態偵測器12 包括電阻R2、R3、R4以及磁滯比較器μ。電阻R2、R3及 R4分壓直流電壓VDC產生電壓V1，磁滯比較器14比較電 壓VI及臨界值Vref而決定保護信號Sc，進而啟動或關閉驅 動器18。低壓狀態谓測器12需要外部電阻R2、R3及R4， 而且控制器晶片10需要為其提供額外的接腳εν，因此增加 了成本。低壓狀態伯測器12也造成電流一直經由電阻R2、 201112595 R3及R4流向地端，導致能量消耗。 【發明内容】 本發明的目的之一’在於提出一種電源轉換器的控制器 晶片® 本發明的目的之一，在於提出一種電源轉換器的保護方 法。 根據本發明，一種電源轉換器的控制器晶片包括高壓接201112595 VI. Description of the Invention: [Technical Field] The present invention relates to a power converter, and more particularly to a controller chip and a protection method for a power converter. [Prior Art] FIG. 1 is a conventional AC-to-DC power converter in which a parent-current power VAC of a power supply converter is subjected to wave-wave and rectification to obtain a DC voltage vdc, which is applied to a primary-side coil Lp of a transformer T1, and a controller The driver 18 in the wafer 10 supplies a control signal Vgate to switch the power switch Q1 to convert the voltage VDC on the primary side coil Lp to an output voltage v〇. The high voltage starting element 16 in the controller wafer 10 is connected between the high voltage pin HV and the power pin VDD to activate the controller chip 10 when the AC voltage VAC is just supplied to the power converter. After the controller wafer 10 is activated, the auxiliary winding Laux generates a current to charge the power supply capacitor C1 via the resistor R1 and the diode D1, thereby supplying power to the controller wafer 10. In the AC-to-DC power converter, in order to avoid an unread operation of the load circuit due to a low DC voltage VDC, a low-voltage state detector 12 is provided to monitor the DC voltage VDC. The low voltage state detector 12 includes resistors R2, R3, R4 and a hysteresis comparator μ. The resistors R2, R3 and R4 divide the DC voltage VDC to generate a voltage V1, and the hysteresis comparator 14 compares the voltage VI and the threshold Vref to determine the protection signal Sc, thereby turning the driver 18 on or off. The low voltage state detector 12 requires external resistors R2, R3 and R4, and the controller wafer 10 needs to be provided with additional pins εν, thus increasing cost. The low voltage state detector 12 also causes current to flow to the ground via resistors R2, 201112595 R3 and R4, resulting in energy consumption. SUMMARY OF THE INVENTION One object of the present invention is to provide a controller wafer of a power converter. One of the objects of the present invention is to provide a method of protecting a power converter. According to the present invention, a controller chip of a power converter includes a high voltage connection
腳、電源接腳及接面場效電晶體（juncti〇n Fieid EffectFoot, power pin and junction field effect transistor (juncti〇n Fieid Effect
Transistor; JFET)作為高壓啟動元件，該jpet具有汲極連接 該高壓接腳，二極體具有陽極連接該JFET的源極以及陰極連 接該JFET電晶體的閘極及該電源接腳，賴電路連接該 JFET的雜’監視該雜電壓以蚊猶錢，以及制器 連接該電雜腳’齡m電源接腳的電壓以決定侧信號供 切換該JFET。 根據本發明 裡电轉換H的賴方法包括在電源择 啟時經：聊職職料電，在該電源f容上㈣壓達湘 界值時截’以及在該肺τ鼓_職薦合 源極電壓以決定保護信號。 由於利用控制器晶片屌古从_广 , At 原有的尚壓啟動元件來達成電路名 蠖功能，因此不需要增加拎击丨。„ i制裔曰日片的接腳及外部元件。 【實施方式】 電源轉換器’其中控制器晶片20實 圖2係應用本發明的 201112595 現保護功能的機制與習知技術不同。在控制器晶片2〇中，作 為阿壓啟動元件22的ΠΈΤ 24具有汲極連接高壓接腳HV， 一極體Dh具有陽極連接jpET 24的源極以及陰極經限流電阻 仙連接IFET 24的閘極’二極體Dh的陰極亦連接電源接腳 VDD，開關ST連接在JFET 24的閘極及地端GND之間，偵 測器26偵測電源接腳VDD的電壓而決定偵測信號S1，用以 切換開關ST，保護電路28監視JFET 24的源極電壓JS而決 定保護信號。保護電路28包括低壓狀態偵測器30及過壓保 濩偵測器34。低壓狀態偵測器3〇具有磁滯比較器32比較電 壓JS及低壓臨界值vrefl而決定低壓保護信號BN〇,用以啟 動或關閉驅動器18。過壓保護偵測器34具有磁滯比較器36 比較電壓JS及過壓臨界值Vref2而決定過壓保護信號〇Vp 給驅動器18。 由於JFET 24的特性是被調製而成的，因此其臨界電壓 Vth與其汲極電壓VDC有密切關聯，圖3係二者之間的特性 曲線。參照圖2及圖3，在電源啟動時，交流電壓VAC剛供 應給電源轉換器’JFET 24的閘極及源極的電壓相等或幾乎相 等，因此JFET 24為導通狀態，電流經由JFET 24、二極體 Dh及電源接腳VDD對電源電容C1充電。偵測器26偵測電 源電容C1上的電壓VDD，例如使用比較器38比較電壓vDD 及臨界值UVLO，當電壓VDD達到UVLO時，偵測器26觸 發偵測信.號81而打開(>1111〇11)開關8丁，因此用£丁24的閘極 電壓JG被拉到0V，使付JFET 24變為截止狀態，亦即不再 導通電流，故可節省電能。由於此時電源電容C1上的電壓 201112595 VDD已足夠啟動控制器晶片20，故驅動器18被啟動以產生 控制信號Vgate切換功率開關Q1，進而啟動輔助線圈Laux 供應控制器晶片20所需的電力，此時電源轉換器的啟動完 成。 在電源轉換器啟動後，JFET 24的閘極電壓JG為0V， 電源接腳VDD的電壓大於臨界值UVL〇,因此jpET24的源 極電壓JS將被鎖在jpet 24的臨界電壓Vth，如圖3所示。 ^ 當直流電壓VDC改變時，JFET24的臨界電壓Vth也將跟著 變化，因此低壓狀態偵測器30可以藉由偵測JFET24的源極 電壓JS判斷直流電壓vdc是否過低。假設啟動電壓(brown_in) 的準位為114V ’而低壓狀態(brown_out)的準位為ιοον，從 圖3可知’電壓VDC為114V時電壓JS約1.2V，電壓VDC 為100V時電壓JS約l.iv，因此當低壓狀態偵測器3〇中的 磁滯比較器32偵測到電壓jS大於uv時，驅動器18可以 正常運作，當磁滯比較器32偵測到電壓JS小於1.iv時，將 φ 觸舍低壓保護信號BNO去關閉驅動器18。同樣的，過壓保 漢偵測為34也可以藉由偵測電壓js來判斷電壓vdc是否過 高。假設過電壓的準位設定為400V，由圖3可知，當電壓 VDC為400V時電壓JS約為4.4V，因此當過壓保護偵測器 34中的磁滯比較器36偵測到電壓JS大於4.4V時，將觸發過 壓保護信號OVP去關閉驅動電路18。 在本實施例中雖然只以低壓狀態保護及過壓保護為例， 但藉由偵測JFET24的汲極電壓JS來達成其他保護也是可以 的’例如過載保護補償。在本實施例中控制器晶片2〇利用高 201112595 壓接腳HV監視直流電壓VDC .來達成保護，在其他實施例中 也可以藉由監視交流電壓VAC或功率開關Q1的汲極電壓來 達成保護。 【圖式簡單說明】 圖1係習知的交流對直流電源轉換器； 圖2係本發明的實施例；以及 圖3係JFET的汲極電壓與臨界電壓之間的特性曲線。 【主要元件符號說明】 10 控制器晶片 12 低壓狀態彳貞測器 14 磁滞比較器 16 高壓啟動元件 18 驅動器 20 控制器晶片 22 高壓啟動元件 24 JFET 26 偵測器 28 保護電路 30 低壓狀態偵測器 32 磁滞比較器 34 過壓保護偵測器 36 磁滞比較器 201112595Transistor; JFET) as a high voltage starting component, the jpet has a drain connected to the high voltage pin, the diode has an anode connected to the source of the JFET and a cathode connected to the gate of the JFET transistor and the power pin, the circuit connection The JFET's miscellaneous 'monitoring the hybrid voltage to the mosquito, and the voltage at which the device is connected to the electrical foot's power supply pin determines the side signal for switching the JFET. According to the present invention, the method of converting H is included in the power supply selection process: when the power supply capacity is (4) when the pressure is reached to the boundary value, and in the lungs, the drum is used. The pole voltage determines the protection signal. Since the controller chip is used to realize the circuit name function from the original pressure-starting component of the _Guang, At, it is not necessary to increase the smashing smash. „I 制 曰 的 的 及 及 外部 外部 电源 电源 电源 电源 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器In the wafer 2, the crucible 24 as the armor starting element 22 has a drain connection high voltage pin HV, the pole body Dh has a source connected to the anode of the jpET 24, and the cathode is connected to the gate of the IFET 24 via a current limiting resistor. The cathode of the body Dh is also connected to the power pin VDD, the switch ST is connected between the gate of the JFET 24 and the ground GND, and the detector 26 detects the voltage of the power pin VDD and determines the detection signal S1 for switching. Switch ST, protection circuit 28 monitors the source voltage JS of JFET 24 to determine the protection signal. Protection circuit 28 includes low voltage state detector 30 and overvoltage guard detector 34. Low voltage state detector 3〇 has hysteresis comparison The device 32 compares the voltage JS with the low voltage threshold vref1 to determine the low voltage protection signal BN〇 for activating or deactivating the driver 18. The overvoltage protection detector 34 has a hysteresis comparator 36 comparing the voltage JS and the overvoltage threshold Vref2. Overvoltage protection letter 〇Vp is given to driver 18. Since the characteristics of JFET 24 are modulated, its threshold voltage Vth is closely related to its gate voltage VDC, and Figure 3 is a characteristic curve between the two. Referring to Figures 2 and 3, When the power is turned on, the voltage of the gate and the source of the AC voltage VAC just supplied to the power converter 'JFET 24 is equal or nearly equal, so the JFET 24 is turned on, and the current is passed through the JFET 24, the diode Dh, and the power pin. VDD charges the power capacitor C1. The detector 26 detects the voltage VDD on the power capacitor C1. For example, the comparator 38 compares the voltage vDD with the threshold UVLO. When the voltage VDD reaches the UVLO, the detector 26 triggers the detection signal. No. 81 and open (>1111〇11) switch 8 butyl, so the gate voltage JG of £4 is pulled to 0V, so that the JFET 24 is turned off, that is, the current is no longer turned on, so energy can be saved. Since the voltage 201112595 VDD on the power supply capacitor C1 is sufficient to start the controller chip 20 at this time, the driver 18 is activated to generate the control signal Vgate to switch the power switch Q1, thereby starting the power required by the auxiliary coil Laux to supply the controller chip 20. this The startup of the power converter is completed. After the power converter is started, the gate voltage JG of the JFET 24 is 0V, and the voltage of the power pin VDD is greater than the threshold value UVL〇, so the source voltage JS of the jpET24 will be locked in the jpet 24 The threshold voltage Vth is as shown in Fig. 3. ^ When the DC voltage VDC changes, the threshold voltage Vth of the JFET 24 will also change, so the low voltage state detector 30 can determine the DC voltage vdc by detecting the source voltage JS of the JFET 24. Is it too low? Assume that the starting voltage (brown_in) is at a level of 114V' and the low-voltage state (brown_out) is at a level of ιοον. From Fig. 3, the voltage JS is about 1.2V when the voltage VDC is 114V, and the voltage JS is about l when the voltage VDC is 100V. Iv, therefore, when the hysteresis comparator 32 in the low-voltage state detector 3〇 detects that the voltage jS is greater than uv, the driver 18 can operate normally. When the hysteresis comparator 32 detects that the voltage JS is less than 1.iv, The φ is connected to the low voltage protection signal BNO to turn off the driver 18. Similarly, the overvoltage protection detection 34 can also determine whether the voltage vdc is too high by detecting the voltage js. Assuming that the level of the overvoltage is set to 400V, as can be seen from FIG. 3, the voltage JS is about 4.4V when the voltage VDC is 400V, so when the hysteresis comparator 36 in the overvoltage protection detector 34 detects that the voltage JS is greater than At 4.4V, the overvoltage protection signal OVP will be triggered to turn off the driver circuit 18. In the present embodiment, although only the low voltage state protection and the overvoltage protection are taken as an example, it is also possible to achieve other protection by detecting the gate voltage JS of the JFET 24, for example, overload protection compensation. In this embodiment, the controller chip 2 监视 monitors the DC voltage VDC by using the high 201112595 crimping pin HV to achieve protection. In other embodiments, the protection can be achieved by monitoring the AC voltage VAC or the drain voltage of the power switch Q1. . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conventional AC-to-DC power converter; FIG. 2 is an embodiment of the present invention; and FIG. 3 is a characteristic curve between a gate voltage and a threshold voltage of a JFET. [Main component symbol description] 10 Controller chip 12 Low voltage state detector 14 Hysteresis comparator 16 High voltage starting element 18 Driver 20 Controller chip 22 High voltage starting element 24 JFET 26 Detector 28 Protection circuit 30 Low voltage state detection 32 hysteresis comparator 34 overvoltage protection detector 36 hysteresis comparator 201112595