CN109450417A - A kind of starting overshoot suppression circuit for LDO - Google Patents
A kind of starting overshoot suppression circuit for LDO Download PDFInfo
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- CN109450417A CN109450417A CN201811122403.8A CN201811122403A CN109450417A CN 109450417 A CN109450417 A CN 109450417A CN 201811122403 A CN201811122403 A CN 201811122403A CN 109450417 A CN109450417 A CN 109450417A
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- ldo
- voltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a kind of starting overshoot suppression circuits for LDO, including one first overshoot suppression circuit, are connected between the power end and output end of the error amplifier of LDO；First overshoot suppression circuit includes concatenated first switch control unit and voltage clamping unit, and the enable signal of the first switch control unit is negated by the enable signal of LDO and postponed for the first predetermined time and obtained, within the first predetermined time that LDO starts, the grid voltage of the power tube of LDO is clamped to a first predetermined value by the voltage clamping unit, and the gate source voltage of the power tube is maintained into a second predetermined value, it is limited so that the LDO is exported to the electric current of load.The inhibition of overshoot voltage when the present invention realizes LDO starting with simpler circuit design, smaller circuit area and ultralow circuit power consumption, to realize lesser starting overshoot.
Description
Technical field
The present invention relates to technical field of power management, in particular to the electricity of a kind of inhibition starting overshoot voltage for LDO
Road.
Background technique
It is growing with consumer electronics product, such as smart phone, tablet computer, laptop etc. be portable
Electronic product has become a part indispensable in people's daily life, and the strong growth of the said goods is but also mixing
Integrated circuit and SOC (System on chip, system level chip) are rapidly developed, and often need multiple low pressure in a chip
Difference linear constant voltage regulator (referred to as " LDO ") power supply, to meet the low-power consumption requirement of digital circuit.
The circuit lifetime under LDO voltage of working will receive the alive influence of institute, excessive overshoot in LDO start-up course
Voltage can seriously affect the service life of digital circuit, in some instances it may even be possible to cause the breakdown of device, therefore inhibit overshoot electricity when LDO starting
Pressure is particularly important.The mode of traditional inhibition LDO starting overshoot can be by additional proprietary circuit come during controlling starting
Peak current, and then inhibit output voltage overshoot.For example, the patent document in Publication No. CN105408829A " is used for
The slow turn-on of ldo regulator " in, provide a high bandwidth access in parallel with high-gain path, including comparator, delay list
Member and switching device, for the high bandwidth access dedicated for inhibiting starting overshoot, principle is by monitoring output voltage and to feed back
The size of current of control flow direction load achievees the purpose that control starting overshoot.However, additional proprietary circuit undoubtedly increases electricity
Road surface product and circuit power consumption, can not be applicable in the design requirement of the nowadays low-power consumption of most of electronic products and small area.
The disclosure of background above technology contents is only used for auxiliary and understands inventive concept and technical solution of the invention, not
The prior art for necessarily belonging to present patent application shows above content in the applying date of present patent application in no tangible proof
Before have disclosed in the case where, above-mentioned background technique should not be taken to evaluation the application novelty and creativeness.
Summary of the invention
It is a primary object of the present invention to overcome the deficiencies in the prior art, propose that a kind of starting overshoot for LDO inhibits
Circuit, overshoot voltage when realizing LDO starting with simpler circuit design, smaller circuit area and ultralow circuit power consumption
Inhibit, to realize lesser starting overshoot.
The present invention proposes following technical scheme for the above-mentioned purpose:
A kind of starting overshoot suppression circuit for LDO, including one first overshoot suppression circuit, are connected to the error of LDO
Between the power end and output end of amplifier；First overshoot suppression circuit includes concatenated first switch control unit and electricity
Pressing tongs bit location, and the enable signal of the first switch control unit is negated by the enable signal of LDO and postpones first and made a reservation for
Time obtains, within the first predetermined time that LDO starts, by the voltage clamping unit by the grid of the power tube of LDO
Voltage clamping maintains a second predetermined value to a first predetermined value, and by the gate source voltage of the power tube, so that described
LDO is exported to the electric current of load and is limited.
The above-mentioned starting overshoot suppression circuit for LDO provided by the invention, can borrow LDO's in LDO start-up course
The electric current for the postpones signal control power supply flow direction load that clock generates, may not need special peripheral circuit, with lesser circuit
Area realizes the inhibition of starting overshoot.
Further, the starting overshoot suppression circuit further includes the second overshoot inhibition electricity for being connected to LDO output end
Road, second overshoot suppression circuit include load current detection unit, current-voltage converting unit and voltage comparison unit；
The load current detection unit is connected to the power tube of the LDO, big by the electric current of LDO flow direction load for real-time monitoring
It is small；The current-voltage converting unit is series at the load current detection unit, is used for the load current detection unit
The electric current of acquisition is converted to voltage；The input terminal of the voltage comparison unit is connected to the current-voltage converting unit, output
End is connected to the output end of error amplifier in LDO, for according to the output voltage of the current-voltage converting unit come by institute
The output end pull-up for stating error amplifier, is exported with limiting the power tube to the size of current of load.The starting of this programme
Suppression circuit is rushed, starting can preferably be inhibited to overshoot.
In short, starting overshoot suppression circuit provided by the invention, the clock that in LDO start-up course, can borrow LDO is generated
Postpones signal directly control LDO power tube grid voltage, and then control the size of current of flow direction load, while can also close
Reason avoids peak current flow direction load in start-up course using the current foldback circuit in linear voltage regulator.
Detailed description of the invention
Fig. 1 is the circuit diagram of traditional low pressure difference linear voltage regulator；
Fig. 2 is the circuit diagram that the starting overshoot suppression circuit that a specific embodiment of the invention provides is used for tradition LDO；
Fig. 3 is the circuit diagram that the starting overshoot suppression circuit that one embodiment of the present invention provides is used for tradition LDO；
Fig. 4 is circuit working timing figure as shown in Figure 3；
Fig. 5 is the circuit that the starting overshoot suppression circuit for providing another preferred embodiment of the present invention is used for traditional LDO
Schematic diagram.
Specific embodiment
The invention will be further described with specific embodiment with reference to the accompanying drawing.
Traditional low pressure difference linear voltage regulator (aftermentioned title " LDO ") as shown in Figure 1, mainly include error amplifier EA and
The power tube M1 of final stage output is served as in amplifying circuit.Wherein, the source electrode of power tube M1 connects two concatenated power resistor Rf1
And Rf2, source electrode is simultaneously also by a capacity earth, since traditional LDO and its circuit connection composition belong to the prior art, herein
It repeats no more.
The present invention is to overcome the defect of existing LDO starting overshoot Restrain measurement, proposes that a kind of circuit area is small, low function
The starting overshoot suppression circuit of consumption, as shown in Fig. 2, the starting for LDO that the specific embodiment of the invention proposes overshoots and inhibits
Circuit includes one first overshoot suppression circuit 100, which is connected to the error amplifier EA's of LDO
Between power end (meeting power vd D) and output end ea_out, and including concatenated first switch control unit and voltage clamping list
Member, and the enable signal of the first switch control unit is negated by the enable signal of LDO and postponed for the first predetermined time and obtained,
With within the first predetermined time that LDO starts, by the voltage clamping unit by the grid voltage clamper of the power tube M1 of LDO
A second predetermined value is maintained to a first predetermined value, and by the gate source voltage (VGS) of the power tube M1, so that described
LDO is exported to the electric current of load and is limited.
Wherein, when the first predetermined time t0 > 0 and t0 are that the starting of the LDO according to required by LDO application system is established
Between set, the t0 the big, and the then present invention is better to the inhibitory effect of LDO starting overshoot.LDO is usually to give SOC (system level chip)
Internal supplying digital circuits, therefore, the application system of LDO is to refer to the application environment of LDO, such as system level chip herein,
The settling time of LDO needs system to be defined from whole timing, and t0 is bigger in system allowed band, overshoots inhibitory effect
Better.
Within the LDO starting t0 time: the first switch control unit is on-state, thus by the voltage clamping list
In member access LDO, inhibited with carrying out starting overshoot, during this period of time, the grid voltage of the power tube M1 is by the voltage
Clamping unit is clamped to first predetermined value VDD-VD1, so that the VGS of power tube M1 maintains second predetermined value VD1, and then can be with
The power tube M1 is limited to export to the size of current of load.Wherein, VDD is the supply voltage of the error amplifier EA, VD1
For the conduction voltage drop of the voltage clamping unit.And after LDO starts the t0 time, the first switch control unit disconnects,
The power tube M1 starts to provide normal electric current to load.
In one embodiment, the first switch control unit includes a first switch tube SW1, the voltage clamping
Unit includes an one way conducting device, and the conducting direction of the one way conducting device is referred to by the power end of the error amplifier EA
To output end (ea_out).In a more preferred embodiment, the first switch control unit is a switching tube SW1, institute
Stating voltage clamping unit is a diode D1, the anode of diode D1 be connected to the error amplifier EA power end,
Cathode is connected to the output end ea_out of error amplifier EA.In further embodiments, diode D1 can also use PMOS tube
Or NMOS tube substitution.
It defines LDO, switching tube SW1 to be connected when signal is ' 1 ', be turned off when being ' 0 '.Such as Fig. 4, show of the invention
The working sequence for starting overshoot suppression circuit, when the enable signal S1 of switching tube SW1 is negated by the enable signal of LDO and postponed t0
Between obtain.When the enable signal EN of LDO becomes ' 1 ' (i.e. LDO starting) by ' 0 ', become via the electric current Iin moment that vdd terminal exports
Greatly, then after delay time t0, the enable signal S1 of switching tube SW1 can become ' 0 ' by ' 1 '.And within the t0 time of LDO starting: function
The grid voltage of rate pipe M1 is clamped to VDD-VD1 by the voltage clamping unit, thus VGS (gate source voltage) quilt of power tube M1
The conduction voltage drop VD1 of diode D1 is maintained, so, so that it may limit power tube M1 and export to the electric current of load, guarantee
Load will not be impacted by instantaneous large-current and generate overshoot voltage.And after LDO starts the t0 time, switching tube SW1's makes
Energy signal S1 can become ' 0 ' by ' 1 ', and switching tube SW1 is disconnected, and the first overshoot suppression circuit 100 disconnects, and power tube M1 starts to provide surely
Fixed operating current is to load.From fig. 4 it can be seen that the voltage Vout of load is steady since when LDO starts within the t0 time
Surely increase, after the t0 time, the first overshoot suppression circuit 100 is disconnected, and Vout is steady state value, starting overshoot electricity does not occur
Pressure.Illustrate that the starting overshoot inhibitory effect of this embodiment of the invention is good.
As shown in Figure 3 and Figure 5, a specific embodiment of the invention additionally provides preferred starting overshoot suppression circuit,
Compared to technical solution exemplified by earlier figures 2, starting overshoot suppression circuit exemplified by Fig. 3 and Fig. 5 increases that be connected to LDO defeated
Second overshoot suppression circuit 200 of outlet.
As shown in Figure 3 and Figure 5, second overshoot suppression circuit 200 includes load current detection unit 201/201 ', electricity
Stream-voltage conversion unit 202 and voltage comparison unit 203；Wherein, the load current detection unit 201/201 ' is connected to institute
The power tube M1 for stating LDO, for real-time monitoring by the size of current of LDO flow direction load；The current-voltage converting unit 202
It is series at the load current detection unit 201/201 ', the electricity for acquiring the load current detection unit 201/201 '
Circulation is changed to voltage；The input terminal of the voltage comparison unit 203 is connected to the current-voltage converting unit 202, output end
It is connected to the output end ea_out of error amplifier EA in LDO, for the output according to the current-voltage converting unit 202
Voltage pulls up the output end of the error amplifier, is exported with limiting the power tube M1 to the size of current of load.
In the particular embodiment, as shown in Figure 3 and Figure 5, the current-voltage converting unit 202 includes being connected to institute
State the first resistor R1 between load current detection unit 201/201 ' and the voltage comparison unit 203.First resistor R1
The electric current that the load current detection unit 201 detects can be converted to voltage, for used in subsequent voltage comparing unit 203.
In a specific implementation, as shown in figure 3, the load current detection unit 201 includes one second power transistor
The grid of M2, the second power transistor M2 are connected to the output end ea_out of the error amplifier EA, drain electrode is connected to
The current-voltage converting unit 202 and source electrode are connected to the source electrode of the power tube M1.The second power transistor M2 makees
For the mirror image pipe of power tube M1, in LDO start-up course, once power tube M1 flows through high current, second power transistor
M2 flows through the high current of corresponding proportion, realizes the monitoring of load current, especially to monitor the spike in LDO start-up course
Electric current.
As shown in figure 5, in another specific embodiment, the load current detection unit 201 ' not only includes the second function
Rate transistor M2, further includes the sixth power transistor M6 in parallel with M2, also, the grid of M6 passes through a switching tube SW ' and the
The grid of two power transistor M2 connects, and the source electrode of the second power transistor M2 and the 6th power transistor M6 are commonly connected to function
The drain electrode of the source electrode of rate pipe M1, the second power transistor M2 and the 6th power transistor M6 is commonly connected to the current-voltage
Converting unit 202；Also, the switching tube SW ' within the first predetermined time that LDO starts in an ON state so that described
Second power transistor M2 and the 6th power transistor M6 parallel connection form the load current detection unit 201 '.
As shown in Figure 3 and Figure 5, the voltage comparison unit 203 includes third to the 5th power transistor M3~M5, first
Current source I1 and the second current source I2；The grid of the grid of third power transistor M3, source electrode and the 4th power transistor M4
It is commonly connected to the first current source I1, first current source I1 other end ground connection；The source electrode and the 5th function of 4th power transistor M4
The grid of rate transistor M5 is commonly connected to the second current source I2, second current source I2 other end ground connection；Third power transistor
The drain electrode of M3 is connected to the first end of the current-voltage converting unit 202, the drain electrode of the 4th power transistor M4 and the 5th function
The drain electrode of rate transistor M5 is commonly connected to the second end of the current-voltage converting unit 202, wherein the current-voltage
The first end of converting unit 202 is the one end connecting with the load current detection unit 201；5th power transistor M5
Source electrode be connected to the output end ea_out of the error amplifier.Within the first predetermined time of LDO starting, work as load current
When detection unit 201/201 ' detects the electric current greater than preset threshold, the source voltage of the third power transistor M3 declines
Pressure difference the amplification of single-stage common source is carried out by the third power transistor M3 and the 4th power transistor M4, after amplification
Signal reach the grid of the 5th power transistor M5, trigger the 5th power transistor M5 conducting, pass through described the
The source electrode of five power transistor M5 pulls up the output end of the error amplifier, with limit the power tube M1 export to
The electric current of load.In preferred scheme, the second to the 4th power transistor is PMOS tube, and the 5th power transistor is NMOS
Pipe.
In a more preferred embodiment, as shown in figure 3, the starting overshoot suppression circuit further includes one and the electric current-
The overcurrent protection branch in parallel of voltage conversion unit 202, the overcurrent protection branch are led after LDO started for the first predetermined time
It is logical, the overcurrent protection of realizing LDO in parallel with the current-voltage converting unit 202.Further, the overcurrent protection branch
Start institute in LDO including concatenated second resistance R2 and second switch control unit SW2, the second switch control unit SW2
It states and connects after the first predetermined time, to control the overcurrent protection branch conducting, so that resistance R1 and R2 parallel connection is realized
The overcurrent protection function of LDO.Second switch control unit SW2 is preferably a switching tube.
In another preferred embodiment, as shown in figure 5, the starting overshoot suppression circuit further includes third switch
Control unit SW3, SW3 be connected to the current-voltage converting unit 202 second end and the 6th power transistor M6
It between grid, and is connected after LDO started for the first predetermined time, the grid of the 6th power transistor M6 is drawn
Height turns off the 6th power transistor M6, and then it is single to convert the second power transistor M2 and the current-voltage
The overcurrent protection in parallel for realizing LDO of member 202.Third switch control unit SW3 is preferably a switching tube.
The principle explanation that starting overshoot inhibits is carried out to embodiment as shown in Figure 3 and Figure 5 separately below.Wherein, it defines
LDO enable signal EN be " 1 " Shi Qidong, be " 0 " when close, equally, also define SW2, SW3 and SW ' be signal be " 1 "
When connect, be " 0 " when disconnect.
With reference to Fig. 3 and Fig. 4, when the enable signal EN of LDO becomes ' 1 ' (i.e. LDO starting) by ' 0 ', via vdd terminal (error
The working power end of amplifier) output electric current Iin moment become larger, LDO starting the t0 period in (the i.e. enabled letter of LDO
Number EN become 1 from 0 after the t0 period in): the enable signal S2 with the concatenated SW2 of resistance R2 is still that 0, SW2 is disconnected, when the
When electric current I detected by two power transistor M2 increases, the pressure drop on resistance R1 also increases, the third power transistor M3
Source voltage (source voltage=VDD-I*R1) decline, the pressure difference △ V of decline passes through third power transistor M3 and the 4th function
Rate transistor M4 carries out the amplification of single-stage common source, and amplified signal reaches the grid of the 5th power transistor M5, described in triggering
5th power transistor M5 conducting, pulls up the output end ea_out of the error amplifier by the source electrode of M5, and then limits
The power tube M1 is made to export to the electric current of load.Wherein it is possible to which it is pre- to set electric current when starting according to specific application environment
If threshold value, once the electric current that M2 is detected is greater than the preset threshold, then the pressure difference that the source voltage terminal of power transistor M3 declines
Amplified signal can trigger power transistor M5 conducting.And after LDO starts the t0 time, (i.e. the enable signal EN of LDO is become by 0
For 1 and after have passed through the t0 time): the enable signal S2 of SW2 becomes 1, SW2 and connects, branch conducting where second resistance R2, with the
The overcurrent protection function of one resistance R1 parallel connection realization LDO.From fig. 4, it can be seen that in the settling time t0 after the starting of LDO,
The voltage Vout of load steadily increases since when LDO starts, and after the t0 time, Vout is steady state value, is not opened
Dynamic overshoot voltage.Illustrate that the starting overshoot inhibitory effect of this embodiment of the invention is good.
As shown in figure 5, the enable signal for the pipe SW ' that opens the light is negated by the enable signal of LDO and postpones t0 for the embodiment
Time obtains, and the enable signal of SW3 is the inversion signal of the enable signal of SW '.Become 1 (i.e. LDO from 0 in the enable signal of LDO
Starting) and after the t0 time, the enable signal of SW ' can become 0 from 1, therefore, within the t0 period of LDO starting: switch
The signal of pipe SW ' is 1, and in an ON state, and third switch control unit SW3 is disconnected, and power transistor M2 and M6 makees at this time
The monitoring that load current is carried out for load current sensing device, when the electric current for monitoring flow direction load increases, the third function
The source voltage of rate transistor M3 declines, especially when M2 and M6 detect that electric current is more than preset threshold, the decline of M3 source electrode
Pressure difference is by reaching the 5th power crystal after the third power transistor M3 and the 4th power transistor M4 amplification
The grid of pipe M5 triggers the 5th power transistor M5 conducting, by the source electrode of M5 to the output end of the error amplifier
Ea_out is pulled up, and then is limited the power tube M1 and exported to the size of current of load.After LDO starts the t0 time,
The signal of SW ' becomes 0, SW from 1 ' it disconnects, SW3 is connected, and the grid of the 6th power switch tube M6 is raised, the 6th power switch tube
M6 shutdown, thus the second power transistor M2 overcurrent protection function for realizing LDO in parallel with first resistor R1.
In short, the starting overshoot suppression circuit for LDO of the aforementioned offer of the present invention, the first overshoot suppression circuit 100
The effect of in AW1760 product by verifying, preferably inhibit starting overshoot.At preferred embodiment (Fig. 3 and Fig. 5)
In simultaneously have effects that the first and second overshoot suppression circuits 100 and 200 LDO starting overshoot suppression circuit in AW1788
Pass through PVT simulating, verifying in product, starting overshoot can be by good limitation in a certain range.Reach small area, with low power
Inhibit the purpose of LDO starting overshoot.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those skilled in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, several equivalent substitute or obvious modifications can also be made, and performance or use is identical, all answered
When being considered as belonging to protection scope of the present invention.
Claims (13)
1. a kind of starting overshoot suppression circuit for LDO, it is characterised in that: including one first overshoot suppression circuit (100), even
It is connected between the power end and output end (ea_out) of the error amplifier (EA) of LDO；
First overshoot suppression circuit (100) includes concatenated first switch control unit and voltage clamping unit, and described
The enable signal of first switch control unit is negated by the enable signal of LDO and postponed for the first predetermined time and obtained, to open in LDO
In the first dynamic predetermined time, the grid voltage of the power tube (M1) of LDO is clamped to one by the voltage clamping unit
One predetermined value, and the gate source voltage of the power tube (M1) is maintained into a second predetermined value, so that the LDO is exported to negative
The electric current of load is limited.
2. starting overshoot suppression circuit as described in claim 1, it is characterised in that: first predetermined time is t0, t0 > 0
And settling time is started to set t0 according to LDO required by LDO application system.
3. starting overshoot suppression circuit as described in claim 1, it is characterised in that: the first predetermined value is VDD-VD1,
VDD is the supply voltage of the error amplifier, and VD1 is the conduction voltage drop of the voltage clamping unit；The second predetermined value
For VD1.
4. starting overshoot suppression circuit as described in claim 1, it is characterised in that: the first switch control unit includes one
First switch tube (SW1).
5. starting overshoot suppression circuit as described in claim 1 or 4, it is characterised in that: the voltage clamping unit includes one
The conducting direction of one way conducting device, the one way conducting device is directed toward output end by the power end of the error amplifier (EA)
(ea_out)。
6. starting overshoot suppression circuit as described in claim 1, it is characterised in that: further include be connected to LDO output end the
Two overshoot suppression circuits (200), second overshoot suppression circuit (200) include load current detection unit (201,201 '),
Current-voltage converting unit (202) and voltage comparison unit (203)；
The load current detection unit (201,201 ') is connected to the power tube (M1) of the LDO, for real-time monitoring by LDO
Flow to the size of current of load；The current-voltage converting unit (202) be series at the load current detection unit (201,
201 '), for the electric current that the load current detection unit (201,201 ') acquire to be converted to voltage；The voltage is more single
The input terminal of first (203) is connected to the current-voltage converting unit (202), output end is connected to error amplifier in LDO
(EA) output end (ea_out), for according to the output voltage of the current-voltage converting unit (202) come by the error
The output end of amplifier pulls up, to limit the size of current of the power tube (M1) output to load.
7. starting overshoot suppression circuit as claimed in claim 6, it is characterised in that: the load current detection unit (201)
Including one second power transistor (M2), the grid of second power transistor (M2) is connected to the error amplifier (EA)
Output end (ea_out), drain electrode is connected to the current-voltage converting unit (202) and source electrode is connected to the power tube
(M1) source electrode.
8. starting overshoot suppression circuit as claimed in claim 6, it is characterised in that: the load current detection unit (201 ')
Including the second power transistor (M2) and the 6th power transistor (M6) in parallel, wherein the 6th power transistor (M6)
Grid connect with the grid of second power transistor (M2) by a switching tube (SW '), second power transistor
(M2) and the source electrode of the 6th power transistor (M6) is commonly connected to the source electrode of the power tube (M1), second power
The drain electrode of transistor (M2) and the 6th power transistor (M6) is commonly connected to the current-voltage converting unit (202)；
Also, the switching tube (SW ') within the first predetermined time that LDO starts in an ON state so that second function
Rate transistor (M2) and the 6th power transistor (M6) the formation load current detection unit (201 ') in parallel.
9. starting overshoot suppression circuit as claimed in claim 7 or 8, it is characterised in that: the current-voltage converting unit
It (202) include the be connected between the load current detection unit (201,201 ') and the voltage comparison unit (203)
One resistance (R1).
10. starting overshoot suppression circuit as claimed in claim 9, it is characterised in that: the voltage comparison unit (203) includes
Third is to the 5th power transistor (M3~M5), the first current source (I1) and the second current source (I2)；
The grid of the grid of third power transistor (M3), source electrode and the 4th power transistor (M4) is commonly connected to the first electricity
Stream source (I1), the first current source (I1) other end ground connection；The source electrode and the 5th power transistor of 4th power transistor (M4)
(M5) grid is commonly connected to the second current source (I2), the second current source (I2) other end ground connection；
The drain electrode of third power transistor (M3) is connected to the first end of the current-voltage converting unit (202), the 4th power
The drain electrode of transistor (M4) and the drain electrode of the 5th power transistor (M5) are commonly connected to the current-voltage converting unit
(202) second end, wherein the first end of the current-voltage converting unit (202) is and the load current detection
One end of unit (201) connection；The source electrode of 5th power transistor (M5) is connected to the output end (ea_ of the error amplifier
out)；
Within the first predetermined time of LDO starting, preset when the load current detection unit (201,201 ') detects to be greater than
When the electric current of threshold value, the pressure difference of the source voltage decline of the third power transistor (M3) passes through the third power transistor
(M3) and the 4th power transistor (M4) carries out the amplification of single-stage common source, and it is brilliant that amplified signal reaches the 5th power
The grid of body pipe (M5) triggers the 5th power transistor (M5) conducting, passes through the source of the 5th power transistor (M5)
Extremely the output end of the error amplifier is pulled up, to limit the electric current of the power tube (M1) output to load.
11. starting overshoot suppression circuit as claimed in claim 7, it is characterised in that: further include one and the current-voltage turn
The overcurrent protection branch of unit (202) parallel connection is changed, the overcurrent protection branch is connected after LDO started for the first predetermined time,
The overcurrent protection of realizing LDO in parallel with current-voltage converting unit (202).
12. starting overshoot suppression circuit as claimed in claim 11, it is characterised in that: the overcurrent protection branch includes series connection
Second resistance (R2) and second switch control unit (SW2), the second switch control unit (SW2) LDO start described in
First predetermined time connected later, to control the overcurrent protection branch conducting.
13. starting overshoot suppression circuit as claimed in claim 8, it is characterised in that: further include a third switch control unit
(SW3), the second end of the current-voltage converting unit (202) and the grid of the 6th power transistor (M6) are connected to
Between, and connected after LDO started for the first predetermined time, the grid of the 6th power transistor (M6) is drawn high,
The 6th power transistor (M6) is turned off, and then converts second power transistor (M2) and the current-voltage
Unit (202) overcurrent protection in parallel for realizing LDO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811122403.8A CN109450417B (en) | 2018-09-26 | 2018-09-26 | A start suppression circuit that overshoots for LDO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811122403.8A CN109450417B (en) | 2018-09-26 | 2018-09-26 | A start suppression circuit that overshoots for LDO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109450417A true CN109450417A (en) | 2019-03-08 |
| CN109450417B CN109450417B (en) | 2022-11-18 |
Family
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| CN201811122403.8A Active CN109450417B (en) | 2018-09-26 | 2018-09-26 | A start suppression circuit that overshoots for LDO |
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| CN112398326A (en) * | 2019-08-13 | 2021-02-23 | 国民技术股份有限公司 | Soft start device and method based on multi-output device, power supply and chip |
| CN114415774A (en) * | 2022-01-21 | 2022-04-29 | 南京元络芯科技有限公司 | LDO circuit for solving power-on transition of LDO |
| CN114510112A (en) * | 2022-01-12 | 2022-05-17 | 电子科技大学 | Transient enhancement circuit applied to low-power-consumption fully-integrated low dropout linear regulator |
| CN114546017A (en) * | 2022-04-27 | 2022-05-27 | 南京芯力微电子有限公司 | Undervoltage area current clamping circuit of linear voltage stabilizer and linear voltage stabilizer |
| CN114583676A (en) * | 2022-03-29 | 2022-06-03 | 拓尔微电子股份有限公司 | Circuit and method for reducing output voltage overshoot of LDO (low dropout regulator) |
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|---|---|
| CN109450417B (en) | 2022-11-18 |
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