CN105763061B - Flyback converter output current counting circuit and computational methods - Google Patents

Flyback converter output current counting circuit and computational methods Download PDF

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Publication number
CN105763061B
CN105763061B CN201410790883.0A CN201410790883A CN105763061B CN 105763061 B CN105763061 B CN 105763061B CN 201410790883 A CN201410790883 A CN 201410790883A CN 105763061 B CN105763061 B CN 105763061B
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voltage
current
output
switch
msub
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CN105763061A (en
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陈佑民
郑荣霈
黄培伦
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Cayman Ltd
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Priority to CN201410790883.0A priority Critical patent/CN105763061B/en
Priority to US14/755,951 priority patent/US9490712B2/en
Publication of CN105763061A publication Critical patent/CN105763061A/en
Priority to US15/343,091 priority patent/US9954449B2/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/10—Measuring sum, difference or ratio
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/145—Indicating the presence of current or voltage
    • G01R19/15—Indicating the presence of current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention mainly relates to the output current counting circuits for flyback converter, can calculate output current on the premise of continuous current mode CCM and discontinuous conduct mode DCM is compatible.First detect cut-off current value and blanking current value, read group total is carried out to cut-off current value and blanking current value, obtained summation electric current is exported according to default proportionate relationship, nationality judges that output stage received a preset time period of summation electric current in one cycle accounts for cycle ratio by a logic control element, and logic control element controls the preset time period of output stage in each cycle to receive summation electric current but remaining time section of the output stage in each cycle in addition to the preset time period is forbidden to receive summation electric current.

Description

Flyback converter output current counting circuit and computational methods
Technical field
The invention mainly relates to power conversion systems, are in the voltage flyback conversion applied to field of power supplies exactly Output current is detected and calculated in device, obtains more accurately output current value.
Background technology
In conventional power conversion system, it will usually using the Switching Power Supply mode for carrying out constant pressure or current constant control. Turning on or off for switch element is controlled in power conversion system on the armature winding of transformer, on the armature winding of transformer The electric current of the switch element flowed through is periodically generated, and the energy transmission of primary side is produced on the secondary winding to primary side Raw alternating current changes into direct current supply load after the rectifying and wave-filterings such as injection diode and capacitor.
But it is a severe problem to be solved that how accurately pre- calculating, which is supplied to the output current of load, because this is me Accurately one of principal element of design topology, especially can be in continuous current mode CCM and discontinuous conduct mode DCM all On the premise of compatibility, it is even more that the prior art is difficult to reach problem to calculate output current.
The content of the invention
In one embodiment, present invention is disclosed a kind of output current counting circuit for flyback converter, including： One detecting module, detection flow through the primary current on an inductive reactance with primary windings connected in series, and first for controlling The moment that the main switch that grade winding is switched on or switched off is turned off by a control signal, detect the shut-off for flowing through inductive reactance Current value IOFFAnd terminate for shielding the effective status of a lead-edge-blanking signal of primary current starting spike Moment, detect the blanking current value I for flowing through inductive reactanceLEB；One sampling keeps latch, has storage shut-off respectively Current value IOFFInformation and blanking current value ILEBFirst, second storage capacitance of information；One electric current sum unit, to shut-off electricity Flow valuve IOFFWith blanking current value ILEBCarry out read group total；One output stage, by cut-off current value IOFFWith blanking current value ILEB The voltage that obtained summation electric current is converted into of summing exports within each cycle according to a default proportionate relationship in cycle, Take this pre- calculating output current；One logic control element in arbitrary a cycle, determines that output stage is received by summation electric current One preset time period of the voltage of conversion accounts for cycle ratio, and the preset time period of output stage in each cycle is allowed to receive and is asked The voltage converted with electric current, but remaining time section of the output stage in each cycle in addition to the preset time period is forbidden to receive and is asked With the voltage of electric current conversion.
Above-mentioned counting circuit, detecting module tool gather to characterize primary current there are one first voltage current converter Size across the voltage sense signal on inductive reactance, and voltage sense signal is converted into flowing through and is connected to first voltage electricity The intermediate current of a transfer resistance between the current output terminal and ground terminal of stream transformer；Main switch shut-off moment, Detecting module by the moment be applied to voltage conversion on transfer resistance into cut-off current value IOFFCorresponding voltage sense signal VCS-OFFIt is conveyed to sampling and keeps latch storage；The moment that the effective status of blanking signal terminates ahead of the curve, detecting module should Moment be applied to voltage conversion on transfer resistance into blanking current value ILEBCorresponding voltage sense signal VCS-LEBIt is conveyed to Sampling keeps latch storage.
Above-mentioned counting circuit, detecting module include first voltage follower, and positive input terminal is connected to first voltage electric current The current output terminal of converter；The one of the first storage capacitance of latch is kept in the output terminal of first voltage follower and sampling The first switch of suspension control signal driving is connected between end, being turned into the second state from first state in control signal opens master The moment of shut-off, first switch are synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is by first voltage Follower is converted into and cut-off current value IOFFCorresponding voltage sense signal VCS-OFFIt is stored in the first storage capacitance.
Above-mentioned counting circuit, detecting module include second voltage follower, and positive input terminal is connected to first voltage electric current The current output terminal of converter；The one of the second storage capacitance of latch is kept in the output terminal of second voltage follower and sampling The second switch driven by lead-edge-blanking signal is connected between end, blanking signal is turned into the second shape from first state ahead of the curve The moment of state, second switch are synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is followed by second voltage Device is converted into and blanking current value ILEBCorresponding voltage sense signal VCS-LEBIt is stored in the second storage capacitance.
Above-mentioned counting circuit, the input terminal for the second voltage current converter that electric current sum unit has are connected to first and deposit It, will be with cut-off current value I on storing up electricity is heldOFFCorresponding voltage sense signal VCS-OFFThe charging of first storage capacitance is embodied Voltage value recovery be converted into from the outflow of the current output terminal of second voltage current converter and cut-off current value IOFFEquivalent Electric current；The input terminal for the tertiary voltage current converter that electric current sum unit has is connected in the second storage capacitance, will be with disappearing Hidden current value ILEBCorresponding voltage sense signal VCS-LEBThe embodied voltage value that charges to the second storage capacitance recovers to turn It changes into from the current output terminal outflow of tertiary voltage current converter and blanking current value ILEBEquivalent electric current；Second, third The common node at the current output terminal interconnection of the rwo is flowed through after the electric current merging that voltage current adapter each exports with connecing A summation resistance between ground terminal, summation resistance have resistance value RSUM, a tertiary voltage that electric current sum unit has with It is connected to the positive input terminal of device at the common node so that the voltage V of tertiary voltage follower outputTRSEqual to RSUM×(ILEB +IOFF)。
Above-mentioned counting circuit, output stage include one the 3rd switch, wherein the input terminal of the 3rd switch receives electric current summation What unit was calculated and exported is equal to R by what summation electric current was converted intoSUM×(ILEB+IOFF) voltage VTRS, and the 3rd switch Output terminal is then grounded；It is equal to the shut-off period T of main switch in each switch periods in preset time periodOFFStage switchs the 3rd It disconnects, by voltage VTRSThe output terminal of output stage is transferred to, but the 3rd switch is connect within each switch periods remaining time It passes to voltage VTRSGround terminal is discharged into thereby to forbid output stage receiving voltage VTRS。
Above-mentioned counting circuit, when flyback converter enters electric current continuous CCM patterns, section T when offOFFBy the 3rd switch It disconnects with by voltage VTRSThe output terminal of output stage is transferred to, but is connecting period TONMake the 3rd switch connection that output stage be forbidden to connect Receive voltage VTRS, the voltage I of output stage outputFVFMeet following functional relation：
Above-mentioned counting circuit, when flyback converter enters DCM patterns, section T when offOFF3rd switch is disconnected inciting somebody to action Voltage VTRSThe output terminal of output stage is transferred to, but is connecting period TONWith dead time TDThe 3rd switch connection is made to forbid exporting Grade receiving voltage VTRS, the voltage V of output stage outputFMeet following functional relation：
Above-mentioned counting circuit, if the number of turn N of armature windingPWith the number of turn N of secondary windingsSThe ratio between be equal to n, then flyback convert Device is transferred to the output current I of loadOMeet following functional relation：
Above-mentioned counting circuit, by be connected to the 3rd switch input terminal and tertiary voltage follower output terminal between one A resistance and a capacitance being connected between the input terminal and ground terminal of the 3rd switch form a sampling hold circuit, by even A resistance being connected between the input terminal of the 3rd switch and the output port of output stage and it is connected to the output port of output stage A capacitance between ground terminal forms a filter circuit.
Above-mentioned counting circuit, logic control element include the 4th voltage follower, and positive input terminal is connected to main switch Drain electrode end and including a capacitance, between one end of capacitance and the output terminal of the 4th voltage follower connection there are one resistance, and The other end of capacitance is connected to ground terminal；Logic control element is also connected to capacitance unearthed one comprising a normal phase input end The comparator at end, the inverting input of comparator are connected to the anode for the voltage source for providing reference voltage, and the cathode of voltage source connects It is connected to the output terminal of the 4th voltage follower, the output terminal of comparator is connected in logic control element putting for rest-set flip-flop Position end S；As the comparative result S of comparator outputCOMFor the output of rest-set flip-flop is set to high level, Yi Ji during high level The other relatively narrow high level pulse of a nanosecond that triggering generates at the time of the trailing edge of control signal is coupled to rest-set flip-flop Reset terminal, which resets to low level by the output of rest-set flip-flop, and drives the 3rd by the output terminal of rest-set flip-flop Switch-off or connection.
Above-mentioned counting circuit, in ccm mode, in conducting period TONThe rest-set flip-flop exports high level to the 3rd switch Control terminal, connect the 3rd switch；And section T when offOFFThe rest-set flip-flop exports a low level to the 3rd switch Control terminal, the 3rd switch of shut-off；Output stage is in each cycle by voltage VTRSWith { TOFF÷(TON+TOFF) preset ratio output.
Above-mentioned counting circuit, in dcm mode, in conducting period TONWith dead zone period TDThe high electricity of rest-set flip-flop output It puts down to the control terminal of the 3rd switch, connects the 3rd switch；And section T when offOFFThe rest-set flip-flop exports a low level To the control terminal of the 3rd switch, the 3rd switch of shut-off；Output stage is in each cycle by voltage VTRSWith { TOFF÷(TON+TOFF+TD)} Preset ratio output.
Above-mentioned counting circuit, logic control element include that output terminal is connected to rest-set flip-flop reset terminal with door, with door Phase inverter to make them form monostable flipflops there are one connections between one input terminal and another input terminal；Control signal passes through The inversion signal crossed after another inverter of logic control element is fed to an input terminal with door, inversion signal The input terminal for the phase inverter being connected between two input terminals of door is also fed to, so as in the trailing edge of control signal Time trigger should generate the output signal S of a high level pulse with doorTRILow level is clamped down on into the output of rest-set flip-flop.
Above-mentioned counting circuit, within each cycle, to effective shape of lead-edge-blanking signal at the time of setting main switch is connected Perdurabgility between at the time of state terminates, at the time of overturning preparation shut-off main switch occurs for the logic state equal to control signal Time delay between being crossed to primary current at the time of being flushed to peak-peak.
The present invention provides a kind of methods for the output current for calculating flyback converter, comprise the following steps：Utilize one Detecting module, detection flow through the primary current on an inductive reactance with primary windings connected in series, and for control it is primary around The moment that the main switch that group is switched on or switched off is turned off by a control signal, detect the cut-off current for flowing through inductive reactance Value IOFFAnd for shielding wink for terminating of effective status of a lead-edge-blanking signal of primary current starting spike Between, detect the blanking current value I for flowing through inductive reactanceLEB；A sampling comprising first, second storage capacitance is provided to keep Latch, using first, second storage capacitance correspondence by cut-off current value IOFFInformation and blanking current value ILEBInformation is given respectively With storage, these current informations of storage embody in the form of voltage；Using an electric current sum unit to cut-off current value IOFFWith Blanking current value ILEBCarry out read group total；By cut-off current value IOFFWith blanking current value ILEBSum obtained summation electric current institute The voltage V being converted intoTRS, exported within each cycle according to a default proportionate relationship in cycle in an output stage；Nationality by One logic control element in arbitrary a cycle, judges that output stage receives the voltage V that summation electric current is converted intoTRS A preset time period account for cycle ratio, logic control element controls the preset time period of output stage in each cycle to receive Sum the voltage V that electric current is convertedTRS, but forbid remaining time section of the output stage in each cycle in addition to the preset time period Receive the voltage V of summation electric current conversionTRS。
The above method, detecting module tool gather to characterize primary current size there are one first voltage current converter Across the voltage sense signal on inductive reactance, and voltage sense signal is converted into flowing through and is connected to first voltage electric current and turns The intermediate current of a transfer resistance between the current output terminal and ground terminal of parallel operation；In the moment of main switch shut-off, detecting Module by the moment be applied to voltage conversion on transfer resistance into cut-off current value IOFFCorresponding voltage sense signal VCS-OFFIt is conveyed to sampling and keeps latch storage；The moment that the effective status of blanking signal terminates ahead of the curve, detecting module should Moment be applied to voltage conversion on transfer resistance into blanking current value ILEBCorresponding voltage sense signal VCS-LEBIt is conveyed to Sampling keeps latch storage.
The above method, detecting module include first voltage follower, and positive input terminal is connected to the conversion of first voltage electric current The current output terminal of device；First voltage follower output terminal and sampling keep latch the first storage capacitance one end it Between be connected with the first switch of suspension control signal driving, control signal is turned into the second state from first state and turns off main switch Moment, first switch is synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is by first voltage follower It is converted into and cut-off current value IOFFCorresponding voltage sense signal VCS-OFFIt is stored in the first storage capacitance.
The above method, detecting module include second voltage follower, and positive input terminal is connected to the conversion of first voltage electric current The current output terminal of device；Second voltage follower output terminal and sampling keep latch the second storage capacitance one end it Between be connected with by lead-edge-blanking signal drive second switch, ahead of the curve blanking signal be turned into the second state from first state Moment, second switch are synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is turned by second voltage follower It changes into and blanking current value ILEBCorresponding voltage sense signal VCS-LEBIt is stored in the second storage capacitance.
The above method, the input terminal for the second voltage current converter that electric current sum unit has are connected to the first storage electricity Rong Shang, will be with cut-off current value IOFFCorresponding voltage sense signal VCS-OFFThe charging of first storage capacitance is embodied Voltage value recovery is converted into from the current output terminal outflow of second voltage current converter and cut-off current value IOFFEquivalent electricity Stream；The input terminal for the tertiary voltage current converter that electric current sum unit has is connected in the second storage capacitance, will be with disappearing Hidden current value ILEBCorresponding voltage sense signal VCS-LEBThe embodied voltage value that charges to the second storage capacitance recovers to turn It changes into from the current output terminal outflow of tertiary voltage current converter and blanking current value ILEBEquivalent electric current；Second, third The current remittance collection that voltage current adapter each exports flows through the common node at the current output terminal interconnection of the rwo after merging A summation resistance between ground terminal, summation resistance have resistance value RSUM, have one the 3rd electricity of electric current sum unit The positive input terminal of pressure follower is connected at the common node, the voltage V for exporting tertiary voltage followerTRSEqual to RSUM× (ILEB+IOFF)。
The above method, output stage include one the 3rd switch, and the input terminal of the 3rd switch receives electric current sum unit and calculates With the voltage V converted by summation electric current of outputTRS, the 3rd switch output terminal be then grounded；Each switch periods TSIt is interior to work as in advance If the period is equal to the shut-off period T of main switchOFFStage disconnects the 3rd switch, by voltage VTRSIt is transferred to the defeated of output stage Outlet, but in each switch periods TSMake the 3rd switch connection in the remaining time with by voltage VTRSBe discharged into ground terminal forbid it is defeated Go out a grade receiving voltage VTRS。
The above method, when flyback converter enters electric current continuous CCM patterns, section T when offOFF3rd switch is disconnected With by voltage VTRSThe output terminal of output stage is transferred to, but is connecting period TONMake the 3rd switch connection that output stage be forbidden to receive electricity Press VTRS, the voltage V of output stage outputFMeet following functional relation：
The above method, when flyback converter enters discontinuous current DCM patterns, section T when offOFF3rd switch is disconnected With by voltage VTRSThe output terminal of output stage is transferred to, but is connecting period TONWith dead time TDForbid the 3rd switch connection Output stage receiving voltage VTR, the voltage V of output stage outputFMeet following functional relation：
The above method, if the number of turn N of armature windingPWith the number of turn N of secondary windingsSThe ratio between be equal to n, then calculate flyback conversion Device is transferred to the output current I of loadOMeet following functional relation：
The above method, by an electricity being connected between the input terminal of the 3rd switch and the output terminal of tertiary voltage follower The capacitance for hindering and being connected between the input terminal and ground terminal of the 3rd switch forms a sampling hold circuit, by being connected to 3rd switch input terminal and output stage output port between a resistance and be connected to output stage output port and connect A capacitance between ground terminal forms a filter circuit.
The above method, logic control element include the 4th voltage follower, and the positive input terminal of the 4th voltage follower connects To the drain electrode end of main switch, logic control element bag further includes a capacitance, one end of the capacitance and the 4th voltage follower Connection is there are one resistance between output terminal, and the other end of capacitance is connected to ground terminal；Logic control element is also including one just Phase input terminal is connected to the comparator of unearthed one end of capacitance, and the inverting input of comparator is connected to offer reference voltage Voltage source anode, the cathode of voltage source is connected to the output terminal of the 4th voltage follower, and the output terminal of comparator is connected to The set end of a rest-set flip-flop in logic control element；As the comparative result S of comparator outputCOMFor RS is touched during high level Hair device output be set to high level and at the time of the trailing edge of control signal triggering generate a nanosecond it is other compared with Narrow high level pulse is coupled to the reset terminal of rest-set flip-flop, which resets to the output of rest-set flip-flop low Level, and the 3rd switch-off or connection are drive by the output terminal of rest-set flip-flop.
The above method, in ccm mode, in conducting period TONThe rest-set flip-flop exports control of the high level to the 3rd switch The 3rd switch is connected at end processed；And section T when offOFFThe rest-set flip-flop exports control of the low level to the 3rd switch End, the 3rd switch of shut-off；Output stage is within each cycle by tertiary voltage follower output voltage VTRSWith { TOFF÷(TON+ TOFF) preset ratio output.
The above method, in dcm mode, in conducting period TONWith dead zone period TDThe rest-set flip-flop export high level to The control terminal of 3rd switch connects the 3rd switch；And section T when offOFFThe rest-set flip-flop exports a low level to the The control terminal of three switches, the 3rd switch of shut-off；The voltage V that output stage exports tertiary voltage follower within each cycleTRSWith {TOFF÷(TON+TOFF+TD) preset ratio output.
The above method, logic control element further include that an output terminal is connected to rest-set flip-flop reset terminal with door, with door An input terminal and another input terminal between connection there are one phase inverter to make they form monostable flipflops；Control signal Inversion signal after another inverter is fed to be connected to and door with an input terminal of door and being fed to Two input terminals between phase inverter input terminal, at the time of the trailing edge of control signal triggering should and door generate a height The output of rest-set flip-flop is clamped down on low level by the output signal of level pulse.
The above method, within each cycle, to the effective status knot of lead-edge-blanking signal at the time of setting main switch is connected Perdurabgility between at the time of beam, the logic state equal to control signal occur at the time of overturning prepares to turn off main switch to just Time delay of the grade current over pulse between at the time of peak-peak.
Description of the drawings
Read it is described further below and with reference to the following drawings after, feature and advantage of the invention will be evident：
Fig. 1 illustrates the mnemocircuit figure of the flyback converter of the present invention.
Fig. 2A is the primary current and secondary current waveform that CCM mode control signals driving main switch generates.
Fig. 2 B are the primary current and secondary current waveform that DCM mode control signals driving main switch generates.
Fig. 3 is that the forward position for being momentarily used for shielding sensing signal that main switch is driven to open originates the blanking signal ripple of spike Shape.
Fig. 4 A-4C are CCM mode primaries electric current and the corresponding stepped current waveform of secondary current.
Fig. 5 A-5C are DCM mode primaries electric current and the corresponding triangular current waveform of secondary current.
Fig. 6 is the counting circuit calculated in the flyback converter of the present invention its output current.
Fig. 7 A-7B are the waveforms that rest-set flip-flop corresponds to output under CCM and DCM patterns.
Specific embodiment
Referring to Fig. 1, it is the circuit structure of flyback Flyback electric pressure converters of the present invention, controls primary side Electronics main switch element QM for example can be a power MOSFET, input terminal with such as drain electrode end and with for example The output terminal of source terminal and the control terminal with such as grid.Main switch QM receives main control module 102 in control terminal and sends Control signal and perform the response action that turns on or off accordingly so that connecting or disconnecting for main switch QM can be to flyback The control that the electric current flowed through on the armature winding 130A of the transformer 130 of converter is opened or closed, by the energy of primary side It is transmitted to primary side.Wherein armature winding 130A is for inputted a DC input voitage V of receptionIN, and the input voltage VINIt can be taken by for example mains voltage VACBy the rectifier cells rectification such as such as bridge rectifier.Transformer 130 also has It is useful for transferring out an output voltage VOUTSecondary windings 130B and with for detecting what is generated on secondary windings 130B The auxiliary winding 130C of voltage status, auxiliary winding 130C be identical with the polarity of secondary windings 130B but they and armature winding The polarity of 130A is opposite.One end of auxiliary winding 130C is grounded and the other end is connected to a diode DAUXAnode, wherein two Pole pipe DAUXCathode be connected to a capacitance CAUXOn, so as to after the ac voltage rectifier generated on auxiliary winding 130C to electricity Hold CAUXIt charges for use as accessory power supply, capacitance CAUXThe voltage V of upper storageCCWith output voltage VOUTAssociated and and VOUTHave Directly proportional relation, voltage VCCIt can be individually for main control module 102 and direct voltage source is provided.It is connected on secondary windings 130B There is diode DOWith capacitor COCurrent rectifying and wave filtering circuit, for generating the output voltage V of flyback converterOUT.The output of direct current Voltage VOUTIt is applied to load RLOn, and formed and flow through load RLOutput current IOUT.In the feedback network of converter, master opens Closing connection between the source terminal of QM and ground terminal GND, there are one inductive reactance RS, inductive reactance RSFor sense and detect it is primary around The primary current I flowed through on group 130AP, and provide and be equal to inductive reactance RSResistance value be multiplied by electric current IPFeedback voltage, that is, saving Sensing signal V is provided at point 101CS, primary current IPIt can be used as the secondary electrical that characterization flows through secondary windings 130B after conversion Flow IS, the functional relation between them will be discussed in detail hereinafter.The sensor port CS of main control module 102 is then by inductive reactance RS To detect the primary current I of armature winding 130APSize adjusts main switch QM as judging whether to need to adjust control signal The foundation of on or off.Those skilled in the art is more known to the topological sum operating mode of flyback converter, can dispense It will not go into details for circuit part and specific function mode.
CCM (Continuous Conduction Mode) pattern is continuously turned on referring to the electric current of Fig. 2A, main switch QM exists Such as carry out switching under the driving of the similar control signal such as pulse width modulating signal PWM.Fig. 2A, which is depicted, to be flowed through The primary current I of armature winding 130AP1With the secondary current I for flowing through secondary windings 130BS1Substantially waveform, also substantially show The pressure difference V of the drain-source interpolar of main switch QMDS1Waveform.In the conducting period T of main switch QMON, primary current IP1There is forward position rank Ladder and ramped up since forward position, in the shut-off period T of main switch QMOFF, secondary current IS1To be superimposed the three of attenuation on ladder Angle ripple.The moment that main switch QM is begun to turn in next cycle preparation, substantial secondary windings 130B have still maintained electric current, That is, opening the moment in next cycle main switch QM, release does not finish the energy that transformer 130 stores completely, Still there is energy residual.
Referring to Fig. 2 B, in order to be compared with the CCM pattern formations of flyback converter, the electric current in converter is also synchronously illustrated Under interrupted DCM (Discontinuous Conduction Mode) pattern, the primary current I of armature winding 130A is flowed throughP2And stream Secondary current I through secondary windings 130BS2Substantially waveform, while also substantially present the pressure difference of the drain-source interpolar of main switch QM VDS2Waveform.Primary current I in dcm modeP2Front end is there is no step values, and in the shut-off period T of main switch QMOFF, Secondary current IS2It is exactly directly the triangular wave decayed, it is before next cycle starts just in TOFFAt the end of decay to zero, Main switch QM is stored in all energy of armature winding 130A during turning on, before next cycle starts just completely Load is transferred to by secondary windings 130B.Pay attention in DCM patterns in any one cycle, with CCM patterns existing for greatly it is poor It is different to be, secondary current IS2During control signal closes main switch QM, zero, and secondary current I can be reduced toS2It is being reduced to There is one section of Dwell is dead for meeting between zero this moment to next cycle starts (namely main switch QM starts again at turn-on instant) Area time TD。
It is shown in Figure 3, in order to avoid in detection primary current IPTrigger unnecessary maloperation in step, introduce this A lead-edge-blanking signal LEB (Leading edge blanking) known to the technical staff in field.In primary electrical flow control In the loop of system, the conducting moment primary current I in main switch QM is often met withPPulse initial, peak phenomenon is had, is embodied Starting kurtosis initial spike can feed back to main control module 102 in sensor port CS, if being connected on armature winding On inductive reactance RSUp-sample current value at this time and as sensing signal VCSCarry out switch control, then it can be because of feeling in Fig. 3 Survey signal VCSUnexpected initial sharp wave Spike 355 and generate false triggering action, further start over current protection protection mechanism so that The no longer output pulse width modulated signal of main control module 102 of control signal is generated, so as to which real throat floater excessively occur no In the case of actively induce the action that mistake closes power main switch QM, to realize that protection power switch and/or entire flyback turn The purpose of parallel operation electronic device.Variable or fixed lead-edge-blanking signal LEB is exactly caused by conventional lead-edge-blanking circuit For eliminating this false triggering hidden danger, which is coupled to the control terminal of main switch QM, can ensure blanking signal LEB tools ahead of the curve There is high level main switch this period not close by mistake, and blanking signal LEB terminates afterwards again in inductive reactance R ahead of the curveSOn Sampling current signal is to capture more true and accurately sensing signal VCSInitial value is realized at the beginning of turning on moment to main switch QM Grade electric current IPPulse initial, peak shielded.
It will be understood that lead-edge-blanking circuit opens moment as primary current I for filtering out in main switch QMPStart to flow And the of short duration disturbing pulse occurred during initial sensing peak voltage initial spike is generated, lead-edge-blanking signal can control Signal, which is turned at the time of opening main switch QM at the time of high level can also open main switch QM than control signal, slightly to shift to an earlier date. Thus by Fig. 1 in inductive reactance RSGenerated primary sensing peak voltage is filtered on the node 101 of unearthed one end Fall.As to how design lead-edge-blanking circuit and the emphasis of non-invention, in the present invention only make it recapitulative discussion And it not repeats to repeat.Conventional power management design manual generally can all have lead-edge-blanking circuit more detailed introduction, U.S. Patent Application Publication US12/492,748, US12/718,707 grade documents can also be referred to.
Referring to Fig. 4 A~4C, when flyback converter enters CCM patterns, in the t of a cycle starting11Moment control signal meeting Main switch QM is driven to connect, due to the energy residual of upper a cycle transformer 130, primary current IPIt is connected in main switch QM Moment almost from zero rapidly direct saltus step into a forward position initial value IPV, forward position initial value IPVBeing one has more than zero Initial forward position step values.And and then in t11To t13This period in, since control signal drives main switch QM always Conducting, then during this period of time primary current IPInitial value I ahead of the curvePVOn the basis of, continue to increase with certain rate of rise. It will be noted that in t13At the moment, such as logic-high state of control signal is released from and is intended to disconnect main switch QM, but sends out Existing primary current IPDo not fall directly, but in moment t13To moment t14This section of turn-off delay time TPIt is interior, primary current IP With with t11To t13The period identical rate of rise and overshoot and rise to electric current IPHighest peak point current IPP, until prolonging Slow time TPT at the time of end14Primary current IPJust rapidly from peak IPPDrop into zero.Such as Fig. 4 B~4C, in moment t14Then Carve t15This period in, control signal can drive main switch QM to complete switch off, and in t14It is primary in moment transformer 130 Winding 130A starts the energy transmission of storage to secondary windings 130B, and flows through the secondary current I of secondary windings 130BSWhen Carve t14From zero meeting saltus step to a current peak I with maximumSP, winding all in transformer 130 is of the same name this moment End and the pole reversal at different name end, the rectifier diode D in Fig. 1 is made so as to the flyback voltage of secondary windings 130BOForward conduction, To provide load current, while return output capacitance COIt charges, from t14To t15This period in secondary current ISWith under one Drop angle rate is progressively decayed.T is arrived15When engrave a cycle and terminate, main switch QM will be re-circulated in next cycle It connects, and secondary current I at this timeSTool is there are one after along final states value ISV, after along final states value ISVIt is a final states having more than zero Step values.In moment t15Back to back next cycle main switch QM will be again switched to connection, the conducting of main switch afterwards Cause secondary current ISFrom rear along final states value ISVSaltus step is to zero.For CCM patterns, from time t on time dimension11It arrives t15It can be seen as a complete cycle TS, from time t11To t14It is defined as conducting period TON, think that main switch QM connects during this It is logical and from time t14To t15It is defined as shut-off period TOFF, think that main switch QM is disconnected during this, the duty cycle D of switchB1It should When being TONDivided by the conducting period is with turning off period sum of the two (TON+TOFF)。
Set the number of turn N of armature winding 130APWith the number of turn N of secondary windings 130BSRatio between two is N, wherein secondary windings Side electric current ISPeak point current ISP=N × IPPAnd secondary windings side electric current ISIt is rear along final states value ISV=N × IPV, in flyback Under the CCM patterns of converter, load R is supplied toLOutput current IOMeet following functional relation：
Referring back to Fig. 4 A, in t13Timing node, we intend the logic level state of control signal is made to be turned over from high level Low level is gone to, turns off main switch QM, this will synchronously cause primary current IPHave one in the overturning moment of control signal A cut-off current value IOFF, it is instantaneous value.It has illustrated above, in time t13To time t14This section of turn-off delay time TP It is interior, cut-off current value IOFFAlso it is primary current I not to bePMaximum, even in t13The logic state of moment control signal Tend to overturning to be intended to turn off main switch QM, primary current IPNor declining at once, actual conditions are, from timing node t13 To t14In this period, primary current IPIt still can be in cut-off current value IOFFOn the basis of continue to rise, rise slope and By forward position initial value IPVRise to cut-off current value IOFFThe rate of rise it is identical, until electric current IPRising to finally has It is the peak point current I of maximumPP, as shown in dotted line vertex in Fig. 4 A.As time delay TPInto during shut-off after terminating Between TOFF, main switch QM is disconnected, in TPTerminate the timing node t of moment14Locate primary current IPJust really from peak point current IPPIt opens Beginning quickly falls to zero.
Referring to Fig. 3, blanking signal LEB is turned into low level from high level and terminates the time of effective status ahead of the curve for we Node t12, to primary current IPOne intermediate samples current value of sampling is denoted as blanking current value ILEB, it is an instantaneous value, just Grade electric current IPBy forward position initial value IPV(forward position step values) rise to blanking current value ILEBThe rate of rise and primary current IPBy Cut-off current value IOFFRise to peak point current IPPThe rate of rise it is identical.In one cycle, we define control signal T at the time of driving main switch QM connections11T at the time of end to blanking signal LEB high level states12Between the duration that continues TLEB, t at the time of overturning occurs to disconnect main switch QM with control signal13To primary current IPRise to peak IPPAt the time of t14 Between the time delay T that continuesPIt is equal, i.e. TLEB=TP, while also define peak point current IPPWith cut-off current value IOFFBetween deposit In a difference DELTA I1, the current relationship of Fig. 4 A can in detail be calculated from geometric angle, can further draw IPP =IOFF+ Δ I1 and IPV=ILEB- Δ I1.
IPP+IPV=(IOFF+ΔI1)+(ILEB- Δ I1) (3)
IPP+IPV=IOFF+ILEB (4)
If formula (4) is substituted into formula (2) can be obtained by output current I under CCM patternsOFinal expression formula, Middle cycle TS=TON+TOFF：
We are not intended to the output current I in primary sideOExpression formula in embody IPPOr ISV, reason for this is that their mistake Stroke degree and on to rush peak value be actually to be difficult to capture or sense in circuit, they are beyond the Grasping skill scope to circuit Outside, it is concealment for the topology of design, to output current IOThe hardly possible dependence I of calculatingPPOr ISV, formula Sub (5) then solve the problems, such as this well in ccm mode.
Referring to Fig. 5 A~5C, when flyback converter enters DCM patterns, in the t of a cycle starting21Moment, control signal Main switch QM will be driven to connect, since the energy of upper periodic pressure oscillation device 130 is without residue, primary current IPIn main switch QM The moment of connection its forward position initial value IPVAlmost zero, this is entirely different with initial step value with CCM patterns.And immediately It in t21To t23This period in, control signal drive always main switch QM turn on, so during this period of time primary current IPInitial value I ahead of the curvePVZero value on the basis of, gradually risen with certain rate of rise.Until in t23Moment, control signal Such as logic-high state be flipped to low level and be intended to disconnect main switch QM, similary primary current IPDo not fall directly Fall, but in moment t23To moment t24This section of turn-off delay time TPIt is interior, primary current IPWith with t21To t23Period is identical The rate of rise and overshoot and rise to electric current IPHighest peak point current IPP, until in time delay TPT at the time of end24It is primary Electric current IPJust rapidly from peak IPPDrop into zero.
Referring to Fig. 5 B~5C, time delay TPAfter end, in moment t24To moment t25This period in, control signal Main switch QM will be driven to complete switch off, and in t24Armature winding 130A starts the energy of storage in moment transformer 130 Secondary windings 130B is transferred to, and flows through the secondary current I of secondary windings 130BSIn moment t24From zero meeting saltus step to most A current peak I being worth greatlySP, the pole reversal at the Same Name of Ends of winding all in transformer 130 and different name end, secondary this moment The flyback voltage of winding 130B causes the rectifier diode D in Fig. 1OForward conduction to provide load current, while returns output Capacitance COIt charges, from t24To t25This period in secondary current ISZero is progressively decayed to a descending slope.DCM patterns with The different another aspect of CCM patterns is embodied in, and has arrived t25Moment a cycle does not terminate, secondary current I at this timeSWith one It is a be zero it is rear along final states value ISV, that is to say, that secondary current ISJust in T before next cycle startsOFFAt the end of decline Zero is reduced to, main switch QM is stored in all energy of armature winding 130A during turning on, before next cycle starts just Load is transferred to by secondary windings 130B completely.In figure 5 c, secondary current ISClose main switch QM's in control signal Turn off period TOFFTerminate moment, zero can be reduced to, secondary current ISIt is being reduced to zero this moment t25To current period terminate when Between point t26Between there is one section of dead time TD, time point t26It is exactly the beginning of next cycle period after terminating, so Dead time TDIt is clamped in secondary current IST at the time of being reduced to zero25With main switch QM conducting is started again in next cycle Between moment.For the DCM patterns of flyback converter, from time t on time dimension21To t26Can be seen as one it is complete Whole cycle TS, from time t21To t24It is defined as conducting period TON, think that main switch QM is connected and from time t during this24 To t25It is defined as shut-off period TOFF, think that main switch QM is disconnected during this, from time t25To t26It is defined as dead time TD, this Period thinks what main switch QM was also disconnected, then the duty cycle D of primary side switchB2Should be TONDivided by conducting the period with Turn off the sum of period, dead zone period three (TON+TOFF+TD)。
Set the number of turn N of armature winding 130APWith the number of turn N of secondary windings 130BSRatio between two is N, wherein secondary windings Side electric current ISPeak point current ISP=N × IPPAnd secondary windings side electric current ISIt is rear along final states value ISV=0, it is converted in flyback Under the DCM patterns of device, load R is supplied toLOutput current IOMeet following functional relation：
Referring to Fig. 5 A and 5C, in time point t23The logic state of control signal is made to overturn to low level to drive main switch QM At the time of shut-off, synchronously cause primary current IPCut-off current value I there are one having in the end moment of control signalOFF.In the time t23To time t24This section of turn-off delay time TPIt is interior, cut-off current value IOFFIt is not primary current IPMaximum, even exist t23The logic state of moment control signal has tended to overturning and has been intended to turn off main switch QM, primary current IPNor under at once Drop.Actual conditions are, from timing node t23To t24In this period, primary current IPIt still can be in cut-off current value IOFFBase Continue to rise on plinth, rise slope and by forward position initial value IPVRise to cut-off current value IOFFThe complete phase of the rate of rise Together, until electric current IPRise to finally have be maximum peak point current IPP, as shown in the vertex of dotted line in Fig. 5 A.One Denier is as time delay TPInto shut-off period T after terminatingOFF, main switch QM is just disconnected completely, and in time delay TPKnot The timing node t of beam moment24Locate primary current IPJust really from peak point current IPPStart to quickly fall to zero.
Referring to Fig. 5 C, still blanking signal LEB is turned into low level from high level and terminates effective status ahead of the curve for we Timing node t22, to primary current IPOne intermediate samples current value of sampling is denoted as blanking current value ILEB, primary current IP By forward position initial value IPV(zero) rises to blanking current value ILEBThe rate of rise and primary current IPBy cut-off current value IOFF Rise to peak point current IPPThe rate of rise it is identical.In a complete cycle, control signal driving main switch QM is defined T at the time of connection21T at the time of end to lead-edge-blanking signal LEB high level states22Between the duration T that continuesLEB, with control T at the time of overturning occurs for signal to disconnect main switch QM23To primary current IPRise to peak IPPAt the time of t24Between continue Time delay TPEqual namely TLEB=TP, then peak point current IPPWith cut-off current value IOFFBetween can there are a difference DELTA I2, The current relationship of Fig. 5 A can in detail be calculated from geometric angle, from which further follow that IPP=IOFF+ Δ I2 and IPV= ILEB- Δ I2=0.
IPP+IPV=(IOFF+ΔI2)+(ILEB- Δ I2) (8)
IPP+IPV=IOFF+ILEB (9)
If formula (9) is substituted into formula (7) can be obtained by output current I under DCM patternsOFinal expression formula, Middle cycle TS=TON+TOFF+TD：
Although primary side peak point current IPPOr primary side peak point current ISVOvershoot degree and on rush peak value and be difficult to be caught It catches or senses, but formula (10) can solve the problems, such as this well in dcm mode, because estimation output current IOPublic affairs Peak point current I is free of in formulaPPOr step values ISV。
Estimation output current I has been set forth aboveOIt needs to capture t under CCM patterns12The blanking current value I at momentLEBAnd t13 The cut-off current value I at momentOFFAnd it needs to capture t under DCM patterns22The blanking current value I at momentLEBAnd t23The shut-off at moment Current value IOFF.Blanking current value ILEBWith cut-off current value IOFFUnlike peak point current IPPOr IPVIt is difficult to sense actual value like that, They can be directly from inductive reactance RSAt the node 101 of one end of no ground connection suitable opportunity is selected to be captured, this Just there are solution in sample formula (5) and (10).
It is for calculating the output current I of flyback converter secondary windings 130B referring to Fig. 6OCounting circuit 280, change Yan Zhi is attempt to realize the calculating of formula (5) and (10).Counting circuit 280 includes at least a detecting module 201, for examining It surveys and captures the primary current I flowed through on armature winding 130AP, test format can capture directly and be across inductive reactance RSOn It is presented as the sensing signal V of voltage valueCS, because flowing through inductive reactance RSOn primary side current at different moments and inductive reactance RS The sensing signal V corresponding at different moments that can be converted into of resistance value multiplicationCS.We need the inspection in rational timing Measure accurate blanking current value ILEBWith accurate cut-off current value IOFFSize, Detection task is by detecting module 201 real It applies.
Referring to the detecting module 201 of Fig. 6, apply at the node 105 that operating voltage is provided for voltage current adapter 110 One direct current power source voltage VDDIt powers to converter 110 and the voltage of voltage current adapter 110 is turned into current input terminal and connect It is connected to inductive reactance R in Fig. 1SAt the common node 101 being connected with main switch QM source terminals.In order to avoid with similar device hereinafter Obscuring nominally, voltage current adapter 110 is denoted as first voltage current converter.In the electricity of voltage current adapter 110 A stream release end/transfer resistance R12 is connected between output terminal and ground terminal, then voltage current adapter 110 will be in voltage Turn current input terminal and input to its voltage i.e. sensing signal VCSThe intermediate current I convertedMTransfer resistance R12 is flowed through, Voltage value will be generated at the node 121 of the unearthed one end of transfer resistance R12.It, can be with as optional and nonessential item Turn to connect a resistance R10 between current input terminal in the voltage of common node 101 and voltage current adapter 110, and in electricity The voltage of voltage-current converter 110 turns to connect a capacitance C between current input terminal and ground terminal1, so as to turn in voltage and current The voltage of parallel operation 110 turns current input terminal and is sent into more smooth sensing signal VCS.It, can also be as optional and nonessential item Node 121 and ground terminal be directly connected to a resistance value variable regulation resistance R11, the regulation resistance R11 of detecting module 201 and Transfer resistance R12 is connected in parallel between node 121 and ground terminal so that total resistance value between node 121 and ground terminal passes through adjusting Resistance R11 and become adjustable.
Referring to Fig. 6, detecting module 201 further includes a first voltage follower 111 and a second voltage follower 112, the positive input terminal of first, second voltage follower 111,112 is set to be all connected to the unearthed one end of transfer resistance R12 At node 121, and the negative input end of first voltage follower 111 is set to be connected to its output terminal, second voltage follower 112 Negative input end be connected to its output terminal, first, second essentially identical voltage follower 111,112 is according to respective positive input The voltage value that end captures comes to next stage output voltage.First, second voltage follower 111,112 is used as input buffer, tool There is higher input impedance feature to be connected with signal source, high input impedance can completely cut off influencing each other for front stage, and They also have relatively low output impedance feature to reduce to sensing signal VCSPull-in time.First, second voltage follow Device 111,112 is configured to voltage follower (Voltage follower) or unity gain buffer by operational amplifier (Unity-gain buffer).In addition, needs have hereinbefore been illustrated in crawl sensing signal V of rational opportunityCS, based on this Point considers that detecting module 201, which also includes, to be denoted as the switch SW1 of first switch and be denoted as the switch SW2 of second switch, switchs SW1 It is connected to the output terminal of first voltage follower 111 and between the sampling that will introduce hereinafter keeps latch 202, switchs SW2 Also it is connected between the output terminal of second voltage follower 112 and sampling holding latch 202.The switch SW1 that occurs herein and SW2 and electronic switch SW3~SW5 that will hereafter introduce etc. is three port type electronic switches, and such switch is except including phase To an input terminal and an output terminal outside, also comprising one for being connected or disconnected between control signal, output terminal Control terminal, electronic switch there are many selection mode, such as p-type or N-type MOS transistor or bipolar transistor or junction transistor or Combination thereof etc..
First, in ccm mode, detecting module 201 is introduced in advance from inductive reactance RSFigure is detected at the node 101 of one end T in 4C12Moment corresponding sensing signal VCS-LEBScheme.Lead-edge-blanking signal LEB is except shielding sensing signal VCSIt is initial Outside sharp wave Spike 355, at the node 103 for the control terminal that lead-edge-blanking signal LEB is also additionally connected to switch SW2, so As long as blanking signal LEB has the stage of high level logic state ahead of the curve, switch SW2 can be switched on always, with first Grade electric current IPVariation, characterization primary current IPThe situation of sizes values is just embodied in the sensing signal V at node 101 completelyCSOn. T at the time of being switched on since the main switch QM in any one cycle11Low electricity is turned into lead-edge-blanking signal LEB from high level T at the time of flat12Namely blanking signal LEB is continuously the period T in high level stage ahead of the curveLEBIt is interior, primary current IPIt is corresponding From forward position initial value IPVRise to moment t12Blanking current value ILEB, sensing signal V in this periodCSRising variation can quilt Detecting module 201 detects at node 101, and voltage current adapter 110 will be by sensing signal VCSThe current value converted Again voltage value is reverted at the node 121 of the unearthed one end of transfer resistance R12.
Specifically, in period TLEBAlthough interior dynamic sensing signal VCSVoltage current adapter is all inputed to always 110, once but lead-edge-blanking signal LEB be turned into low level and disconnect switch SW2, moment t12Believe afterwards to lead-edge-blanking Into before the high level state of its next cycle, second voltage follower 112 all can not be by the electricity at node 121 by number LEB Pressure value is converted into electric current output.In moment t12Corresponding characterization blanking current value ILEBThe sensing signal V of sizeCS-LEBIt is input to The voltage of voltage current adapter 110 turns current input terminal, is converted thereof by voltage current adapter 110 and flows through transfer resistance The intermediate conversion electric current I of R12M, take this intermediate conversion electric current I furtherMIt is converted into across the pressure at transfer resistance R12 both ends Drop, such as equal to voltage sense signal VCS-LEB, and the voltage that second voltage follower 112 will be applied on transfer resistance R12 again That is the voltage of node 121 changes into and sensing signal VCS-LEBEqual voltage output.Lead-edge-blanking signal LEB is turned into low electricity After flat, a cycle TSThe voltage value of interior 112 final output of second voltage follower is fixed in t12Moment corresponding voltage sense Survey signal VCS-LEBLevel.Included one sampling of counting circuit 280 one second that latch (S/H) 202 is kept to have deposits Storing up electricity holds C3It receives the voltage from 112 output terminal of second voltage follower and is electrically charged, the second storage capacitance C3One end as save Switch SW2, the second storage capacitance C are connected between point 123 and 112 output terminal of second voltage follower3The other end directly connect To ground terminal.With voltage sense signal VCS-LEBEquivalent voltage is to the second storage capacitance C3It charges, then the second storage capacitance C3It protects Hold and store moment t12The corresponding blanking current value I for flowing through armature winding 130ALEBInformation, the information of storage are presented as Two storage capacitance C3The voltage value V held at one end node 123CS-LEB。
It is still in ccm mode, then to introduce detecting module 201 from inductive reactance RSFigure is detected at the node 101 of one end T in 4C13Moment corresponding voltage sense signal VCS-OFFScheme.Controls of the control signal such as PWM except driving main switch QM Outside end, control signal is additionally also coupling-connected to the control terminal of switch SW1, as long as so there is high level in control signal In the stage of logic state, switch SW1 can be switched on always, on the contrary then switch SW1 and be turned off, with primary current IPBy Step rises, characterization primary current IPThe situation of sizes values is just embodied in the sensing signal V at node 101 completelyCSOn.From any one T at the time of the main switch QM in a cycle starts to be switched on11Low level moment t is turned into control signal from high level13, just Grade electric current IPIt corresponds to from forward position initial value IPVRise to moment t13Cut-off current value IOFF, sensing signal in similary this period VCSRising variation can be detected module 201 and detected in node 101, and voltage current adapter 110 will be by sensing signal VCS The current value converted reverts to voltage value at the node 121 of the unearthed one end of transfer resistance R12 again.
Specifically, in t11To t13Although period in dynamic sensing signal VCSVoltage and current is all inputed to always Converter 110, once but control signal be turned into low level from high level and disconnect switch SW1, moment t13Afterwards to control Signal processed enters before the high level state of its next cycle, and first voltage follower 111 all can not be by the electricity at node 121 Pressure value is converted into electric current output.And moment t13Correspondence characterizes cut-off current value IOFFThe sensing signal V of sizeCS-OFFIt is entered Turn current input terminal to the voltage of voltage current adapter 110, converted thereof by voltage current adapter 110 and flow through conversion electricity Hinder the intermediate conversion electric current I of R12M, take this intermediate conversion electric current IMIt is converted into across the voltage at transfer resistance R12 both ends, example Such as it is equal to voltage sense signal VCS-OFF, and first voltage follower 111 again will be across voltage, that is, node on transfer resistance R12 Voltage at 121 changes into and sensing signal VCS-OFFEqual voltage output.A cycle TSInterior first voltage follower 111 The voltage value of final output is fixed in t13Moment corresponding sensing signal VCS-OFF.Sampling is kept for one in latch 202 the One storage capacitance C2The voltage from the transmission of 111 output terminal of first voltage follower is received, in first storage capacitance C2One end It is controlled by the switch SW1 of control signal, the first storage as being connected between 111 output terminal of node 122 and first voltage follower Capacitance C2Another terminate to ground terminal.With sensing signal VCS-OFFEquivalent voltage is to the first storage capacitance C2Charging, first Storage capacitance C2Keep and store moment t13The corresponding cut-off current value I for flowing through armature winding 130AOFFInformation, storage Information be presented as the first storage capacitance C2The voltage value V held at a unearthed end node 122CS-OFF.As optional Optionally item can also connect one and the first storage electricity in sampling keeps latch 202 between node 122 and ground terminal Hold C2Switch SW3 in parallel and connection one and the second storage capacitance C between node 123 and ground terminal3Switch in parallel SW4, switch SW3 and SW4 are traditionally arranged to be disconnection but can apply drive signal in their control terminal when necessary The first storage capacitance C is discharged respectively to connect them2With the second storage capacitance C3Upper storage electricity carries out reset operation.
Although it is that blanking current value I is detected based on discussion electric pressure converter in ccm mode aboveLEBAnd cut-off current Value IOFFThe mode of information.But substantially, in order to also detect blanking current value I in dcm modeLEBWith cut-off current value IOF F Information, method for detecting above stand good, and are hereafter stated simple.
In dcm mode, detecting module 201 is from inductive reactance RST in Fig. 5 C is detected at the node 101 of one end22Moment pair The sensing signal V answeredCS-LEBScheme it is as follows.Lead-edge-blanking signal LEB is connected to the node 103 of the control terminal of switch SW2 Place, the high level logic state phase of blanking signal LEB, switch SW2 are switched on ahead of the curve.From the main switch in any one cycle T at the time of QM starts to be switched on21Low level moment t is turned into lead-edge-blanking signal LEB from high level22Namely in the time Section TLEBIt is interior, primary current IPThe corresponding forward position initial value I from zeroPVRise to moment t22Blanking current value ILEB.In the time Section TLEBAlthough interior dynamic sensing signal VCSVoltage current adapter 110 is all inputed to always, once but lead-edge-blanking signal LEB is turned into low level and disconnects switch SW2, moment t22Enter its next cycle to lead-edge-blanking signal LEB afterwards Before high level state, the voltage value at node 121 all can not be converted into exporting by second voltage follower 112.And the moment t22Corresponding characterization blanking current value ILEBThe sensing signal V of sizeCS-LEBThe voltage for being input to voltage current adapter 110 turns Current input terminal is converted thereof into the intermediate conversion electric current I for flowing through transfer resistance R12 by voltage current adapter 110M, take this Further by intermediate conversion electric current IMIt is converted into across the voltage at transfer resistance R12 both ends, and second voltage follower 112 is again It will be changed into and sensing signal V across the voltage at voltage, that is, node 121 on transfer resistance R12CS-LEBEquivalent voltage is defeated Go out.A cycle TSThe voltage value of interior 112 final output of second voltage follower is fixed in t22Moment corresponding sensing signal VCS-LEB.Second storage capacitance C3It receives from the transmission of 112 output terminal of second voltage follower and sensing signal VCS-LEBIt is equivalent Voltage, to the second storage capacitance C3It charges, the second storage capacitance C3Keep and store moment t22It is corresponding flow through it is primary around The blanking current value I of group 130ALEBInformation, the information of storage is presented as the second storage capacitance C3A unearthed end node 123 The voltage value V that place is heldCS-LEB。
In dcm mode, detecting module 201 detects t in Fig. 5 C at the node 101 of inductive reactance RS one end23Moment pair The sensing signal V answeredCS-OFFScheme it is as follows.Control signal is connected to the control terminal of switch SW1, in the height electricity of control signal Flat logic state stage, switch SW1 are switched on.T at the time of being switched on since the main switch QM in any one cycle21To control Signal is turned into low level moment t from high level23, primary current IPThe corresponding forward position initial value I from zeroPVRise to the moment t23Cut-off current value IOFF.In t21To t23Although period in dynamic sensing signal VCSVoltage and current is all inputed to always Converter 110, once but control signal be turned into low level from high level and disconnect switch SW1, moment t23Afterwards to control Signal processed enters before the high level state of its next cycle, and first voltage follower 111 all can not be by the electricity at node 121 The conversion output of pressure value.And moment t23It is corresponding to characterize cut-off current value IOFFThe sensing signal V of sizeCS-OFFIt is input to electricity The voltage of voltage-current converter 110 turns current input terminal, is converted thereof by voltage current adapter 110 and flows through transfer resistance The intermediate conversion electric current I of R12M, further by intermediate conversion electric current IMIt is converted into across the voltage at transfer resistance R12 both ends, the One voltage follower 111 will be changed into again across the voltage at voltage, that is, node 121 on transfer resistance R12 and sensing signal VCS-OFFEquivalent voltage output.A cycle TSThe voltage value of interior 111 final output of first voltage follower is fixed in t23When Carve corresponding sensing signal VCS-OFF.First storage capacitance C2It receives from the transmission of 111 output terminal of first voltage follower and sense Survey signal VCS-OFFEquivalent voltage, and to the first storage capacitance C2Charging, the first storage capacitance C2Holding stores moment t23 The corresponding cut-off current value I for flowing through armature winding 130AOFFInformation, the information of storage is presented as the first storage capacitance C2Not The voltage value V held at one end node 122 of ground connectionCS-OFF。
By scheme discussed above, detecting module 201 has captured t under CCM patterns12The blanking current value I at momentLEBWith t13The cut-off current value I at momentOFFSampling is stored in keep latch 202 and captured t under DCM patterns22The blanking at moment Current value ILEBAnd t23The cut-off current value I at momentOFFIt is stored in sampling and keeps latch 202.Final purpose is to cater to formula (5) and the calculating of (10) will be further described, therefore hereafter to blanking current value ILEBWith cut-off current value IOFFThe meter summed Calculate and calculate TOFFWith TSThe ratio between.
Referring to Fig. 6, counting circuit 280 includes an electric current sum unit 203, and electric current sum unit 203 is containing there are one electricity Voltage-current converter 113 and another voltage current adapter 114, in order to be distinguished with showing, they correspond to and are denoted as the second He respectively Tertiary voltage current converter.It provides in respectively voltage current adapter 113,114 and is applied at the node 106,107 of operating voltage Add direct current power source voltage VDDIt powers to converter 113,114 and is exported in the electric current of both voltage current adapters 113,114 It holds and connects a summation resistance R14 at the common connection node 124 of interconnection between ground terminal.Voltage current adapter 113 Voltage turns current input terminal and is connected to the first storage capacitance C2At the node 122 of one end, the first storage capacitance C2The shut-off electricity of holding Flow valuve IOFFInformation is to be equal to voltage value VCS-OFFMode be conveyed to voltage current adapter 113, so as to voltage current adapter 113 by the first storage capacitance C2The cut-off current value I of storageOFFInformation is changed into is equal to shut-off in the output of its current output terminal Current value IOFFElectric current.At the same time, the voltage of voltage current adapter 114 turns current input terminal and is then connected to the second storage Capacitance C3At the node 123 of one end, make the second storage capacitance C3The blanking current value I of holdingLEBInformation is to be equal to voltage value VCS-LEB Mode be conveyed to voltage current adapter 114, so as to which voltage current adapter 114 is by the second storage capacitance C3The blanking of storage Current value ILEBInformation is changed into is equal to blanking current value I in the output of its current output terminalLEBElectric current.
That is, it is based on cooperatively connecting the voltage current adapter 113,114 respective current output terminals merging It is connected at the common node 124 of the unearthed one end of summation resistance R14 and is grounded the other end for the resistance R14 that sums, then flow through and ask Cut-off current value I is equal to the total current of resistance R14OFFWith blanking current value ILEBThe summation of the two, equal to ILEB+IOFF, and Voltage value V at node 124124Equal to ILEB+IOFFThe sum of with sum resistance R14 resistance value RSUMIt is multiplied.In addition, electric current summation is single Member 203 also comprising a tertiary voltage follower 128, positive input terminal be connected at the common node 124 of resistance R14 one end and Negative input end is then connected to its output terminal, is configured to voltage follower (Voltage follower) or unit gain amplification Device, the voltage received by its positive input terminal generates and output voltage VTRS, the size of adjustment summation resistance R14 resistance values is adjusted the The output voltage values size of three voltage followers 128 can for example set the output voltage V of tertiary voltage follower 128TRSWith The resistance value R of summation resistance R14SUMIt is multiplied by (ILEB+IOFF) result it is equal or proportional therewith.It is exemplary but unrestricted at one Property embodiment in, if the resistance value of summation resistance R14 is taken to be equal to 1 ohm, the output voltage of tertiary voltage follower 128 can To be equal to (ILEB+IOFF)。
Referring to Fig. 6, counting circuit 280 includes 205 circuit of output stage, in the node of the output port of output stage 205 Final output voltage V is conveyed at 126F.If the output voltage V that tertiary voltage follower 128 transmitsTRSIn a cycle TSIt is interior Only in period TOFFIt is interior to be exported by output stage 205, cycle TSThe interior others period is not exported by output stage 205, It can allow output voltage VF=VTRS×(TOFF÷TS) namely VF=RSUM×(ILEB+IOFF)×(TOFF÷TS), this imagination Specific budget mode dependent on counting circuit.With reference to above equation (5) and (10), it is contemplated that since turn ratio N is transformation The setting value of device 130 and adjustable accommodation, then the output current I of 130 primary side of transformerOWith the output electricity of output stage 205 Press VFBetween relation be IO=(N × VF)÷(RSUM× 2), that is to say, that flyback converter output current IOIt can be by output stage 205 realize precomputation.
Referring to Fig. 6, counting circuit 280 further includes a logic control element 204, and logic control element 204 determines the 3rd The output voltage V that voltage follower 128 transmitsTRSIn a cycle TSInside only in period TOFFIt is interior to pass through output stage 205 Output, in whole cycle TSExcept period TOFFIt is not exported in remaining other times from output stage 205.In output stage 205 There is provided a switch SW5, are denoted as the 3rd switch, switch SW5 an output head grounding and an input terminal node 125 it is straight Connect or be indirectly coupled to the output terminal of tertiary voltage follower 128.In one embodiment, tertiary voltage follower 128 is defeated Node of the connection there are one resistance R15 and in switch SW5 one end between the node 125 of outlet and switch SW5 input terminals There are one capacitance C for connection between 125 and ground terminal5If enable resistance R15 and capacitance C5If then they be equivalent to one and take Sample holding circuit.In a complete cycle TSPeriod, either CCM patterns or DCM patterns, when closed all section TOFFIt will It switchs SW5 to disconnect, so as to output voltage VTRSThe node 126 of output port can be output to by output stage 205.But in CCM moulds Conducting period T under formulaONInterior needs will switch SW5 and connect or be needed in dcm mode in conducting period TONIt is interior and dead Area period TDIt is interior to connect switch SW5, so as to output voltage VTRSGround terminal GND is flowed to but not by defeated by the switch SW5 of connection Go out the node 126 that grade 205 is output to output port.As long as it is intended that judge to switch using logic control element 204 The opportunity that SW5 is turned on or off can transmit output voltage V out to tertiary voltage follower 128TRSIt further performs and multiplies With a ratio (TOFF÷TS) calculating.
Referring to Fig. 6, logic control element 204 includes the 4th voltage follower 115, wherein the 4th voltage follower 115 positive input terminal is connected in Fig. 1 at the node 104 of the drain electrode end of N-type power MOSFET main switches QM, the source of main switch QM Extremely it is connected at node 101.4th voltage follower 115 be used as input buffer, have higher input impedance feature with Just it is connected with signal source, high input impedance can completely cut off influencing each other for front stage, the negative input end of the 4th voltage follower 115 Its output terminal is connected to, it is made to be configured to voltage follower (Voltage follower) or unit gain by operational amplifier Buffer, the 4th voltage follower 115 are used to detect the drain electrode end of main switch QM and armature winding 130A junctions common node 104 voltage change.Except that the 4th voltage follower 115 can be configured to follower according to Fig. 6, it is to be understood that can also use The similar devices such as input voltage and the adjustable voltage amplifier of the proportionate relationship of output voltage replace it, by the leakage of main switch QM Extreme voltage is transported to one end of resistance R13 again after first reducing or increase.Nationality is picked by 115 positive input terminal of the 4th voltage follower The drain terminal voltage taken generates and exports a voltage, and the voltage of the 4th voltage follower 115 output is transferred to logic control list One end of a resistance R13, the other end of resistance R13 are connected to a capacitance C in logic control element 204 in member 2044's At one end node 127, capacitance C4Other end ground connection, resistance R13 and capacitance C4A phase-shift circuit is formed, is embodied in when the When the voltage of four voltage followers, 115 output terminal declines, the voltage of node 127 will postpone under just starting after a short time Drop, so they also correspond to be a delay circuit.In addition, logic control element 204 further includes a comparator 116, it should The in-phase input end of comparator 116 is connected at node 127 and inverting input is then connected to one and provides reference voltage VTH's The anode of voltage source (such as battery), and the cathode of the battery is connected to 115 output terminal of the 4th voltage follower.4th voltage follow The very sensitive voltage change trend of monitoring main switch QM drain electrodes end node 104 of device 115, and the primary voltage of node 104 is by the The form that four voltage followers 115 are converted into secondary state voltage embodies.The effect of comparator 116 is, in-phase end is received Capacitance C4On node 127 at voltage and end of oppisite phase receive reference voltage VTHWith 115 output terminal of the 4th voltage follower Voltage sum of the two is compared, while a rest-set flip-flop 120 comparative result being transported in logic control element 204 Set end S.
Grid and driving switch of the control signal that main control module 102 the is sent such as pwm signal except driving main switch QM Outside the control terminal of SW1, also logic control element 204 is controlled.Logic control element 204 contains two phase inverters 117th, 118 and one with door 119, wherein being connected with the phase inverter between an input terminal of door 119 and another input terminal 118.It needs control signal being transported to after 117 reverse phase of phase inverter with an input terminal of door 119 and by control signal It is transported to another input terminal with door 119 again after phase inverter 117,118 priority of phase inverter twice reverse phase successively.Phase inverter 118 have the time delays of nanosecond (ns) grade, and merge with door 119 and phase inverter 118 together with phase inverter 117 be formed as one by The monostable flipflop of the trailing edge triggering of control signal.The reset of rest-set flip-flop 120 is connected to the output terminal of door 119 simultaneously R is held, the output signal S with door 119 is controlled primarily by so as to the output result of 120 its Q output of rest-set flip-flopTRIAnd comparator 116 comparative result SCOM, and the comparative result S of comparator 116COMDepending on the influence of main switch QM drain terminal voltages, with door 119 output signal STRITrailing edge depending on control signal.The Q output of rest-set flip-flop 120 is also connected to output by us The control terminal of SW5 is switched in grade 205, by the output result of Q output come the switching of driving switch SW5.Reference can be made to Fig. 7 A CCM patterns and Fig. 7 B DCM patterns under, the output signal S with door 119TRIWith the comparative result S of comparator 116COMInfluence Q The waveform diagram of the output result of output terminal.
It is all with each conducting of the door 119 in main switch QM referring to Fig. 7 A and Fig. 7 B, either CCM patterns or DCM patterns The high level monostable that a nanosecond (ns) grade can be generated at the end of phase because of the inversion signal of control signal PWM resets letter Number, i.e., the output signal S shown in figure with door 119TRIRelatively narrow high level pulse, make rest-set flip-flop Q ends export result It, should at the end of the high level of every secondary control signal PWM namely the trailing edge of control signal PWM at the time of enters low level state State continues entire shut-off period TOFF, switch SW5 is forced to disconnect the voltage V tertiary voltage follower 128 to be exportedTRSIt is closing Disconnected period TOFFIt is exported by output stage 205.Under CCM patterns and DCM patterns, any one switch periods works as main switch QM quilts The control signal connection of high level initially enters conducting period TONIn the stage, the drain terminal voltage value of main switch QM is relatively low, when the 4th When the secondary voltage value that the primary voltage for the node 104 that voltage follower 115 detects is converted into its output terminal emerges from, The voltage decline of node 104 can also cause the voltage of 115 output terminal of the 4th voltage follower to decline, because of resistance R13 and capacitance C4 Phase shift effect or carryover effects, the relatively low voltage of this stage main switch QM drain electrode ends can cause capacitance C4At upper node 127 Voltage value is higher than reference voltage VTHThe sum of with the secondary voltage value of 115 output terminal of the 4th voltage follower, so rest-set flip-flop 120 set end S receives the high level comparative result S that comparator 116 exportsCOMTo transmit out high level in Q output, force Switch voltage V of the SW5 connections tertiary voltage follower 128 to be exportedTRSIn conducting period TONIt is discharged into ground.It is noticeable It is, in dcm mode, because of secondary current ISWhen dropping to zero, expression will enter dead time TDSo that main switch QM drain electrode ends are electric Drops, drain voltage is in the period than turning off period TOFFIt is much lower, since relatively low drain voltage can cause the 4th voltage The voltage synchronous of 115 output terminal of follower declines, this moment capacitance C4Voltage value at upper node 127 is because of resistance R13 and capacitance C4's Phase shift effect so that capacitance C4Upper 127 voltage value of node is higher than reference voltage VTHIn addition 115 output terminal of the 4th voltage follower Voltage, so the set end S of rest-set flip-flop 120 receives the high level comparative result S that comparator 116 exportsCOMWith in Q output High level is transmitted out, switch SW5 is forced to connect the voltage V tertiary voltage follower 128 to be exportedTRSIn dead time TDIt releases It is put into ground.
Take this, in cycle TSInside in this way, only in period TOFFInterior permission voltage VTRSIt is exported by output stage 205 To node 126, V can be madeF=RSUM×(ILEB+IOFF)×(TOFF÷TS), then the secondary one side of transformer 130 is provided to load Output current IOEqual to { N × (ILEB+IOFF)×TOFF}÷(2×TS), further extrapolate electric current IOEqual to (N × VF)÷(2× RSUM), realize the calculating of formula (5) and (10), wherein N is the number of turn N of armature winding 130APWith the number of turn N of secondary windings 130BS The ratio of the two.
In some optional embodiments, at the node 125 for the input terminal that SW5 can be switched in output stage 205 and A resistance R15 and at the node 125 of switch SW5 one end and defeated is connected between the output terminal of tertiary voltage follower 128 A resistance R16 is connected between the node 126 of exit port, is connected at one end of resistance R16 namely node 125 between ground terminal One capacitance C5, another capacitance C is connected between the other end of resistance R16 namely node 126 and ground terminal6.Output stage 205 Comprising resistance R16 and C6It is good filter circuit, can ensures the output voltage exported at the node 126 of output port VFIt is the smooth voltage with smaller ripple.
Above by explanation and attached drawing, the exemplary embodiments of the specific structure of specific embodiment, foregoing invention are given Existing preferred embodiment is proposed, but these contents are not intended as limiting to.For a person skilled in the art, in reading State it is bright after, various changes and modifications undoubtedly will be evident.Therefore, appended claims, which should be regarded as, covers the present invention True intention and scope whole variations and modifications.In Claims scope the scope of any and all equivalence with it is interior Hold, be all considered as still belonging to the intent and scope of the invention.

Claims (30)

1. a kind of output current counting circuit for flyback converter, which is characterized in that including：
One detecting module, detection flow through the primary current on an inductive reactance with primary windings connected in series, and for controlling It the moment that the main switch that armature winding processed is switched on or switched off is turned off by a control signal, detects and flows through inductive reactance Cut-off current value IOFFAnd for shield primary current starting spike a lead-edge-blanking signal effective status The moment of end detects the blanking current value I for flowing through inductive reactanceLEB；
One sampling keeps latch, storage cut-off current value IOFFInformation and blanking current value ILEBInformation；
One electric current sum unit, to cut-off current value IOFFWith blanking current value ILEBCarry out read group total；
One output stage, by cut-off current value IOFFWith blanking current value ILEBThe voltage that obtained summation electric current is converted of summing exists It is exported in each cycle according to a default proportionate relationship in cycle；
One logic control element, judge output stage receive in one cycle one of voltage that summation electric current is converted into it is default Period accounts for cycle ratio, and the preset time period of output stage in each cycle is allowed to receive the voltage that summation electric current is converted but taboo Only remaining time of the output stage in each cycle in addition to the preset time period receives the voltage of summation electric current conversion.
A kind of 2. output current counting circuit for flyback converter according to claim 1, which is characterized in that detecting Module tool there are one first voltage current converter, gather to characterize primary current size across the voltage on inductive reactance Sensing signal, and voltage sense signal is converted into flow through the current output terminal and the ground connection that are connected to first voltage current converter The intermediate current of a transfer resistance between end；
In the moment of main switch shut-off, detecting module by the moment be applied to voltage conversion on transfer resistance into cut-off current Value IOFFCorresponding voltage sense signal is conveyed to sampling and keeps latch storage；
The moment is applied to the voltage on transfer resistance by the moment that the effective status of blanking signal terminates ahead of the curve, detecting module It is converted into and blanking current value ILEBCorresponding voltage sense signal is conveyed to sampling and keeps latch storage.
A kind of 3. output current counting circuit for flyback converter according to claim 2, which is characterized in that detecting Module includes first voltage follower, and positive input terminal is connected to the current output terminal of first voltage current converter；
First voltage follower output terminal and sampling keep latch the first storage capacitance one end between be connected with by The first switch of control signal driving, control signal are turned into the moment that the second state turns off main switch from first state, the One switch is synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is converted into and is closed by first voltage follower Power off flow valuve IOFFCorresponding voltage sense signal is stored in the first storage capacitance.
A kind of 4. output current counting circuit for flyback converter according to claim 2, which is characterized in that detecting Module includes second voltage follower, and positive input terminal is connected to the current output terminal of first voltage current converter；
Second voltage follower output terminal and sampling keep latch the second storage capacitance one end between be connected with by The second switch of lead-edge-blanking signal driving, ahead of the curve blanking signal be turned into the moment of the second state from first state, second Switch is synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is converted into and blanking by second voltage follower Current value ILEBCorresponding voltage sense signal is stored in the second storage capacitance.
A kind of 5. output current counting circuit for flyback converter according to claim 1, which is characterized in that electric current The second voltage current converter that sum unit has corresponds to cut-off current value I by sampling holding latch storageOFFElectricity Pressure sensing signal recovery is converted into from the current output terminal outflow of second voltage current converter and cut-off current value IOFFIt is equivalent Electric current；
The tertiary voltage current converter that electric current sum unit has corresponds to blanking electric current by sampling holding latch storage Value ILEBVoltage sense signal recovery be converted into from the outflow of the current output terminal of tertiary voltage current converter and blanking electric current Value ILEBEquivalent electric current；
The electric current convergence flow that second, third voltage current adapter each exports crosses both second, third voltage current adapters Current output terminal interconnection at common node and ground terminal between one summation resistance, and electric current sum unit have one The positive input terminal of a tertiary voltage follower is connected at the common node, the voltage V for exporting tertiary voltage followerTRSDeng In (ILEB+IOFF) it is multiplied by the resistance value R of summation resistanceSUM。
A kind of 6. output current counting circuit for flyback converter according to claim 5, which is characterized in that output Grade includes one the 3rd switch, and the input terminal of the 3rd switch receives the electricity converted by summation electric current of electric current sum unit output Press VTRS, the 3rd switch output terminal be then grounded；
It is each main switch-off period T in the preset time period in switch periodsOFFStage disconnects the 3rd switch, with By voltage VTRSThe output terminal of output stage is transferred to, but makes the 3rd switch connection within each switch periods remaining time to incite somebody to action Voltage VTRSIt is discharged into ground terminal and forbids output stage receiving voltage VTRS。
A kind of 7. output current counting circuit for flyback converter according to claim 6, which is characterized in that flyback When converter enters electric current continuous CCM patterns, section T when offOFF3rd switch is disconnected with by voltage VTRSIt is transferred to output The output terminal of grade, but connecting period TONThe 3rd switch connection is made to forbid output stage receiving voltage VTRS, the voltage of output stage output VFMeet following functional relation：
<mrow> <msub> <mi>V</mi> <mi>F</mi> </msub> <mo>=</mo> <msub> <mi>V</mi> <mrow> <mi>T</mi> <mi>R</mi> <mi>S</mi> </mrow> </msub> <mo>&amp;times;</mo> <mfrac> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> <mrow> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>N</mi> </mrow> </msub> <mo>+</mo> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> </mrow> </mfrac> <mo>.</mo> </mrow>
A kind of 8. output current counting circuit for flyback converter according to claim 6, which is characterized in that flyback When converter enters discontinuous current DCM patterns, section T when offOFF3rd switch is disconnected with by voltage VTRSIt is transferred to output The output terminal of grade, but connecting period TONWith dead time TDThe 3rd switch connection is made to forbid output stage receiving voltage VTRS, output The voltage V of grade outputFMeet following functional relation：
<mrow> <msub> <mi>V</mi> <mi>F</mi> </msub> <mo>=</mo> <msub> <mi>V</mi> <mrow> <mi>T</mi> <mi>R</mi> <mi>S</mi> </mrow> </msub> <mo>&amp;times;</mo> <mfrac> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> <mrow> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>N</mi> </mrow> </msub> <mo>+</mo> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> <mo>+</mo> <msub> <mi>T</mi> <mi>D</mi> </msub> </mrow> </mfrac> <mo>.</mo> </mrow>
9. a kind of output current counting circuit for flyback converter according to claim 7 or 8, which is characterized in that If the number of turn N of armature windingPWith the number of turn N of secondary windingsSThe ratio between be equal to n, then flyback converter be transferred to the output current of load IOMeet following functional relation：
<mrow> <msub> <mi>I</mi> <mi>O</mi> </msub> <mo>=</mo> <mi>n</mi> <mo>&amp;times;</mo> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> <mo>&amp;times;</mo> <mfrac> <msub> <mi>V</mi> <mi>F</mi> </msub> <msub> <mi>R</mi> <mrow> <mi>S</mi> <mi>U</mi> <mi>M</mi> </mrow> </msub> </mfrac> <mo>.</mo> </mrow>
10. a kind of output current counting circuit for flyback converter according to claim 6, which is characterized in that by A resistance between the input terminal of the 3rd switch and the output terminal of tertiary voltage follower is connected to switch with being connected to the 3rd Input terminal and ground terminal between a capacitance form a sampling hold circuit, by be connected to the 3rd switch input terminal and A resistance between the output port of output stage and a capacitance being connected between the output port of output stage and ground terminal Form a filter circuit.
11. a kind of output current counting circuit for flyback converter according to claim 6, which is characterized in that patrol Volume control unit include a positive input terminal be connected to main switch drain electrode end the 4th voltage follower and including a capacitance, Connection is there are one resistance between the output terminal of one end of capacitance and the 4th voltage follower, and the other end of capacitance is connected to ground connection End；
Logic control element is also connected to the comparator of unearthed one end of capacitance, inverting input comprising normal phase input end The anode for the voltage source that reference voltage is provided is connected to, the cathode of voltage source is connected to the output of the 4th voltage follower End, the output terminal of comparator are connected to the set end of a rest-set flip-flop in logic control element；
The output of rest-set flip-flop is set to high level by the high level comparative result of comparator, is touched by the trailing edge of control signal The output of rest-set flip-flop is reset to low level by the high level pulse that hair generates, the 3rd switch of output control of the rest-set flip-flop Shut-off is connected.
12. a kind of output current counting circuit for flyback converter according to claim 11, which is characterized in that Under CCM patterns, in conducting period TONThe rest-set flip-flop exports control terminal of the high level to the 3rd switch, connects the 3rd switch；With And
Section T when offOFFThe rest-set flip-flop exports control terminal of the low level to the 3rd switch, the 3rd switch of shut-off；
Output stage is in each cycle by voltage VTRSWith { TOFF÷(TON+TOFF) preset ratio output.
13. a kind of output current counting circuit for flyback converter according to claim 11, which is characterized in that Under DCM patterns, in conducting period TONWith dead zone period TDThe rest-set flip-flop exports control terminal of the high level to the 3rd switch, connects 3rd switch；And
Section T when offOFFThe rest-set flip-flop exports control terminal of the low level to the 3rd switch, the 3rd switch of shut-off；
Output stage is in each cycle by voltage VTRSWith { TOFF÷(TON+TOFF+TD) preset ratio output.
14. a kind of output current counting circuit for flyback converter according to claim 11, which is characterized in that patrol Volume control unit further include that an output terminal is connected to rest-set flip-flop reset terminal with door, with an input terminal of door and another Phase inverter to make them form monostable flipflops there are one connections between input terminal；
Inversion signal of the control signal after another inverter is fed to and an input terminal of door and is conveyed To the input terminal for the phase inverter being connected between two input terminals of door, so as to be triggered at the time of the trailing edge of control signal The output of rest-set flip-flop is clamped down on low level by the output signal that a high level pulse is generated with door.
15. a kind of output current counting circuit for flyback converter according to claim 1, which is characterized in that In each cycle, at the time of end at the time of setting the main switch to connect to the effective status of lead-edge-blanking signal between continuity when Between, the logic state equal to control signal is crossed to primary current at the time of overturning preparation shut-off main switch occurs and is flushed to peak-peak At the time of between time delay.
A kind of 16. method for the output current for calculating flyback converter, which is characterized in that comprise the following steps：
Flow through the primary current on an inductive reactance with primary windings connected in series using the detection of detecting module, and for It the moment that the main switch that control armature winding is switched on or switched off is turned off by a control signal, detects and flows through inductive reactance Cut-off current value IOFFAnd for shield primary current starting spike a lead-edge-blanking signal effective shape The moment that state terminates detects the blanking current value I for flowing through inductive reactanceLEB；
By cut-off current value IOFFInformation and blanking current value ILEBInformation stores to a sampling and keeps latch；
Using an electric current sum unit to cut-off current value IOFFWith blanking current value ILEBCarry out read group total；
By cut-off current value IOFFWith blanking current value ILEBThe voltage that the summation electric current that summation obtains is converted is within each cycle It is exported according to a default proportionate relationship in cycle in an output stage；
Nationality judges that output stage receives the voltage being converted by summation electric current in one cycle by a logic control element One preset time period accounts for cycle ratio, and logic control element controls preset time period reception of the output stage in each cycle to ask With the voltage of electric current conversion but output stage is forbidden to receive summation in remaining time of each cycle in addition to the preset time period The voltage of electric current conversion.
17. according to the method for claim 16, which is characterized in that detecting module has first voltage current converter, adopts Collect for characterize primary current size across the voltage sense signal on inductive reactance, voltage sense signal is converted into flowing through It is connected to the intermediate current of a transfer resistance between the current output terminal and ground terminal of first voltage current converter；
In the moment of main switch shut-off, detecting module by the moment be applied to voltage conversion on transfer resistance into cut-off current Value IOFFCorresponding voltage sense signal is conveyed to sampling and keeps latch storage；
The moment is applied to the voltage on transfer resistance by the moment that the effective status of blanking signal terminates ahead of the curve, detecting module It is converted into and blanking current value ILEBCorresponding voltage sense signal is conveyed to sampling and keeps latch storage.
18. according to the method for claim 17, which is characterized in that detecting module includes first voltage follower, just defeated Enter the current output terminal that end is connected to first voltage current converter；
First voltage follower output terminal and sampling keep latch the first storage capacitance one end between be connected with by The first switch of control signal driving, control signal are turned into the moment that the second state turns off main switch from first state, the One switch is synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is converted into and is closed by first voltage follower Power off flow valuve IOFFCorresponding voltage sense signal is stored in the first storage capacitance.
19. according to the method for claim 17, which is characterized in that detecting module includes second voltage follower, just defeated Enter the current output terminal that end is connected to first voltage current converter；
Second voltage follower output terminal and sampling keep latch the second storage capacitance one end between be connected with by The second switch of lead-edge-blanking signal driving, ahead of the curve blanking signal be turned into the moment of the second state from first state, second Switch is synchronously turned off, and the voltage that intermediate current generates on transfer resistance this moment is converted into and blanking by second voltage follower Current value ILEBCorresponding voltage sense signal is stored in the second storage capacitance.
20. according to the method for claim 16, which is characterized in that the second voltage electric current conversion that electric current sum unit has Device corresponds to cut-off current value I by sampling holding latch storageOFFVoltage sense signal recovery be converted into from second voltage Current converter current output terminal outflow with cut-off current value IOFFEquivalent electric current；
The tertiary voltage current converter that electric current sum unit has corresponds to blanking electric current by sampling holding latch storage Value ILEBVoltage sense signal recovery be converted into from the outflow of the current output terminal of tertiary voltage current converter and blanking electric current Value ILEBEquivalent electric current；
The electric current convergence flow that second, third voltage current adapter each exports crosses both second, third voltage current adapters Current output terminal interconnection at common node and ground terminal between one summation resistance, and electric current sum unit have one The positive input terminal of a tertiary voltage follower is connected at the common node, the voltage V for exporting tertiary voltage followerTRSDeng In (ILEB+IOFF) it is multiplied by the resistance value R of summation resistanceSUM。
21. according to the method for claim 20, which is characterized in that output stage includes one the 3rd switch, the 3rd switch Input terminal receives the voltage V converted by summation electric current that electric current sum unit is calculated and exportedTRS, the output terminal of the 3rd switch Then it is grounded；
Preset time period is main switch-off period T in each switch periodsOFFStage disconnects the 3rd switch, by voltage VTRSThe output terminal of output stage is transferred to, but makes within each switch periods remaining time the 3rd switch connection with by voltage VTRS It is discharged into ground terminal and forbids output stage receiving voltage VTRS。
22. according to the method for claim 21, which is characterized in that when flyback converter enters electric current continuous CCM patterns, Turn off period TOFF3rd switch is disconnected with by voltage VTRSThe output terminal of output stage is transferred to, but is connecting period TONMake the 3rd Switch connection forbids output stage receiving voltage VTRS, the voltage V of output stage outputFMeet following functional relation：
<mrow> <msub> <mi>V</mi> <mi>F</mi> </msub> <mo>=</mo> <msub> <mi>V</mi> <mrow> <mi>T</mi> <mi>R</mi> <mi>S</mi> </mrow> </msub> <mo>&amp;times;</mo> <mfrac> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> <mrow> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>N</mi> </mrow> </msub> <mo>+</mo> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> </mrow> </mfrac> <mo>.</mo> </mrow>
23. according to the method for claim 21, which is characterized in that when flyback converter enters discontinuous current DCM patterns, Turn off period TOFF3rd switch is disconnected with by voltage VTRSThe output terminal of output stage is transferred to, but is connecting period TONAnd dead zone Time TDThe 3rd switch connection is made to forbid output stage receiving voltage VTRS, the voltage V of output stage outputFMeet following functional relation：
<mrow> <msub> <mi>V</mi> <mi>F</mi> </msub> <mo>=</mo> <msub> <mi>V</mi> <mrow> <mi>T</mi> <mi>R</mi> <mi>S</mi> </mrow> </msub> <mo>&amp;times;</mo> <mfrac> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> <mrow> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>N</mi> </mrow> </msub> <mo>+</mo> <msub> <mi>T</mi> <mrow> <mi>O</mi> <mi>F</mi> <mi>F</mi> </mrow> </msub> <mo>+</mo> <msub> <mi>T</mi> <mi>D</mi> </msub> </mrow> </mfrac> <mo>.</mo> </mrow>
24. the method according to claim 22 or 23, which is characterized in that set the number of turn N of armature windingPWith secondary windings Number of turn NSThe ratio between be equal to n, then flyback converter be transferred to the output current I of loadOMeet following functional relation：
<mrow> <msub> <mi>I</mi> <mi>O</mi> </msub> <mo>=</mo> <mi>n</mi> <mo>&amp;times;</mo> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> <mo>&amp;times;</mo> <mfrac> <msub> <mi>V</mi> <mi>F</mi> </msub> <msub> <mi>R</mi> <mrow> <mi>S</mi> <mi>U</mi> <mi>M</mi> </mrow> </msub> </mfrac> <mo>.</mo> </mrow>
25. according to the method for claim 21, which is characterized in that by the input terminal and tertiary voltage that are connected to the 3rd switch A resistance between the output terminal of follower and a capacitance structure being connected between the input terminal and ground terminal of the 3rd switch Into a sampling hold circuit, by a resistance being connected between the input terminal of the 3rd switch and the output port of output stage and A capacitance being connected between the output port of output stage and ground terminal forms a filter circuit.
26. according to the method for claim 21, which is characterized in that logic control element is connected to including a positive input terminal 4th voltage follower of the drain electrode end of main switch and including a capacitance, the output of one end of capacitance and the 4th voltage follower Connection is there are one resistance between end, and the other end of capacitance is connected to ground terminal；
Logic control element is also connected to the comparator of unearthed one end of capacitance, the reverse phase of comparator comprising normal phase input end Input terminal is connected to the anode for the voltage source for providing reference voltage, and the cathode of voltage source is connected to the output of the 4th voltage follower End, the output terminal of comparator are connected to the set end of a rest-set flip-flop in logic control element；
The output of rest-set flip-flop is set to high level by the high level comparative result of comparator, is touched by the trailing edge of control signal The output of rest-set flip-flop is reset to low level by the high level pulse that hair generates, the 3rd switch of output control of the rest-set flip-flop Shut-off is connected.
27. according to the method for claim 26, which is characterized in that in ccm mode, in conducting period TONThe rest-set flip-flop Control terminal of the high level to the 3rd switch is exported, connects the 3rd switch；And
Section T when offOFFThe rest-set flip-flop exports control terminal of the low level to the 3rd switch, the 3rd switch of shut-off；
Output stage is in each cycle by voltage VTRSWith { TOFF÷(TON+TOFF) preset ratio output.
28. according to the method for claim 26, which is characterized in that in dcm mode, in conducting period TONWith the dead zone period TDThe rest-set flip-flop exports control terminal of the high level to the 3rd switch, connects the 3rd switch；And
Section T when offOFFThe rest-set flip-flop exports control terminal of the low level to the 3rd switch, the 3rd switch of shut-off；
Output stage is in each cycle by voltage VTRSWith { TOFF÷(TON+TOFF+TD) preset ratio output.
29. according to the method for claim 26, which is characterized in that logic control element further includes an output terminal and is connected to Rest-set flip-flop reset terminal with door, being connected between an input terminal of door and another input terminal makes them there are one phase inverter Form monostable flipflop；
Inversion signal of the control signal after another inverter is fed to and an input terminal of door and is conveyed To the input terminal for the phase inverter being connected between two input terminals of door, triggering should be at the time of the trailing edge of control signal The output of rest-set flip-flop is clamped down on low level by the output signal that door generates a high level pulse.
30. according to the method for claim 16, which is characterized in that within each cycle, at the time of main switch connection is set Perdurabgility between at the time of end to the effective status of lead-edge-blanking signal, the logic state equal to control signal are turned over Turn to prepare the time delay between crossing to primary current at the time of being flushed to peak-peak at the time of shut-off main switch.
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