TW201108330A - Method of producing semiconductor device, and semiconductor device - Google Patents

Method of producing semiconductor device, and semiconductor device Download PDF

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TW201108330A
TW201108330A TW099109656A TW99109656A TW201108330A TW 201108330 A TW201108330 A TW 201108330A TW 099109656 A TW099109656 A TW 099109656A TW 99109656 A TW99109656 A TW 99109656A TW 201108330 A TW201108330 A TW 201108330A
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gate
semiconductor device
region
drain
source
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TW099109656A
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Chinese (zh)
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TWI467664B (en
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Toru Imori
Junichi Ito
Hajime Momoi
Tomohiro Shibata
Shuji Ikeda
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Nippon Mining Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28537—Deposition of Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A method of producing a semiconductor device, able to form a source/drain of a Schottky junction (FET) with simple steps and able to improve the device characteristics. A gate is formed on an element region defined in a silicon substrate layer by element isolation regions (first step), the silicon substrate is etched by self-alignment using the gate and the element isolation regions as masks (second step), and an insulating film is formed on the side surfaces of the gate (third step). Then, a metal film acting as the source/drain is selectively formed on the etching region of the silicon substrate by electroless plating (fourth step).

Description

201108330 六、發明說明 【發明所屬之技術領域】 本發明是有關半導體裝置的製造方法及半導體裝置， 特別是有關在源極/汲極利用蕭特基接合（Schottky barrier junction)之場效電晶體的製造方法。 【先前技術】 以往，在一片的基板上製作多數的電路元件（例如電 晶體）與配線的半導體裝置（積體電路）爲人所知。構成此 半導體裝置的半導體元件，例如有場效電晶體（FET : FieldEffectTransistor)爲人所知，其係具備：在矽基板表 層所被劃成的元件區域中隔著通道區域來形成的一對源極 /汲極、及在通道區域上隔著閘極絕緣膜來形成多晶矽層 的閘極。 在半導體裝置的領域中，爲了實現高速化.高集成 化，而被要求半導體元件的微細化，例如縮短F ET的閘 極長，或使閘極絕緣膜形成更薄，藉此來謀求微細化。 並且，不是以在矽基板摻雜雜質而形成的擴散層來構 成FET的源極/汲極，而使藉由金屬來構成之技術被提案 (例如非專利文獻1)。若根據此技術，則相較於以擴散層 來構成源極/汲極時，可容易形成淺的接合，且壓倒性地 成爲低電阻。 如此以金屬/矽基板的蕭特基接合來實現源極/汲極之 FET是被稱爲蕭特基接合FET。 201108330 以下，參照圖面來說明有關以往被利用之 FET的製造方法的典型例。 圖2是顯示有關以往的蕭特基接合FET 之一例的說明圖。 圖2是顯示有關在矽基板201上形成閘極 源極/汲極的形成。亦即，在圖2A所示的前段 的半導體裝置的製造工程在矽基板101上形成 FET20的閘極212° 另外，閘極 212是以閘極絕緣膜 203 2 04、覆蓋閘極電極的絕緣膜205所構成。在 極204是藉由金屬或具有金屬的導電性的仆 Ni，Co，Pt或該等的合金）所形成，用以控制 實現所謂閘極的任務之電極。 圖2A是顯示在矽基板201的全面形成 203、閘極電極204及絕緣膜205之後，藉 程，以光阻劑圖案206作爲遮罩來除去閘極電 緣膜205的不要部分之狀態。 如圖2 A所示，在除去閘極電極2 0 4及絕 後，再除去閘極絕緣膜203。然後，藉由自我 定的深度蝕刻矽基板201(圖2B)。在此蝕刻區 上部形成源極/汲極。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device and a semiconductor device, and more particularly to a field effect transistor using a Schottky barrier junction at a source/drain. Production method. [Prior Art] Conventionally, a semiconductor device (integrated circuit) in which a large number of circuit elements (for example, a transistor) and a wiring are formed on one substrate is known. The semiconductor element constituting the semiconductor device is, for example, a field effect transistor (FET: Field Effect Transistor), and includes a pair of sources formed by a channel region in an element region in which the surface layer of the germanium substrate is formed. A pole/drain, and a gate of a polysilicon layer formed on the channel region via a gate insulating film. In the field of semiconductor devices, in order to achieve high speed and high integration, it is required to reduce the size of the semiconductor element, for example, to shorten the gate length of F ET or to form a thinner gate insulating film, thereby achieving miniaturization. . Further, a technique in which a source/drain of an FET is formed by a diffusion layer formed by doping impurities on a germanium substrate is used, and a technique of forming a metal is proposed (for example, Non-Patent Document 1). According to this technique, when the source/drain is formed by the diffusion layer, the shallow junction can be easily formed and the resistance is overwhelming. The FET that implements the source/drain in such a Schottky junction with a metal/germanium substrate is called a Schottky junction FET. 201108330 Hereinafter, a typical example of a method of manufacturing a conventionally used FET will be described with reference to the drawings. FIG. 2 is an explanatory view showing an example of a conventional Schottky junction FET. Fig. 2 is a view showing formation of a gate source/drain on the germanium substrate 201. That is, the gate electrode 212 of the FET 20 is formed on the germanium substrate 101 in the manufacturing process of the semiconductor device in the preceding stage shown in FIG. 2A. Further, the gate 212 is a gate insulating film 203 2 04, an insulating film covering the gate electrode. 205 constitutes. The pole 204 is formed by a metal or a metal-positive Ni, Co, Pt or alloy thereof to control the electrode for achieving the so-called gate. Fig. 2A shows a state in which the unnecessary portion of the gate electrode film 205 is removed by using the photoresist pattern 206 as a mask after the overall formation 203, the gate electrode 204, and the insulating film 205 of the germanium substrate 201 are performed. As shown in Fig. 2A, the gate insulating film 203 is removed after the gate electrode 220 is removed and thereafter. Then, the substrate 201 (Fig. 2B) is etched by self-determination. A source/drain is formed on the upper portion of the etched region.

其次，剝離光阻劑圖案206之後，在基板 形成矽氮化膜207(圖2C)。然後，對此矽氮化 異方性鈾刻的回蝕，藉此在閘極2 1 2的側I 蕭特基接合 的製造過程 2 1 2之後的 ，藉由一般 蕭特基接合 、閘極電極 此，閘極電 :合物（例如 電子的移動 閘極絕緣膜 由光蝕刻工 極2 04及絕 緣膜205之 整合僅以所 域2 0 1 a的 全面，例如 膜207進行 S形成側壁 -6 - 201108330 207a(圖 2D)。 在形成側壁 207a 之後，藉由光蝕刻微影 (Photolithography)工程來形成以矽基板201的蝕k區域 201a能夠露出的方式設置開口部 208a的光阻劑圖案 2 08 (圖 2E)。藉由濺射等的物理氣相成長（PVD : PhysicalVaporDeposition)來將金屬膜（例如、Ni)形成於全 面（圖2F)，剝離光阻劑圖案208 (圖2G)。 可藉由以上的工程來取得蕭特基接合FET20。形成於 閘極212的兩側之金屬膜209會成爲源極/汲極210, 211，在與矽基板201之間形成蕭特基接合。 [先行技術文獻] [非專利文獻] [非專利文獻1]木下敦寛，其他2名，「雜質偏析蕭 特基接合電晶體j ，東芝review、Vol.59No.1 2(2004) 【發明內容】 (發明所欲解決的課題） 然而，就上述以往的蕭特基接合FET的製造方法而 言，爲了在矽基板201的蝕刻區域201a形成源極/汲極 2 1 0，2 1 1，需要光蝕刻微影工程等複雜的工程。因此，對 於謀求半導體裝置的良品率的提升或低價格化不利。 又，由於藉由PVD來使金屬膜209蒸鍍於矽基板201 的蝕刻區域201a，因此在矽基板201與金屬膜209的界 面容易形成凹凸，恐有導致裝置特性的降低之虞。 201108330 本發明的目的是在於提供一種可用簡單的工程來形成 蕭特基接合FET的源極/汲極的同時，可提升裝置特性之 半導體裝置的製造方法。 (用以解決課題的手段） 爲了達成上述目的，請求項1所記載的發明爲一種半 導體裝置的製造方法，其特徵係具備： 在藉由元件分離區域來劃成於矽基板表層的元件區域 中形成閘極之第1工程： 以上述閘極及元件分離區域作爲遮罩，藉由自我整合 來蝕刻上述矽基板之第2工程； 在上述閘極的側面形成絕緣膜之第3工程；及 在上述矽基板的蝕刻區域，藉由無電解電鍍法來選擇 性形成成爲源極/汲極的金屬膜之第4工程。 請求項2所記載的發明，係於請求項1所記載的半導 體裝置的製造方法中，上述金屬膜爲由金、白金、銀、 銅、鈀、鎳、鈷、釕的群中所選擇的一種金屬或組合二種 以上的合金或至少含一種的合金。 請求項3所記載的發明爲一種半導體裝置，係具備： 在藉由元件分離區域來劃成於矽基板表層的元件區域中所 形成的閘極、及以上述閘極及元件分離區域作爲遮罩來蝕 刻之上述矽基板的蝕刻區域中所形成的源極/汲極，之半 導體元件，其特徵爲： 上述源極.汲極係藉由無電解電鏟法來選擇性形成的 -8 - 201108330 金屬膜所構成。 請求項4所記載的發明，係於請求項3所記載的半導 體裝置中’上述金屬膜爲由金、白金、銀、銅、絕、鎮、 鈷、釕的群中所選擇的一種金屬或組合二種以上的合金或 至少含一種的合金。 [發明的效果] 若根據本發明’則因爲形成蕭特基接合FET的源極/ 汲極之工程被簡素化’所以可謀求半導體裝置的良品率的 提升或低價格化。具體而言’可省略以往的光蝕刻微影工 程。 又’由於不是PVD，而是藉由無電解電鍍法來形成成 爲源極/汲極的金屬膜，所以與矽基板的界面平滑，可期 待裝置特性的提升。 【實施方式】 以下，參照圖面來詳細說明有關本發明的實施形態。 圖1是顯示有關本實施形態的蕭特基接合FET的製 造過程之一例的說明圖。 圖1是顯示有關在矽基板1 〇 1上形成閘極111之後的 源極/汲極的形成。 亦即，在圖1Α所示的前段，藉由一般的半導體裝置 的製造工程在矽基板101上形成蕭特基接合FET〗〇的閘 極 1 1 1 〇 -9 - 201108330 簡單說明，在P型矽基板101上的所定區域形成由深 度300〜40〇nm的矽氧化膜所構成的元件分離區域102。 藉由此元件分離區域1 02來劃成元件區域。 在基板全面形成厚度 5nm的閘極絕緣膜（氧化 膜）1〇3，其上形成由厚度100〜150nm的多結晶矽、金屬 膜或矽化物膜所構成的閘極電極1 04及絕緣膜1 05。然 後，藉由光蝕刻工程，以光阻劑圖案1 06作爲遮罩，剩下 成爲閘極的部分來除去閘極電極104及絕緣膜105。 藉由以上的工程來取得圖1 A所示的狀態。 如圖1 A所示，在除去閘極電極1 04及絕緣膜1 05之 後，再除去閘極絕緣膜1 〇3。然後，藉由自我整合僅以所 定的深度（例如10〜100nm)蝕刻矽基板101(圖1B)。在此 蝕刻區域1 〇1 a形成源極/汲極。 在此，所謂自我整合的蝕刻是意指不使用光罩，利用 既存的圖案（作爲遮罩）來蝕刻加工。在本實施形態是以閘 極1 1 1及隔絕的氧化膜（元件分離區域）1 02作爲遮罩來蝕 刻源極/汲極區域，因此成爲自我整合的餓刻。 其次，在剝離光阻劑圖案1 06後，在基板全面形成厚 度10nm以下的矽氮化膜1〇7(圖1C)。然後，對此矽氮化 膜107進行異方性蝕刻的回蝕（etch back)，藉此在閘極 1 1 1的側面形成側壁1 07a(圖1 D)。 另外，到此工程爲止是與以往例（參照圖2)相同。 在形成側壁1 07 a之後，藉由無電解電鍍法在蝕刻區 域1 〇 1 a選擇性形成厚度1 0〜1 〇 〇 _的金屬膜（例如 -10 - 201108330Next, after the photoresist pattern 206 is peeled off, a tantalum nitride film 207 is formed on the substrate (Fig. 2C). Then, the etch back of the yttrium-nitride anisotropic uranium engraved, whereby the manufacturing process 2 1 2 of the side I Schottky junction of the gate 2 1 2, by the general Schottky junction, the gate Electrode, the gate electrode: (for example, the moving gate insulating film of electrons is integrated by the photoetching electrode 2 04 and the insulating film 205 only by a comprehensive range of 2 0 1 a, for example, the film 207 is S to form a sidewall - 6 - 201108330 207a (Fig. 2D) After forming the side wall 207a, the photoresist pattern 2 in which the opening portion 208a is provided in such a manner that the etched k region 201a of the ruthenium substrate 201 can be exposed is formed by photolithography 08 (Fig. 2E) A metal film (e.g., Ni) is formed in a full range by physical vapor phase growth (PVD: Physical Vapor Deposition) such as sputtering (Fig. 2F), and the photoresist pattern 208 is peeled off (Fig. 2G). The Schottky junction FET 20 is obtained by the above process. The metal film 209 formed on both sides of the gate 212 becomes the source/drain electrodes 210, 211, and forms a Schottky junction with the germanium substrate 201. [Professional Literature] [Non-Patent Document] [Non-Patent Document 1] Two of them, "Impurity segregation Schottky junction transistor j, Toshiba review, Vol. 59 No. 1 2 (2004) [Summary of the invention] However, the conventional Schottky junction FET described above In the manufacturing method, in order to form the source/drain electrodes 2 1 0, 21 1 in the etching region 201a of the germanium substrate 201, complicated processes such as photolithography lithography are required. Therefore, in order to achieve a yield of the semiconductor device, Further, since the metal film 209 is vapor-deposited on the etching region 201a of the ruthenium substrate 201 by PVD, unevenness is likely to be formed at the interface between the ruthenium substrate 201 and the metal film 209, which may cause device characteristics. The purpose of the present invention is to provide a method for manufacturing a semiconductor device which can improve the characteristics of a device while forming a source/drain of a Schottky junction FET by simple engineering. In order to achieve the above object, the invention according to claim 1 is a method of manufacturing a semiconductor device, characterized in that: the substrate is separated into a germanium substrate by an element isolation region The first step of forming a gate in the element region: the second process of etching the germanium substrate by self-integration using the gate and the element isolation region as a mask; and forming the third insulating film on the side surface of the gate And a fourth process of selectively forming a metal film to be a source/drain by an electroless plating method in the etching region of the germanium substrate. The invention described in claim 2 is described in claim 1 In the method for producing a semiconductor device, the metal film is one selected from the group consisting of gold, platinum, silver, copper, palladium, nickel, cobalt, and rhodium, or a combination of two or more alloys or at least one alloy. The invention according to claim 3 is a semiconductor device comprising: a gate electrode formed in an element region of the surface layer of the germanium substrate by the element isolation region; and a gate region and the element isolation region as a mask a semiconductor device for etching a source/drain formed in an etched region of the germanium substrate, wherein the source and drain electrodes are selectively formed by an electroless shovel method -8 - 201108330 Made of a metal film. The invention according to claim 3, wherein the metal film is a metal or a combination selected from the group consisting of gold, platinum, silver, copper, lanthanum, cobalt, and lanthanum. Two or more alloys or alloys containing at least one. [Effects of the Invention] According to the present invention, since the process of forming the source/drain of the Schottky junction FET is simplified, the yield of the semiconductor device can be improved or reduced. Specifically, the conventional photo-etching lithography project can be omitted. Further, since the metal film which becomes the source/drain is formed by the electroless plating method because it is not PVD, the interface with the ruthenium substrate is smooth, and the characteristics of the device can be improved. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Fig. 1 is an explanatory view showing an example of a manufacturing process of a Schottky junction FET according to the present embodiment. Fig. 1 is a view showing the formation of a source/drain after forming a gate 111 on a germanium substrate 1 〇 1. That is, in the front stage shown in FIG. 1A, the gate of the Schottky junction FET is formed on the germanium substrate 101 by the fabrication process of a general semiconductor device. 1 1 〇-9 - 201108330 Briefly, in the P-type An element isolation region 102 composed of a tantalum oxide film having a depth of 300 to 40 nm is formed in a predetermined region on the germanium substrate 101. The element region is drawn by the element separation region 102. A gate insulating film (oxide film) 1〇3 having a thickness of 5 nm is formed on the substrate, and a gate electrode 104 and an insulating film 1 composed of a polycrystalline germanium, a metal film or a germanide film having a thickness of 100 to 150 nm are formed thereon. 05. Then, by the photo-etching process, the photoresist pattern 106 is used as a mask, and the gate portion is removed to remove the gate electrode 104 and the insulating film 105. The state shown in FIG. 1A is obtained by the above engineering. As shown in Fig. 1A, after the gate electrode 104 and the insulating film 156 are removed, the gate insulating film 1 〇 3 is removed. Then, the germanium substrate 101 is etched only at a predetermined depth (e.g., 10 to 100 nm) by self-integration (Fig. 1B). Here, the etched region 1 〇 1 a forms a source/drain. Here, the self-integration etching means etching without using a photomask and using an existing pattern (as a mask). In the present embodiment, the source electrode/drain region is etched by the gate electrode 11 1 and the isolated oxide film (element separation region) 102 as a mask, and thus the self-integration is hungry. Next, after the photoresist pattern 106 is peeled off, a tantalum nitride film 1〇7 having a thickness of 10 nm or less is formed over the entire substrate (Fig. 1C). Then, the tantalum nitride film 107 is subjected to an etch back of the anisotropic etching, whereby the side wall 107a is formed on the side surface of the gate electrode 112 (Fig. 1D). In addition, this project is the same as the conventional example (refer to FIG. 2). After the sidewalls 07a are formed, a metal film having a thickness of 1 0 to 1 〇 〇 _ is selectively formed in the etching region 1 〇 1 a by electroless plating (for example, -10 - 201108330)

Ni)108(圖1E)。若利用無電解電鍍法，則在矽上是藉由矽 的自觸媒反應來形成金屬。因此，只在砂基板1〇1的餘刻 區域101a形成有金屬膜1〇8。 具體而言，將以硫酸鎳0.08M、檸檬酸0.10M、次膦 酸0.20M爲主成分的無電解鎳電鍍液調整成pH = 9 5。然 後，在此無電解鎳電鍍液中使半導體裝置10以70°c浸漬 2分鐘。藉此，形成厚度約50nm的鎳膜（金屬膜）1〇8。 另外’雖是顯示有關使用鎳的情況作爲藉由無電解電 鍍法來形成的金屬膜之一例，但例如可使用由金、白金、 銀、銅、鈀、鈷、釕的群中所選擇的一種金屬或組合二種 以上的合金或至少含一種的合金。若爲該等的金屬，則可 藉由無電解電鍍法來容易地形成金屬膜，也適合作爲源極 /汲極材料。 可藉由以上的工程來取得蕭特基接合FET10。形成於 閘極111的兩側的金屬膜108會成爲源極/汲極1〇9, 1 1 〇，在與矽基板丨〇〗之間形成蕭特基接合。 如上述般，本實施形態是藉由元件分離區域（1 02)在 矽基板（101)表層所被劃成的元件區域形成閘極（1 1 1)(第1 工程，圖1A)’以閘極（in)及元件分離區域（1〇2)作爲遮 罩，藉由自我整合來蝕刻矽基板（101)(第2工程，圖 1 B) ° 其次’在閘極（1 1 1 )的側面形成絕緣膜（砂氮化膜 107 ’側壁107a)(第3工程，圖1C，D)，在矽基板（101) 的蝕刻區域（l〇la)，藉由無電解電鍍法來選擇性形成成爲 -11 - 201108330 源極/汲極（109，110)的金屬膜（1〇8)(第4工程，圖IE)。 藉此，因爲形成蕭特基接合FET的源極/汲極之工程 被簡素化，所以可謀求半導體裝置的良品率的提升或低價 格化。具體而言，可省略以往的光蝕刻微影工程。 又，由於不是PVD，而是藉由無電解電鍍法來形成成 爲源極/汲極的金屬膜，所以與矽基板的界面平滑，可期 待裝置特性的提升。 在第4工程所形成的金屬膜（1〇8)是由金、白金、 銀、銅、鈀、鎳、鈷、釕的群中所選擇的一種金屬或組合 二種以上的合金或至少含一種的合金所構成。藉此，可藉 由無電解電鍍法來容易地形成源極/汲極。 以上，根據實施形態來具體說明有關本發明者的發 明，但本發明並非限於上述實施形態，亦可在不脫離其主 旨範圍內實施變更。 在上述實施形態是說明有關在矽基板上形成蕭特基接 合FET的情況，但在SOI(silicononinsulator)基板上形成 蕭特基接合FET時也可適用本發明。 此次所被揭示的實施形態是所有的點爲例示，並非限 於此。本發明的範圍非上述的說明，而是藉由申請專利範 圍來表示，包含與申請專利範圍同等的意義及範圍內的所 有變更。 【圖式簡單說明】 圖1A是顯示有關本實施形態的蕭特基接合FET的製 -12- 201108330 造過程之一例的說明圖。 圖1 B是顯示有關本實施形態的蕭特基接合FET的製 造過程之一例的說明圖。 圖1C是顯示有關本實施形態的蕭特基接合FEt的製 造過程之一例的說明圖。 圖1D是顯示有關本實施形態的蕭特基接合FET的製 造過程之一例的說明圖。 圖1E是顯示有關本實施形態的蕭特基接合FET的製 造過程之一例的說明圖。 圖2A是顯示有關以往的蕭特基接合FET的製造過程 之一例的說明圖。 圖2B是顯示有關以往的蕭特基接合FET的製造過程 之一例的說明圖。 圖2C是顯示有關以往的蕭特基接合FET的製造過程 之一例的說明圖。 圖2D是顯示有關以往的蕭特基接合FET的製造過程 之一例的說明圖。 圖2E是顯示有關以往的蕭特基接合FET的製造過程 之一例的說明圖。 圖2F是顯示有關以往的蕭特基接合FET的製造過程 之一例的說明圖。 圖2G是顯示有關以往的蕭特基接合FET的製造過程 之一例的說明圖。 -13- 201108330 【主要元件符號說明】 10 :蕭特基接合FET 1 0 1 :矽基板 102 :元件分離區域 103 :閘極絕緣膜 1 0 4 :閘極電極 1 〇 5 :絕緣膜 106 :光阻劑圖案 107 :矽氮化膜（絕緣膜） 108 :金屬膜 1 0 9，1 1 0 :源極/汲極 1 1 1 :閘極 -14-Ni) 108 (Fig. 1E). If electroless plating is used, the metal is formed by the self-catalytic reaction of ruthenium on the ruthenium. Therefore, the metal film 1〇8 is formed only in the remaining region 101a of the sand substrate 1〇1. Specifically, an electroless nickel plating solution containing nickel sulfate 0.08 M, citric acid 0.10 M, and phosphinic acid 0.20 M as a main component was adjusted to pH = 9.5. Then, the semiconductor device 10 was immersed at 70 ° C for 2 minutes in this electroless nickel plating solution. Thereby, a nickel film (metal film) 1〇8 having a thickness of about 50 nm was formed. Further, although an example in which nickel is used as an example of a metal film formed by electroless plating is used, for example, one selected from the group consisting of gold, platinum, silver, copper, palladium, cobalt, and rhodium may be used. Metal or a combination of two or more alloys or an alloy containing at least one. In the case of these metals, a metal film can be easily formed by electroless plating, and it is also suitable as a source/drain material. The Schottky junction FET 10 can be obtained by the above process. The metal film 108 formed on both sides of the gate 111 becomes a source/drain 1 〇9, 1 1 〇, and forms a Schottky junction with the 矽 substrate. As described above, in the present embodiment, the gate region (1 1 1) (the first project, FIG. 1A) is gated by the element isolation region (102) in the element region where the surface of the germanium substrate (101) is formed. The pole (in) and the element isolation region (1〇2) act as a mask to etch the germanium substrate (101) by self-integration (2nd project, Fig. 1 B) ° second 'on the side of the gate (1 1 1 ) An insulating film (the sidewall 107a of the sand nitride film 107') (third process, FIG. 1C, D) is formed, and the etching region (10a) of the germanium substrate (101) is selectively formed by electroless plating. -11 - 201108330 Metal film of the source/drain (109,110) (1〇8) (4th project, figure IE). As a result, since the process of forming the source/drain of the Schottky junction FET is simplified, it is possible to improve the yield of the semiconductor device or to lower the cost. Specifically, the conventional photo-etching lithography project can be omitted. Further, since the metal film which becomes the source/drain is formed by electroless plating instead of PVD, the interface with the ruthenium substrate is smooth, and the characteristics of the device can be improved. The metal film (1〇8) formed in the fourth engineering project is one selected from the group consisting of gold, platinum, silver, copper, palladium, nickel, cobalt, and rhenium, or a combination of two or more alloys or at least one type. Made up of alloys. Thereby, the source/drain can be easily formed by electroless plating. The invention has been described in detail with reference to the embodiments, but the invention is not limited thereto, and modifications may be made without departing from the spirit and scope of the invention. In the above embodiment, the case where the Schottky junction FET is formed on the germanium substrate is described. However, the present invention is also applicable to the case where a Schottky junction FET is formed on an SOI (siliconon insulator) substrate. The embodiments disclosed this time are all examples for illustration and are not limited thereto. The scope of the present invention is defined by the scope of the claims, and is intended to be [Brief Description of the Drawings] Fig. 1A is an explanatory view showing an example of the manufacturing process of the Schottky bonded FET of the present embodiment -12-201108330. Fig. 1B is an explanatory view showing an example of a manufacturing process of the Schottky junction FET according to the embodiment. Fig. 1C is an explanatory view showing an example of a manufacturing process of the Schottky junction FEt of the present embodiment. Fig. 1D is an explanatory view showing an example of a manufacturing process of the Schottky junction FET according to the embodiment. Fig. 1E is an explanatory view showing an example of a manufacturing process of the Schottky junction FET according to the embodiment. Fig. 2A is an explanatory view showing an example of a manufacturing process of a conventional Schottky junction FET. Fig. 2B is an explanatory view showing an example of a manufacturing process of a conventional Schottky junction FET. Fig. 2C is an explanatory view showing an example of a manufacturing process of a conventional Schottky junction FET. Fig. 2D is an explanatory view showing an example of a manufacturing process of a conventional Schottky junction FET. Fig. 2E is an explanatory view showing an example of a manufacturing process of a conventional Schottky junction FET. Fig. 2F is an explanatory view showing an example of a manufacturing process of a conventional Schottky junction FET. Fig. 2G is an explanatory view showing an example of a manufacturing process of a conventional Schottky junction FET. -13- 201108330 [Description of main component symbols] 10 : Schottky junction FET 1 0 1 : germanium substrate 102 : element isolation region 103 : gate insulating film 1 0 4 : gate electrode 1 〇 5 : insulating film 106 : light Resistor pattern 107: germanium nitride film (insulating film) 108: metal film 1 0 9, 1 1 0 : source/drain 1 1 1 : gate-14-

Claims (1)

201108330 七、申請專利範圍 1. 一種半導體裝置的製造方法，其特徵係具備： 在藉由元件分離區域來劃成於矽基板表層的元件區域 中形成閘極之第1工程； 以上述閘極及元件分離區域作爲遮罩，藉由自我整合 來蝕刻上述矽基板之第2工程： 在上述閘極的側面形成絕緣膜之第3工程；及 在上述矽基板的蝕刻區域，藉由無電解電鍍法來選擇 性形成成爲源極/汲極的金屬膜之第4工程。 2. 如申請專利範圍第1項之半導體裝置的製造方法， 其中，上述金屬膜爲由金、白金、銀、銅、鈀、鎳、鈷、 釕的群中所選擇的一種金屬或組合二種以上的合金或至少 含一種的合金。 3. —種半導體裝置’係具備：在藉由元件分離區域來 劃成於矽基板表層的元件區域中所形成的閘極、及以上述 閘極及元件分離區域作爲遮罩來蝕刻之上述矽基板的蝕刻 區域中所形成的源極/汲極，之半導體元件，其特徵爲： 上述源極·汲極係藉由無電解電鍍法來選擇性形成的 金屬膜所構成。 4. 如申請專利範圍第3項之半導體裝置，其中，上述 金屬膜爲由金、白金、銀、銅、鈀、鎳 '鈷、釕的群中所 選擇的一種金屬或組合二種以上的合金或至少含一種的合 金。 -15-201108330 VII. Patent Application No. 1. A method for manufacturing a semiconductor device, comprising: forming a gate in an element region defined by a device isolation region in a surface region of a germanium substrate; a second process of etching the germanium substrate by self-integration as a mask: a third process of forming an insulating film on a side surface of the gate electrode; and an electroless plating method in an etching region of the germanium substrate The fourth project to selectively form a metal film to be a source/drain. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film is one selected from the group consisting of gold, platinum, silver, copper, palladium, nickel, cobalt, and ruthenium. The above alloy or alloy containing at least one. 3. A semiconductor device comprising: a gate formed in an element region of a surface of a germanium substrate by an element isolation region; and the germanium etched by using the gate and the element isolation region as a mask A semiconductor element having a source/drain formed in an etching region of a substrate, wherein the source/drain is formed of a metal film selectively formed by electroless plating. 4. The semiconductor device according to claim 3, wherein the metal film is one selected from the group consisting of gold, platinum, silver, copper, palladium, nickel, cobalt, and lanthanum, or a combination of two or more alloys. Or at least one alloy. -15-
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