JP3423859B2 - Method for manufacturing field effect semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method for producing a field effect semiconductor <br/> equipment.

[0002]

2. Description of the Related Art In recent years, miniaturization of elements has been rapidly promoted for high integration and high speed of LSI (Large Scale Integrated Circuit). A proportional reduction rule (scaling rule) for appropriately reducing or increasing the element size and the parameters related thereto has been proposed as a method for realizing good element performance and circuit performance when the element is miniaturized.

However, in practice, it is difficult to change all the parameters so as to comply with the proportional reduction rule. In particular, the power supply voltage cannot be reduced in proportion to the element size due to the demand for the power supply voltage in the peripheral circuits.
Therefore, the device size is reduced with the power supply voltage kept constant, which is outside the proportional reduction rule.

As a result, in a field effect semiconductor device such as a metal-oxide film-semiconductor field effect transistor (hereinafter referred to as a MOS transistor), fluctuations in element characteristics due to hot carriers and gate oxidation are accompanied by miniaturization of elements. A short channel effect occurs that causes dielectric breakdown of the film.

In order to suppress such a short channel effect, an LDD (Lightly Doped Drain) structure is used. FIG. 16 is a schematic sectional view showing a structure of a conventional MOS transistor having an LDD structure.

In FIG. 16, a source region 34 made of an n ⁺ layer is formed on the surface of a p-type silicon substrate 31 with a predetermined space therebetween.
And a drain region 35 is formed. Silicon substrate 3 between source region 34 and drain region 35
The region 1 corresponds to the channel region 37. Channel region 37
A gate electrode 33 is formed on the gate oxide film 32. Insulating films 38a and 38b are formed on both side surfaces of the gate electrode 33, respectively.

At the end of the source region 34 and the end of the drain region 35, n ⁻ layers 36a and 36b having a low impurity concentration and spreading in the channel direction are formed, respectively.

In the MOS transistor of FIG. 16,
When a drain voltage is applied between the drain region 35 and the source region 34, the n ⁻ layer 36a having a relatively high resistance value,
36b suppresses an abrupt increase in the electric field generated near the end of the drain region 35. As a result, high breakdown voltage of the MOS transistor and suppression of hot carriers are realized.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In a conventional MOS transistor having a structure, n
^-It is difficult to accurately form the layers 36a and 36b
It n^-If the distance between the layers 36a and 36b varies, the char
The flannel resistance changes. Thereby, the MOS transistor
However, there is a problem that the characteristics of are different.

An object of the present invention is to provide a method for manufacturing a field effect semiconductor device which can suppress the short channel effect and can be manufactured with high accuracy.

[0011]

[0012]

Means for Solving the Problems and Effects of the Invention
A method of manufacturing a field effect semiconductor device according to
Alternatively, a gate insulating film and a gate electrode are sequentially formed on the semiconductor layer.
And the semiconductor on both sides of the gate insulating film
The source region and the drain are respectively formed on the substrate or the semiconductor layer.
Process for forming the gate region, the gate insulating film and the gate electrode.
Forming a first material layer on both sides of the pole, and a semiconductor substrate
Forming a second material layer on the top surface of the plate or semiconductor layer
And formed on both sides of the gate insulating film and the gate electrode.
Removing the first material layer and the semiconductor substrate or semi-finished
The second material layer on the conductor layer may be removed by etching.
The semiconductor near the both sides of the gate insulating film.
First and second grooves are provided in the substrate or the semiconductor layer, respectively.
And the step provided on the semiconductor substrate or the semiconductor layer.
First and second tunnels are provided in the first and second grooves, respectively.
And a step of forming a dielectric insulating film.

Manufacture of a field effect semiconductor device according to the present invention
In the method, provided on a semiconductor substrate or semiconductor layer
The first and second grooves in the first and second grooves, respectively.
The channel insulating film is formed, so that the channel of the source region is formed.
Channel region of the end of the channel region and the drain region
The first and second tunnel insulating films are formed at the ends of the
Is made.

In this case, the first and second tunnel insulations
The film thickness in the channel direction of the film is equal to that of the first and second grooves.
The width of the first and second trenches is determined by the width, and
And a film of the first material layer formed on both side surfaces of the gate electrode
It depends on the thickness. The thickness of the first material layer can be controlled accurately.
Therefore, the first and second tunnel insulating film
The film thickness in the channel direction can also be controlled accurately.
It Therefore, the device characteristics can be easily made uniform.
It becomes Noh.

A battery manufactured by the manufacturing method according to the present invention.
In the field effect semiconductor device, the drain region and the source
When the drain voltage is applied between the source region and
Channel region side end and drain region channel
The first and second magnets respectively provided at the end portions on the region side.
Of the source and drain regions
A voltage drop occurs at each end. As a result,
A sharp increase in the electric field at the end of the in region is suppressed. So
As a result, fluctuations in device characteristics due to hot carriers and gate
The short channel effect that causes dielectric breakdown of the insulating film is suppressed.
Therefore, high breakdown voltage can be achieved.

In particular, as the channel length decreases, the drain
Voltage applied to the first and second tunnel insulating films
Since the voltage ratio increases, the more miniaturized the device,
The suppression rate of the short channel effect is high.

[0017]

[0018]

[0019]

The thickness of each of the first and second tunnel insulating films in the channel direction is preferably 0.5 nm or more and 5 nm or less. As a result, a film can be formed and electrons can tunnel. In particular,
The thickness of each tunnel insulating film is 1 nm so that a sufficient electric field relaxation effect can be obtained and tunneling of electrons is facilitated.
The thickness of each tunnel insulating film is more preferably 2 nm or more and 4 nm or less so that a sufficient electric field relaxation effect can be obtained and electrons can be easily tunneled.

The semiconductor substrate or semiconductor layer may be made of silicon. In this case, a field effect type made of silicon
The short channel effect is suppressed in the semiconductor device . Alternatively, the semiconductor substrate or semiconductor layer may be made of a compound semiconductor. In this case, the field effect consisting of compound semiconductor
The short channel effect is suppressed in the semiconductor device .

The length of the channel region between the first tunnel insulating film and the second tunnel insulating film may be a length at which a quantum mechanical effect occurs.

In this case, the resonant tunneling phenomenon occurs due to the double barrier formed by the first and second tunnel insulating films. As a result, the gate voltage-drain current characteristic rises sharply and the switching characteristic becomes good.

Each of the first and second tunnel insulating films may have a multi-layer structure in which a plurality of insulating films are laminated in the channel direction with a semiconductor film or an insulating film interposed therebetween. In this case, a sufficient electric field relaxation effect is obtained and the pressure resistance is improved.

In particular, when the length of the channel region between the first tunnel insulating film and the second tunnel insulating film is the length at which the quantum mechanical effect is generated, the first structure having a multi-layer structure is used. A multiple resonance tunnel phenomenon occurs due to the multiple barriers formed by the tunnel insulating film and the second tunnel insulating film having a multilayer structure. As a result, the rise of the gate voltage-drain current characteristic becomes steeper, and the switching characteristic becomes better.

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

1 is a schematic sectional view showing the structure of a MOS transistor according to an embodiment of the present invention.

In FIG. 1, a source region 4 and a drain region 5 made of an n ⁺ layer are formed on the surface of a p-type silicon substrate 1 at a predetermined interval. The region of the silicon substrate 1 between the source region 4 and the drain region 5 becomes the channel region 7. SiO ₂ is formed on the channel region 7.
And a gate electrode 3 is formed on the gate oxide film 2.

A tunnel oxide film 6a made of SiO ₂ is formed between the source region 4 and the channel region 7, and SiO ₂ is formed between the drain region 5 and the channel region 7.
_A tunnel oxide film 6b made of ₂ is formed.

The film thicknesses d _OXS and d _OXD of the tunnel oxide films 6a and 6b are preferably 0.5 nm to 5 nm so that films can be formed and electrons can be tunneled, and a sufficient electric field relaxation effect can be obtained. Is more preferably 1 nm to 4 nm to facilitate electron tunneling, and 2 nm to 4 nm to obtain a sufficient electric field relaxation effect and facilitate electron tunneling.
More preferably, it is nm.

The source region 4 is grounded, and the drain region 5
A drain voltage V _ds is applied to. A gate voltage V _gs is applied to the gate electrode 3. In this MOS transistor, the distance between the tunnel oxide films 6a and 6b becomes the channel length L.

In the MOS transistor of this embodiment, when the drain voltage V _ds is applied between the drain region 5 and the source region 4, the tunnels inserted in the inner end portions of the source region 4 and the drain region 5 respectively. Oxide film 6
As a result, a voltage drop occurs at each end of the source region 4 and the drain region 5. This suppresses a sharp increase in the electric field at the end of the drain region 5. As a result, the short channel effect is suppressed and high breakdown voltage is achieved.

In particular, as the channel length L decreases, the ratio of the voltage applied to the tunnel oxide films 6a and 6b in the drain voltage V _ds increases. As a result, as the device becomes finer, the suppression rate of the short channel effect becomes higher.

Further, as will be described later, when the channel length L becomes a region where the quantum mechanical effect appears, a resonance tunnel phenomenon occurs due to the double barrier formed by the two tunnel oxide films 6a and 6b, and the device characteristics are improved. Change.

FIG. 2 is a diagram showing the calculation result of the electric field distribution in the channel direction in the MOS transistors of the embodiment and the conventional example. Further, FIG. 3 shows the MOS of the embodiment and the conventional example.
It is a figure which shows the calculation result of the electric potential distribution of the channel direction in a transistor. Further, FIG. 4 is a diagram showing the calculation results of the electron concentration distribution in the channel direction in the MOS transistors of the example and the conventional example. 2, 3 and 4
In (a), when the channel length L is 100 nm,
(B) shows the case where the channel length L is 50 nm, and (c) shows the case where the channel length L is 10 nm.

The horizontal axes of FIGS. 2, 3 and 4 represent the distance from the source region 4 in the channel direction. In this calculation, the gate voltage V _gs was 5.0 V and the drain voltage V _ds was 2.0 V. In addition, M of this embodiment
In the OS transistor, the film thickness d _OXS of the tunnel oxide film 6a at the end of the source region 4 and the film thickness d _OXD of the tunnel oxide film 6b at the end of the drain region 5 are both 3.0 n.
m. The conventional MOS transistor is shown in FIG.
This structure does not have the tunnel oxide films 6a and 6b.

As shown in FIG. 2, in both the MOS transistor of the embodiment and the conventional example, the absolute value of the electric field distribution in the channel increases as the channel length L decreases. However, comparing the two with the same channel length L,
In the MOS transistor of the example, the absolute value of the electric field is smaller than that of the conventional MOS transistor, and the increase rate of the electric field is small in the vicinity of the end of the drain region 5. This tendency is more remarkable as the channel length L is smaller.

Next, as shown in FIG. 3, the increase rate of the potential increases as the channel length L decreases in both the MOS transistor of the embodiment and the conventional example. Comparing the two with the same channel length L, the conventional MOS
In the transistor, the potential in the vicinity of the end of the drain region 5 is equal to the drain voltage V _ds , whereas in the MOS transistor of the embodiment, as the channel length L decreases, in the vicinity of the end of the drain region 5. Potential tends to decrease.

Further, as shown in FIG.
In the S transistor, the electron concentration near the end of the source region 4 and the electron concentration near the end of the drain region 5 are the same regardless of the channel length L, and the concentration gradient increases as the channel length L decreases. ing. On the other hand, in the MOS transistor of this example, the electron concentration near the end of the drain region 5 increases as the channel length L decreases.

From the results of FIG. 2, when the channel length L is the same, the MOS transistor of the embodiment is
It can be seen that the increase rate of the electric field in the vicinity of the end of the drain region 5 is suppressed as compared with the transistor.

This is because the tunnel oxide films 6a and 6a formed at the ends of the source region 4 and the drain region 5, respectively.
It is considered that this is because a voltage drop occurs due to b and the electric field is relaxed.

As a result, as shown in FIG. 3, in the MOS transistor of the embodiment, the tunnel oxide films 6 formed at the ends of the source region 4 and the drain region 5, respectively.
The voltage applied to the channel is reduced by the voltage drop of a and 6b.

Considering that the relative permittivity of silicon is 11.7 and the relative permittivity of SiO ₂ is 3.9, the tunnel oxide films 6a and 6b are formed as the channel length L is reduced. It can be seen that the electric field relaxation effect of the tunnel oxide films 6a and 6b becomes remarkable as the distribution amount of the drain voltage V _ds increases.

As a result, as shown in FIG. 4, in the MOS transistor of the embodiment, the electric field relaxation effect in the channel by the tunnel oxide films 6a and 6b has a gentler electron concentration gradient as compared with the MOS transistor of the conventional example. become.

FIG. 5A is a diagram showing the calculation result of the drain current I _ds with respect to the drain voltage V _ds in the conventional MOS transistor, and FIG. 5B is the drain current with respect to the drain voltage V _ds in the MOS transistor of the embodiment. It is a figure which shows the calculation result of _Ids . In this calculation, the gate voltage V _gs was set to 5.0V.

In the MOS transistor of the embodiment, the current flowing between the source and the drain, that is, the electron flowing between the source and the drain tunnels through the tunnel oxide film 6a formed at the end of the source region 4 and diffuses in the channel. Flows toward the drain region 5 side due to drift,
Tunnel oxide film 6b formed at the end of drain region 5
Tunnel into the drain region 5. in this case,
The time taken for the electrons to tunnel through the tunnel oxide films 6a and 6b is considered to be extremely short compared with the time taken for the electrons to diffuse and drift in the channel. Therefore, in the drain current I _ds of the MOS transistor of the example, the diffusion current component and the drift current component are predominantly calculated.

As shown in FIG. 5A, in the conventional MOS transistor, the drain current I _ds greatly increases as the channel length L decreases. As shown in FIG. 5B, the MOS transistor of this embodiment also shows the same tendency as the conventional MOS transistor, but the value of the drain current I _ds with respect to each drain voltage V _ds decreases and the current increases. The rate is also decreasing.

Here, the MOS transistor of the conventional example is paired.
The electric field relaxation effect of the MOS transistor of the embodiment
M with LDD structure for example MOS transistor
It was compared with the electric field relaxation effect of the OS transistor. Of the example
In the MOS transistor, the channel length L is 100n
m and the thickness of each tunnel oxide film 6a, 6b is 3.0n.
When m, the electric field relaxation near the edge of the drain region 5
The amount is about 0.79 times that of the conventional MOS transistor
Becomes On the other hand, dose amount 1.0 × 10¹⁴/ Cm ³Made with
In a MOS transistor having an integrated LDD structure,
When the channel length L is 100 nm, the end of the drain region
The amount of electric field relaxation near the
It will be about 0.62 times.

From this result, the channel length L is 100 nm.
In the case of, in the MOS transistor of the embodiment, LDD
Although the amount of electric field relaxation is slightly smaller than that of the MOS transistor having the structure, as described above, in the MOS transistor of the embodiment, the amount of electric field relaxation increases as the channel length L decreases. Accordingly, it is considered that the electric field relaxation performance is superior to that of the MOS transistor having the LDD structure.

Next, considering the energy band in the channel direction of the MOS transistor of the embodiment, the source region 4
The tunnel oxide films 6a and 6b formed at the ends of the drain region 5 form a double barrier structure. Therefore, when the channel length L becomes a region where the quantum mechanical effect appears (for example, about 10 nm), the two tunnel oxide films 6 are formed.
It is considered that a resonance tunnel phenomenon occurs due to the double barriers of a and 6b. Therefore, a numerical analysis was performed on the resonant tunneling phenomenon due to the double barrier of the tunnel oxide films 6a and 6b.

FIG. 6 is a diagram showing the calculation result of the transmission coefficient characteristic with respect to the drain voltage V _ds in the MOS transistor of the embodiment. In this calculation, the channel length L is set to 10 nm.
And the film thickness d _OXS of the tunnel oxide film 6a at the end of the source region 4 and the tunnel oxide film 6 at the end of the drain region 5
The film thickness d _OXD of b was both 3.0 nm. That is,
The thickness of the two tunnel oxide films 6a and 6b was set symmetrically.

In this case, the double barrier asymmetry increases by applying the drain voltage V _ds . From the calculation result of the transmission coefficient characteristic of FIG. 6, it is possible to confirm a plurality of peaks of the transmission coefficient due to the resonance tunnel phenomenon. Further, the value of the transmission coefficient at the time of resonance is increased by more than ten orders of magnitude as compared to the value at the time of non-resonance. It is considered that this resonance tunnel phenomenon is caused by the formation of a plurality of quantum levels due to the channel length L becoming extremely small.

From these results, the transmission coefficient due to the double barrier is
The number characteristic is the film thickness d of the two tunnel oxide films 6a and 6b.
_OXS, D_OXDAnd drain voltage V_dsBy
Very sharp peaks with increasing double barrier asymmetry
Found to have. The peak of this transmission coefficient characteristic is
The film thickness d of the tunnel oxide film 6b at the end of the drain region 5_OX
DIs the film thickness d of the tunnel oxide film 6a at the end of the source region 4.
_OXSThicker and drain voltage V_dsDue to double barrier
By making the structure so that the asymmetry of
It is thought that it can be further increased. By this
Gate voltage V _gs-Drain current I_dsCharacteristics (Thresshi
The hold characteristic) rises sharply and the switch
Good squeeze characteristics.

As described above, in the MOS transistor of the embodiment, when the channel length L is relatively long, the characteristics similar to those of the normal MOS transistor are exhibited, and the channel length L is
If becomes very short, the transistor characteristics will change due to the resonance tunnel phenomenon.

7 and 8 are process cross-sectional views showing a first example of the method for manufacturing a MOS transistor of this embodiment.

[0064] First, as shown in FIG. 7 (a), on a p-type silicon substrate 1, to form a gate electrode 3 consisting of the gate oxide film 2 and the polycrystalline silicon made of SiO ₂ in this order. Then, as shown in FIG. 7B, the gate oxide film 2
And the recesses 11a, 1 in the regions of the silicon substrate 1 on both sides of the gate electrode 3 by dry etching.
1b is formed. Thereafter, as shown in FIG. 7C, an oxide film 6 made of SiO ₂ and having a film thickness of about 30Å is formed on the entire surface by a thermal oxidation method.

Next, as shown in FIG. 8D, the oxide film 6 on the upper surface of the silicon substrate 1 and the upper surface of the gate electrode 3 is removed by sputtering or anisotropic dry etching. As a result, the oxide film 6 remains on the side surfaces of the recesses 11a and 11b and the side surface of the gate electrode 3.

After that, by selective epitaxial growth of silicon, vapor deposition of polycrystalline silicon, or formation of silicide, the source electrode 8a and the drain electrode 8b made of n ⁺ layers are formed in the recesses 11a and 11b, respectively, and the gate electrode 3 is formed. Then, the wiring layer 8c is formed.

In this case, the source electrode 8a and the drain electrode 8b correspond to the source region 4 and the drain region 5 of FIG. 1, respectively, and the region of the silicon substrate 1 between the source electrode 8a and the drain electrode 8b is the channel region 7. Become.
The oxide film between the source electrode 8a and the channel region 7 becomes the tunnel oxide film 6a, and the oxide film between the drain electrode 8b and the channel region 7 becomes the tunnel oxide film 6b.

FIG. 9, FIG. 10 and FIG. 11 show M of this embodiment.
FIG. 6 is a process sectional view showing a second example of the method for manufacturing the OS transistor.

First, as shown in FIG. 9A, a gate oxide film 2 and a gate electrode 3 are sequentially formed on a p-type silicon substrate 1, and then the gate electrode 3 and the gate oxide film 2 are used as a mask to form an n-type impurity. By ion-implanting (n-type dopant), the source region 4 and the drain region 5 formed of the n ⁺ layer are formed on the surface of the silicon substrate 1. The region of the silicon substrate 1 between the source region 4 and the drain region 5 becomes the channel region 7.

Next, as shown in FIG. 9B, an insulating film made of SiO ₂ or SiN having a film thickness of about 30 Å is formed on the entire surface by a vapor deposition method or the like, and the silicon substrate 1 is formed by sputtering or anisotropic dry etching. The insulating films on the upper surface of the gate electrode 3 and the upper surface of the gate electrode 3 are removed. As a result, the insulating film 9 remains on the side surfaces of the gate oxide film 2 and the gate electrode 3.

After that, as shown in FIG. 9C, a silicon layer 10 is formed on the upper surface of the silicon substrate 1 and the upper surface of the gate electrode 3 by selective epitaxial growth of silicon.

Next, as shown in FIG. 10D, the insulating film 9 on the side surfaces of the gate oxide film 2 and the gate electrode 3 is removed by etching. When the insulating film 9 is made of SiO ₂ , HF (hydrogen fluoride) is used as an etching solution, and when the insulating film 9 on the side surface is made of SiN, phosphoric acid is used as an etching solution. As a result, the groove 12 is formed between the side surface of the gate oxide film 2 and the edge of the silicon layer 10.

Next, as shown in FIG. 10E, the silicon layer 10 on the upper surface of the silicon substrate 1 and the upper surface of the gate electrode 3 is removed by dry etching the entire surface, and the side surface of the gate oxide film 2 is near. Silicon substrate 1
The groove 13 is formed in the area of.

Next, as shown in FIG. 10F, an oxide film 60 made of SiO ₂ is formed on the entire surface by a thermal oxidation method. As a result, the tunnel oxide films 6a and 6b are formed in the trench 13.
Are formed respectively.

Finally, as shown in FIG. 11G, the oxide film 60 on the source region 4 and the drain region 5 is removed by etching to remove the source region 4 and the drain region 5.
A source electrode 14 and a drain electrode 15 are formed on each.

In the MOS transistor of FIG. 1, single-layer tunnel oxide films 6a and 6b are formed at the end of the source region 4 and the end of the drain region 5, respectively. A tunnel insulating film having a multi-layer structure (hereinafter, referred to as a multi-layer tunnel insulating film) may be provided at each end of the region 5. Next, a method of manufacturing a MOS transistor having a multilayer tunnel insulating film will be described.

12 and 13 are process sectional views showing a first example of a method for manufacturing a MOS transistor having a multilayer tunnel insulating film.

First, the gate oxide film 2 and the gate electrode 3 are formed on the p-type silicon substrate 1 by the steps shown in FIGS. 7A and 7B, and both sides of the gate oxide film 2 and the gate oxide film 3 are formed. Recesses 11a and 11b are formed in the regions of the silicon substrate 1, respectively. Then, as shown in FIG. 12A, a Si film having a film thickness of about 30 Å is formed on the entire surface by a thermal oxidation method.
An oxide film 6 made of O ₂ is formed.

Next, as shown in FIG. 12B, a film thickness of 0.5 to 10 nm is formed on the oxide film 6 by the CVD method (chemical vapor deposition method) or the MBE method (molecular beam epitaxy method).
Then, the silicon film 16 is formed.

Further, as shown in FIG. 12C, an oxide film 17 made of SiO ₂ and having a film thickness of 0.5 to 10 nm is formed on the silicon film 16 by the CVD method or the sputtering method.

Next, as shown in FIG. 13D, the oxide film 6, the silicon film 16 and the oxide film 17 on the upper surface of the silicon substrate 1 and the upper surface of the gate electrode 3 are removed by sputtering or anisotropic dry etching. . As a result, the side surfaces of the recesses 11a and 11b and the gate oxide film 2
And an oxide film 6 and a silicon film 16 on the side surface of the gate electrode 3.
And the oxide film 17 remains.

Thereafter, as shown in FIG. 13E, the recesses 11a and 11b are formed by selective epitaxial growth of silicon, vapor deposition of polycrystalline silicon, or formation of silicide.
A source electrode 8a and a drain electrode 8b each made of an n ⁺ layer are formed on the gate electrode 3, and a wiring layer 8c is formed on the gate electrode 3.

After that, as shown in FIG. 13F, the oxide film 6, the silicon film 16 and the oxide film 17 on the side surfaces of the gate oxide film 2 and the gate electrode 3 are removed by dry etching.

In this case, the source electrode 8a and the drain electrode 8b correspond to the source region 4 and the drain region 5 of FIG. 1, respectively, and the region of the silicon substrate 1 between the source electrode 8a and the drain electrode 8b is the channel region 7. Become.
Further, the oxide film 6, the silicon film 16 and the oxide film 17 between the source electrode 8a and the channel region 7 constitute the multilayer tunnel insulating film 21a, and the oxide film 6 and the silicon between the drain electrode 8b and the channel region 7 are formed. Film 16 and oxide film 17
Form the multilayer tunnel insulating film 21b.

The multilayer tunnel insulating films 21a and 21b are used.
When increasing the number of layers of, the steps of FIGS. 12A to 12C are repeated.

As described above, the multilayer tunnel insulating film 21
By including a silicon film in a and 21b, the transmission coefficient can be improved, that is, the current value associated with the resonance tunnel phenomenon can be increased.

14 and 15 are process sectional views showing a second example of the method of manufacturing a MOS transistor having a multilayer tunnel insulating film.

First, the gate oxide film 2 and the gate electrode 3 are formed on the p-type silicon substrate 1 by the steps shown in FIGS. 7A and 7B, and both sides of the gate oxide film 2 and the gate electrode 3 are formed. In the region of the silicon substrate 1 in
1a and 11b are formed respectively. And in FIG.
As shown in (a), the film thickness is 30Å on the entire surface by the thermal oxidation method.
An oxide film 6 made of SiO ₂ is formed.

Next, as shown in FIG. 14B, a nitride film 18 of SiN having a film thickness of 0.5 to 10 nm is formed on the oxide film 6 by the LPCVD method (liquid phase chemical vapor deposition method). Form. SiH ₂ Cl ₂ and NH ₃ as source gases
Mixed gas is used, and the growth condition is a pressure of 0.3T.
Orr and the temperature is 705 ° C.

Further, as shown in FIG. 14C, the temperature of the nitride film 18 was set to 8 at a normal pressure of O ₂ / H ₂ O.
The oxide film 17 made of SiO ₂ and having a film thickness of 0.5 to 10 nm is formed under the condition of 50 ° C.

Next, as shown in FIG. 15D, the oxide film 6, the nitride film 18 and the oxide film 17 on the upper surface of the silicon substrate 1 and the upper surface of the gate electrode 3 are removed by sputtering or anisotropic dry etching. . As a result, the oxide film 6, the nitride film 18 and the oxide film 17 on the side surfaces of the recesses 11a and 11b and on the side surfaces of the gate oxide film 2 and the gate electrode 3 remain.

After that, as shown in FIG. 15E, the recesses 11a and 11b are formed by selective epitaxial growth of silicon, vapor deposition of polycrystalline silicon, or formation of silicide.
A gate electrode 8a and a drain electrode 8b each made of an n ⁺ layer are formed therein, and a wiring layer 8c is formed on the gate electrode 3.

Finally, as shown in FIG. 15F, the oxide film 6, the nitride film 18 and the oxide film 17 on the side surfaces of the gate oxide film 2 and the gate electrode 3 are removed by dry etching.

In this case, the source electrode 8a and the drain electrode 8b correspond to the source electrode 4 and the drain electrode 5 of FIG. 1, respectively, and the region of the silicon substrate 1 between the source electrode 8a and the drain electrode 8b is the channel region 7. Become.
Further, the oxide film 6, the nitride film 18 and the oxide film 17 between the source electrode 8a and the channel region 7 constitute the multilayer tunnel insulating film 21a, and the oxide film 6 and the nitride film between the drain electrode 8b and the channel region 7 are nitrided. The film 18 and the oxide film 17 form the multilayer tunnel insulating film 21b.

The multilayer tunnel insulating films 21a and 21b are used.
14A to 14C, the steps of FIGS. 14A to 14C are repeated.

Instead of forming the oxide film 6 by the thermal oxidation method in the step of FIG. 14A, the film thickness formed on the surface of the silicon substrate 1 and the surface of the gate electrode 3 during or after the cleaning of the silicon substrate 1. A 1.0-1.5 nm natural oxide film may be used.

In the above MOS transistor, each of the multilayer tunnel insulating films 21a and 21b constitutes a double barrier structure. Since the two sets of multilayer tunnel insulating films 21a and 21 each have a double barrier structure, the channel length is a region where a quantum mechanical effect appears (for example, about 10 nm).
Then, a resonance tunnel phenomenon occurs due to the quadruple barrier formed by the two sets of multilayer tunnel insulating films 21a and 21b.

In this case, each multilayer tunnel insulating film 21a,
Since a plurality of quantum levels are formed between the double barriers of 21b, a sharp peak of the transmission coefficient appears for a plurality of drain voltages V _ds . As a result, the gate voltage _Vgs -drain current _Ids characteristic (threshold characteristic) of the MOS transistor becomes steeper, and the switching characteristic is further improved.

In the above embodiment, the same effect can be obtained even if the following changes are made.

In the above embodiment, the single-layer tunnel oxide films 6a and 6b made of SiO ₂ are used as the tunnel insulating film.
Alternatively, although the multilayer tunnel insulating films 21a and 21b are used, a single-layer tunnel insulating film or a multilayer tunnel insulating film made of another insulating film such as SiN may be used.

[0102] In the above embodiment uses the gate oxide film 2 made of SiO ₂ as a gate insulating film, S
A gate insulating film made of another insulating film such as iN may be used.

Further, in the above embodiment, the silicon substrate 1
Although the MOS transistor is formed in the above, the MOS transistor may be formed in the silicon layer. Further, instead of the silicon substrate 1, the MOS transistor may be formed on a semiconductor substrate or a semiconductor layer made of a compound semiconductor such as SiC (silicon carbide) or GaN (gallium nitride).

The present invention is not limited to MOS transistors, but can be applied to other field effect semiconductor devices.

The field effect type semiconductor device or field effect transistor according to the present invention can be used as a MOS transistor of an LSI, and can also be applied to a switching transistor of a DRAM (dynamic random access memory). .

Although the MOS transistor having an n-type channel has been described in the above embodiment, the present invention can be applied to a field effect semiconductor device such as a MOS transistor having a p-type channel.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing the structure of a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing calculation results of an electric field distribution in a channel direction in MOS transistors of an example and a conventional example.

FIG. 3 is a diagram showing calculation results of a potential distribution in a channel direction in MOS transistors of an example and a conventional example.

FIG. 4 is a diagram showing calculation results of an electron concentration distribution in a channel direction in MOS transistors of an example and a conventional example.

FIG. 5 is a diagram showing calculation results of drain current with respect to drain voltage in MOS transistors of a conventional example and an example.

FIG. 6 is a diagram showing calculation results of transmission coefficient characteristics with respect to drain voltage in the MOS transistor of the example.

7A to 7C are process cross-sectional views showing a first example of a method for manufacturing the MOS transistor of FIG.

8A to 8D are process cross-sectional views showing a first example of a method for manufacturing the MOS transistor of FIG.

FIG. 9 is a process sectional view showing a second example of the method for manufacturing the MOS transistor of FIG.

FIG. 10 is a second method of manufacturing the MOS transistor of FIG.
FIG. 6 is a process sectional view showing an example of FIG.

FIG. 11 is a second manufacturing method of the MOS transistor of FIG.
FIG. 6 is a process sectional view showing an example of FIG.

FIG. 12 is a process sectional view showing a first example of a method of manufacturing a MOS transistor having a multilayer tunnel insulating film.

FIG. 13 is a process sectional view showing a first example of a method for manufacturing a MOS transistor having a multilayer tunnel insulating film.

FIG. 14 is a process sectional view showing a second example of the method for manufacturing the MOS transistor having the multilayer tunnel insulating film.

FIG. 15 is a process sectional view showing a second example of a method for manufacturing a MOS transistor having a multilayer tunnel insulating film.

FIG. 16 is a schematic cross-sectional view of a conventional MOS transistor having an LDD structure.

[Explanation of symbols]

1 Silicon substrate 2 Gate oxide film 3 Gate electrode 4 Source area 5 drain region 6a, 6b tunnel oxide film 7 channel area 6,17,60 Oxide film 8a source electrode 8b drain electrode 10 Silicon layer 11a, 11b recesses 13 groove 16 Silicon film 18 Nitride film 21a, 21b Multilayer tunnel insulating film

Claims (6)

(57) [Claims] 1. A step of sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate or a semiconductor layer, and a step of forming a source region and a drain region on the semiconductor substrate or the semiconductor layer on both sides of the gate insulating film, respectively. A first side surface of each of the gate insulating film and the gate electrode;
Forming a second material layer on the upper surface of the semiconductor substrate or the semiconductor layer, and forming the first material layer on both side surfaces of the gate insulating film and the gate electrode. And removing the second material layer on the semiconductor substrate or the semiconductor layer by etching, thereby removing the first and the first semiconductor layers from the semiconductor substrate or the semiconductor layer in the vicinity of both side surfaces of the gate insulating film, respectively. And a step of forming first and second tunnel insulating films in the first and second grooves provided in the semiconductor substrate or the semiconductor layer, respectively. Electric field effect
Manufacturing method of fruit-shaped semiconductor device . 2. The first and the first in the channel direction
The thickness of the tunnel insulating film of No. 2 is 0.5 nm or more 5
The electric field effect according to claim 1, which is less than or equal to nm.
Manufacturing method of fruit-shaped semiconductor device. 3. The semiconductor substrate or semiconductor layer is a silicon substrate.
The battery according to claim 1 or 2, characterized in that
Method for manufacturing field effect semiconductor device. 4. The semiconductor substrate or semiconductor layer is a compound
3. The semiconductor device according to claim 1, wherein the semiconductor device is made of a semiconductor.
Of manufacturing a field effect semiconductor device of. 5. The first tunnel insulating film and the second tunnel insulating film.
The length of the channel region between the tunnel insulating film and the tunnel insulating film is quantum.
Claim characterized in that the length is such that a mechanical effect occurs
Item 7. A field effect semiconductor device according to any one of items 1 to 4.
Build method. 6. The first and second tunnel insulating films
Each has a plurality of insulating films through the semiconductor film or the insulating film.
Having a multi-layer structure that is laminated in the channel direction
The field-effect type according to any one of claims 1 to 5.
Manufacturing method of semiconductor device .