201105187 υνυ^υυ ι 3155 l.twf.doc/u 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板及其製造方法，且特別是 有關於一種適於進行疊孔設計的線路板及其製造方法。 【先前技術】 近年來，隨著電子技術的日新月異’以及高科技電子 產業的相繼問世’使得更人性化、功能更佳的電子產品不 也推陳出新，並朝向輕、薄、短、小的趨勢邁進。於習 知技術中’主要是藉由線路板承載多個電子元件以及使這 些電子元件彼此電性連接。一般而言，線路板的製作方法 是先在一介電層上全面形成一導電層，然後，以微影蝕刻 的方式圖案化介電層以形成一線路層。然而，昂貴的光罩 /、繁雜的製程步驟，勢必增加製程的成本。 【發明内容】 本發明提供一種線路板，適於進行疊孔設計。 本發明提供一種線路板的製作方法，可又製作疊孔結 本發明提出-種線路板包括—第—絕緣層、 二„料以及—第—接塾。第„絕緣層具有: -弟一通孔，其中凹槽具有一底部，且第— 曰 部’第一絕緣声的材皙Λ班右々彻铱 通孔貝穿底 料。導電==觸媒顆粒的絕緣材 %層配置於弟-通孔的内壁上。填孔材料填充於第 201105187 υνυουυ i 3155 ltwf.doc/n :=:第填=:的材質為摻有多個第二觸媒顆粒的絕 置㈣槽中，並覆蓋填孔材料、Ϊ電 層與H緣層，且解電層電性連接。 在本發明之一實施例φ ,, 具有-第二接塾，其中第j路板更包括線路基板，其 广2 導電層更配置於第二接塾上並盘 弟二接墊電性連接。 在本發明之-實施例中，線路板更包括至少一第二絕 緣層、^少-第三缝以及至少—導電通道。第二絕緣層 配置=第緣層上。第三接墊配置於第二絕緣層上，並 位於第接塾上方。導電通道貫穿第二絕緣層並連接第一 接墊與第三接墊。 在本發明之一實施例中，第一觸媒顆粒的材質或第二 觸媒顆粒的材質包括多個金屬配位化合物。 ，本發明之一實施例中，金屬配位化合物的材質包栝 金屬氧化物、金屬氮化物、金屬錯合物或金屬螯合物。 在本發明之一實施例中，金屬配位化合物的材質為盡 自於由鋅、銅、銀、金、鎳、鈀、鉑、鋁、鈷、铑、銥、 鐵、猛、鉻'鉬、鎢、叙、鈕、銦以及鈦所組成的群組。 本發明提出一種線路板的製作方法如下所述。首先， 提供一第一絕緣層，第一絕緣層的材質為摻有多個第一觸 媒顆粒的絕緣材料。接著，於第一絕緣層上形成一第一通 孔。然後，於第一通孔的内壁上形成一導電層。之後，將 一填孔材料填入第一通孔中，填孔材料的材質為摻有多侗 201105187 〇y〇5UUl 31551twf.doc/n 第二觸媒顆粒的絕緣材料。接著，移除第—絕緣 第-通孔之-開放端的部分、導電層之位=鄰近 以及填孔材料之位於開放端的部分，以於第部分 成暴f出導電層與填孔村料的1槽。然後，；形 成-第-接墊，第-接塾配置於填孔材料電j形 絕緣層上，並與導電層電性連接。 、電3與弟一 沉積 射燒ΐ本伽之—實施财，形絲—通孔財法包括雷 在本發明之-實施例中，形成導電層的方法包括化學 在本發明之-實施例中，形成凹槽的方法包括雷射燒 學沉ί本發3狀—實施财，形成第—接㈣方法包括化 本《狀例中’線路板的製作方法更包括在 絕緣層時，提供—線路基板，線路基板具有一ί —接塾’且第—絕緣層配置於線路基板上，其中形成第一 mrr括移除第一絕緣層之覆蓋第二接塾的部分， ^成W層的方法包括同時在第—通 墊上形成導電層。 # ^ ^在本么月之只鈿例中，線路板的製作方法更包括於 =I彖層上形成—第二絕緣層’然後，形A貫穿第二絕 ί層的一第二通孔’第二通孔暴露出第-接塾，之後，於 弟一絕緣層上形成一線路結構，線路結構包括-導電結構 201105187 uyu^uui 3l551twf.doc/n 與一第三接墊，其中導電結構配置於第二通孔中並電性連 接第一接墊’第三接墊配置於導電結構上並位於第二絕緣 層之遠離第一絕緣層的一表面上。 在本發明之一實施例中，第一觸媒顆粒的材質或第二-觸媒顆粒的材質包括多個金屬配位化合物。 在本發明之一實施例中，金屬配位化合物的材質包括 金屬氧化物、金屬氮化物、金屬錯合物或金屬螯合物。 在本發明之一實施例中，金屬配位化合物的材質為選 自於由鋅、銅、銀、金、鎳、把、翻、銘、始、錄、銀、 鐵、猛、鉻、鉬、鎢、釩、鈕、銦以及鈦所組成的群組。 基於上述，由於本發明將填孔材料填入第一絕緣層的 第通孔中，且填孔材料的材質為摻有多個第二觸媒顆粒 的絕緣材料，因此，本發明可在第一通孔上方直接形成第 一接墊。換言之，將填孔材料填入第一通孔中可有利於疊 孔設計，進而可增加線路的設計彈性以及線路的佈局空間。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例’並配合所附圖式作詳細說明如下。 【實施方式】 圖1繒'示本發明一實施例之線路板的剖面圖。請參照 ，1，本實施例之線路板100包括一第一絕緣層11〇、二導 电，120、一填孔材料130以及—第一接墊140。此外，在 本貫施例中’第-絕緣層11〇可選擇性地配置於—線路基 板150上’線路基板15〇可為一單面板、一雙面板或一多 201105187 υνυ^υυι 3I551twf.doc/n 層板。線路基板150可具有一第二接墊152。201105187 υνυ^υυ ι 3155 l.twf.doc/u VI. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a design suitable for stacking holes Circuit board and its manufacturing method. [Prior Art] In recent years, with the rapid development of electronic technology and the advent of the high-tech electronics industry, more humanized and better-functioning electronic products have not been introduced, and they are moving toward a trend of light, thin, short and small. . In the prior art, a plurality of electronic components are mainly carried by a circuit board and electrically connected to each other. Generally, the circuit board is formed by first forming a conductive layer on a dielectric layer, and then patterning the dielectric layer by photolithography to form a wiring layer. However, expensive masks/complex process steps are bound to increase the cost of the process. SUMMARY OF THE INVENTION The present invention provides a circuit board suitable for stacking holes. The invention provides a method for fabricating a circuit board, which can also make a stacked hole junction. The invention provides a circuit board comprising a first insulating layer, a second material and a first interface. The first insulating layer has: - a through hole Wherein the groove has a bottom portion, and the first portion of the first insulating sound is traversed by the through hole. Conductive == Insulating material of the catalyst particles The % layer is disposed on the inner wall of the via-through hole. The hole-filling material is filled in the 201105187 υνυουυ i 3155 ltwf.doc/n:=: the first filling =: the material is in the semi-tank (four) groove doped with a plurality of second catalyst particles, and covers the hole-filling material, the electric layer And the H edge layer, and the electric layer is electrically connected. In one embodiment of the present invention, φ has a second interface, wherein the j-th board further comprises a circuit substrate, and the wide conductive layer is disposed on the second interface and the second pads are electrically connected. In an embodiment of the invention, the circuit board further includes at least a second insulating layer, a minor-third slit, and at least a conductive via. Second insulation layer configuration = on the edge layer. The third pad is disposed on the second insulating layer and located above the first port. The conductive path penetrates the second insulating layer and connects the first pad and the third pad. In an embodiment of the invention, the material of the first catalyst particles or the material of the second catalyst particles comprises a plurality of metal coordination compounds. In one embodiment of the invention, the metal coordination compound is made of a metal oxide, a metal nitride, a metal complex or a metal chelate. In one embodiment of the present invention, the metal coordination compound is made of zinc, copper, silver, gold, nickel, palladium, platinum, aluminum, cobalt, rhodium, ruthenium, iron, lanthanum, chromium, molybdenum, A group of tungsten, ruthenium, knob, indium, and titanium. The present invention provides a method of fabricating a circuit board as follows. First, a first insulating layer is provided, and the material of the first insulating layer is an insulating material doped with a plurality of first catalyst particles. Next, a first via hole is formed on the first insulating layer. Then, a conductive layer is formed on the inner wall of the first through hole. Thereafter, a hole-filling material is filled into the first through-hole, and the material of the hole-filling material is an insulating material doped with a plurality of 05 侗 侗 U U U U U U U 5UUl 31551 twf. Then, the portion of the open-end of the first-insulating first-via hole, the position of the conductive layer=the adjacent portion, and the portion of the hole-filling material at the open end are removed, so that the first portion is formed into a conductive layer and a filled hole material groove. Then, a - first pad is formed, and the first contact is disposed on the electrical j-type insulating layer of the hole-filling material and electrically connected to the conductive layer. , electricity 3 and the younger one deposits the burnt ΐ 伽 — 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 在 在 在 在 在 在 在 在 在 在The method for forming the groove includes a laser burning method, a method of forming a third method, and a method of forming a first-to-fourth (fourth) method, including the method of manufacturing the circuit board in the case of the circuit board. a substrate, the circuit substrate has a 塾-junction and the first insulating layer is disposed on the circuit substrate, wherein the first mrr is formed to include a portion of the first insulating layer covering the second interface, and the method for forming the W layer includes At the same time, a conductive layer is formed on the first through pad. # ^ ^ In the case of this month, the circuit board is further formed on the =I layer - the second insulating layer 'then, the shape A penetrates a second through hole of the second layer" The second via hole exposes the first via, and then a wiring structure is formed on the insulating layer of the brother, the wiring structure comprises a conductive structure 201105187 uyu^uui 3l551twf.doc/n and a third pad, wherein the conductive structure is configured The third pad is electrically connected to the first pad and the third pad is disposed on the conductive structure and located on a surface of the second insulating layer away from the first insulating layer. In an embodiment of the invention, the material of the first catalyst particles or the material of the second catalyst particles comprises a plurality of metal coordination compounds. In an embodiment of the invention, the material of the metal complex compound comprises a metal oxide, a metal nitride, a metal complex or a metal chelate. In an embodiment of the invention, the metal coordination compound is selected from the group consisting of zinc, copper, silver, gold, nickel, pour, turn, inscription, beginning, recording, silver, iron, fission, chromium, molybdenum, A group of tungsten, vanadium, knobs, indium, and titanium. Based on the above, since the hole filling material is filled in the first through hole of the first insulating layer, and the material of the hole filling material is an insulating material doped with a plurality of second catalyst particles, the present invention can be first A first pad is directly formed above the through hole. In other words, filling the hole-filling material into the first through-hole can facilitate the design of the stack, thereby increasing the design flexibility of the line and the layout space of the line. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] FIG. 1A' is a cross-sectional view showing a wiring board according to an embodiment of the present invention. Referring to FIG. 1, the circuit board 100 of the present embodiment includes a first insulating layer 11 , two conductive electrodes 120 , a hole-filling material 130 , and a first pad 140 . In addition, in the present embodiment, the 'first insulating layer 11' can be selectively disposed on the circuit substrate 150. The circuit substrate 15 can be a single panel, a double panel or a multi-201105187 υνυ^υυι 3I551twf.doc /n Layer. The circuit substrate 150 can have a second pad 152.
第一絕緣層110具有一凹槽112與一第一通孔114， 其中凹槽112具有一底部U2a ’且第一通孔114貫穿底部 U2a並暴露出第二接墊152。導電層ι2〇配置於第—通孔 1H的内壁114a以及第二接墊152上，並與第二接墊152 電性連接。填孔材料130填充於第一通孔114中。第—接 墊140配置於凹槽112中，並覆蓋填孔材料13〇、導電層 120與第一絕緣層11〇，且與導電層12〇電性連接。 此外，在本實施例中，第一絕緣層11〇的材質可為摻 有多個第一觸媒顆粒（未繪示）的絕緣材料，且填孔材料 no的材質可為摻有多個第二觸媒顆粒（未繪示）的絕緣 ^料。第一觸媒顆粒與第二觸媒顆粒適於被雷射活化且可 藉由化學沉積製程在雷射活化後的第一觸媒顆粒與第二觸 媒，粒上形成一金屬層。第一觸媒顆粒或第二觸媒顆粒的 材質包括金屬配位化合物，且金屬配位化合物的材質可為 金屬氧化物、金屬氮化物、金屬錯合物或金屬螯合物，此 金屬配位化合物的材質亦可以是選自於由鋅、銅、銀、 金、鎳、鈀、鉑、鋁、鈷、鍺、銥、鐵、錳、鉻、鉬、鎢、 銳、鈕、銦以及鈦所组成的群組。 ’·· 在本實施例中，還可在第—絕緣層11〇上形 結構A，增層結構A包括—第二絕緣層16()、—第三^ 170、一導電通道18〇以及一線路部分19〇。第二絕緣層1⑹ 配置於第—絕緣層11G上。第三接塾nG配置於第二曰絕緣 層160之遠離第一絕緣層11〇的一表面164上，並位於第 201105187 uyu^uui 3155 ltwf，doc/n 一接塾140上方。線路部分190配置於表面164上並與第 二接塾170相連接。導電通道18〇貫穿第二絕緣層ι6〇並 連接第一接墊140與第三接墊170。 在本貫施例中’增層結構.A所包括的第二絕緣層 160、第三接墊170、線路部分190以及導電通道180的數 目僅為舉例說明，並非用以限定本發明。舉例來說，增層 結構A亦可包括多層相互堆疊的第二絕緣層16〇、多個分 ，酉^置於這些第二絕緣層160上的第三接墊170以及線路 部f 190，以及多個分別貫穿這些第二絕緣層16〇並連接 相鄰二第三接墊17〇或相鄰的第一接墊14〇與第三接墊 170的導電通道18〇。換言之，增層結構a可為一單層結 構或一多層結構。 值得〉主意的是，由於本實施例在第一通孔114中填入 填孔材料130，且填孔材料13〇的材質為摻有多個第二觸 媒顆粒的絕緣材料，因此，本實施例可在第二接墊152上 方的填孔材料130上形成第一接墊140。換言之，將填孔 ，料130配置於第一通孔114中可有助於疊孔設計，進而 可增加線路的設計彈性以及線路的佈局空間。 I +具體而言，若未於第一通孔114 _填入填孔材料13〇, 貝 =增加導電層12G的厚度以填滿第—通孔114。然而， ^電層=的生成速度慢，為了要將第-通孔114填滿則 而要相當長的沉積時間，當沉積時間過長時，導電層12〇 =表面平整度會下降’而無法進行後續的疊孔製程，而且 曰有信賴性的問題。此外，若未在第一通孔114中填入填 201105187 0905001 3l551twf.doc/n 孔材料130’亦可將第—接塾14〇形成在位於第—通孔川 第-絕緣層110的表面116上，但這將會降低線路 的政计彈性並減少線路的佈局空間。 。圖2A〜圖2F繪示本發明一實施例之線路板的製作流 ㈣剖面圖。值躲意的是，在圖2A〜圖2F的實施例中， 與圖1中的元件標號相同者，其材質亦相同於圖1之元件 的材質’故於此不再贅述。 首先，請參照圖2A，在本實施例中，提供一第一絕 緣層11G以及-線路基板15G，並將第__絕緣層ιι〇配置 於線，基板15G上，且第—絕緣層nG覆蓋線路基板15〇 的第一接Φ 152。接著，在本實施例中，例如以雷射燒 ，的方式移除第二接墊152上方的第—絕緣層ιι〇，以於 1第 絕緣層110上形成暴露出第二接墊152的一第一通孔 然後，請參照圖2B，在本實施例中，例如以化學沉 積的方式在第-通孔114的内壁114a以及第二接墊152 上形成二導電層120，且導電層12〇與第二接墊152電性 連接。詳細而言，由於以雷射燒蝕的方式所形成的第—通 孔114的内壁114a存在有多個已被活化的第一觸媒顆粒， f此，本實施例可藉由化學沉積製程將導電層120形成在 第通孔114的内壁114a上。如此一來，本實施例可藉由 雷射燒㈣方式定義出預定形成導電層m的位置，而毋 須以微影蝕刻的方式圖案化導電層。 之後，請參照圖2C，例如以塗佈或是其他適當的方 201105187 0905001 31551twf.doc/n 式將-填孔_ 13G填4 —觀n 圖2D，例如以雷射燒蝕的方彳矽搔者β月多’、、、 第一通孔m之-絕緣層110之鄰近 Γ ^ 以及填孔材料13G之位於開放端⑽The first insulating layer 110 has a recess 112 and a first through hole 114, wherein the recess 112 has a bottom portion U2a' and the first through hole 114 penetrates the bottom portion U2a and exposes the second pad 152. The conductive layer ι2 is disposed on the inner wall 114a of the first through hole 1H and the second pad 152, and is electrically connected to the second pad 152. The hole filling material 130 is filled in the first through holes 114. The first pad 140 is disposed in the recess 112 and covers the hole filling material 13 , the conductive layer 120 and the first insulating layer 11 , and is electrically connected to the conductive layer 12 . In addition, in this embodiment, the material of the first insulating layer 11〇 may be an insulating material doped with a plurality of first catalyst particles (not shown), and the material of the hole filling material no may be mixed with multiple Insulating material of two catalyst particles (not shown). The first catalyst particles and the second catalyst particles are adapted to be laser activated and a metal layer can be formed on the particles by the first catalyst particles and the second catalyst after the laser activation by a chemical deposition process. The material of the first catalyst particle or the second catalyst particle includes a metal coordination compound, and the material of the metal coordination compound may be a metal oxide, a metal nitride, a metal complex or a metal chelate, and the metal coordination The material of the compound may also be selected from the group consisting of zinc, copper, silver, gold, nickel, palladium, platinum, aluminum, cobalt, rhodium, ruthenium, iron, manganese, chromium, molybdenum, tungsten, sharp, button, indium and titanium. The group consisting of. In this embodiment, the structure A may also be formed on the first insulating layer 11 , and the build-up structure A includes a second insulating layer 16 ( ), a third ^ 170 , a conductive path 18 〇 , and a The line portion 19〇. The second insulating layer 1 (6) is disposed on the first insulating layer 11G. The third interface nG is disposed on a surface 164 of the second germanium insulating layer 160 away from the first insulating layer 11〇, and is located above the first layer 140 of the 201105187 uyu^uui 3155 ltwf, doc/n. The line portion 190 is disposed on the surface 164 and is coupled to the second port 170. The conductive via 18 〇 extends through the second insulating layer 〇6〇 and connects the first pad 140 and the third pad 170. The number of the second insulating layer 160, the third pad 170, the line portion 190, and the conductive via 180 included in the build-up structure. A in the present embodiment is merely illustrative and is not intended to limit the present invention. For example, the build-up structure A may further include a plurality of second insulating layers 16 相互 stacked on each other, a plurality of sub-layers, a third pad 170 disposed on the second insulating layers 160, and a line portion f 190, and A plurality of conductive vias 18B respectively extending through the second insulating layers 16 and connecting adjacent two third pads 17A or adjacent first pads 14 and third pads 170. In other words, the build-up structure a can be a single layer structure or a multilayer structure. It is worth noting that, in this embodiment, the first through hole 114 is filled with the hole filling material 130, and the material of the hole filling material 13 is an insulating material doped with a plurality of second catalyst particles. Therefore, the present embodiment For example, a first pad 140 may be formed on the hole-filling material 130 above the second pad 152. In other words, disposing the hole-filling material 130 in the first through-hole 114 can contribute to the stacking design, thereby increasing the design flexibility of the line and the layout space of the line. Specifically, if the first via hole 114 _ is not filled with the hole filling material 13 〇, Bay = increase the thickness of the conductive layer 12G to fill the first through hole 114. However, the generation rate of the electric layer = is slow, and a relatively long deposition time is required in order to fill the first through hole 114. When the deposition time is too long, the conductive layer 12 〇 = the surface flatness is lowered 'and cannot The subsequent stacking process is carried out, and there is a problem of reliability. In addition, if the first via hole 114 is not filled with 201105187 0905001 3l551twf.doc/n hole material 130', the first interface 14〇 may be formed on the surface 116 of the first through hole-first insulating layer 110. But this will reduce the political flexibility of the line and reduce the layout space of the line. . 2A to 2F are cross-sectional views showing a fabrication flow (four) of a circuit board according to an embodiment of the present invention. It is to be understood that in the embodiment of Fig. 2A to Fig. 2F, the same reference numerals are given to the elements of Fig. 1 and the materials thereof are the same as those of the elements of Fig. 1 and therefore will not be described again. First, referring to FIG. 2A, in the embodiment, a first insulating layer 11G and a circuit substrate 15G are provided, and the __ insulating layer is disposed on the line, the substrate 15G, and the first insulating layer nG is covered. The first connection Φ 152 of the circuit substrate 15A. Then, in the embodiment, the first insulating layer ι above the second pad 152 is removed, for example, by laser firing, to form a first exposed pad 152 on the first insulating layer 110. First via hole, then, referring to FIG. 2B, in the embodiment, a second conductive layer 120 is formed on the inner wall 114a of the first via hole 114 and the second pad 152, for example, by chemical deposition, and the conductive layer 12〇 The second pad 152 is electrically connected. In detail, since the inner wall 114a of the first through hole 114 formed by the laser ablation has a plurality of activated first catalyst particles, the present embodiment can be processed by a chemical deposition process. The conductive layer 120 is formed on the inner wall 114a of the first through hole 114. In this way, the position of the conductive layer m is predetermined to be defined by the laser firing (four) method, and the conductive layer is not patterned by photolithography. After that, please refer to FIG. 2C, for example, by coating or other suitable square 201105187 0905001 31551twf.doc/n, fill-filling _ 13G into 4 - view n Figure 2D, for example, by laser ablation The β month is ',, the first via hole m is adjacent to the insulating layer 110 and the hole filling material 13G is located at the open end (10)
絕緣層11(3上形成暴露出導制12M 的—凹槽112 °然後，請參照圖2E，例如以 化干儿積的方式在凹槽112中形成—第—接塾⑽，第一 130 ' 120 110上，並與‘電層12〇電性連接。 詳細而言，請同時參照圖2d與圖π，由於第一通孔 114斤中填有填孔材料130,且填孔材料13〇的材質為換有多 個弟-觸媒顆粒的絕緣材料，因此，在以雷射燒姓的方式 形成凹槽112之後，凹槽112的内壁112&存在多個已活化 的第二觸媒顆粒（與第-觸媒顆粒）。如此—來， 化學沉積製程直接在第-通孔114上方的凹槽112中开;成 第-接墊14G。換言之，本實施例在第—通孔ιΐ4中填入 填孔材料130可有助於後續的疊孔製程。 此外，在本實施例巾，由於第一絕緣層n〇的材質斑 填孔材料！3㈣材質皆為掺有多個觸媒顆粒的絕緣材料，、 因此，本實施例可以雷射祕的方式（或是其他適於活化 觸媒顆粒的方式）直接定義出預定形成導電層12〇與第一 接塾H0的位置，而毋須使用昂貴的光罩製程來圖案化導 層’故可降低製作成本並減少製程步驟。 之後，β參A?、圖2F，在本貫施例中，可於第一絕緣層 201105187 0905001 31551 twf doc/nThe insulating layer 11 (3 is formed to expose the guide 12M - the groove 112 °, then, please refer to FIG. 2E, for example, in the groove 112, formed in the groove 112 - the first connection (10), the first 130 ' 120 110, and electrically connected to the 'electric layer 12 。. In detail, please refer to FIG. 2d and FIG. π at the same time, because the first through hole 114 kg is filled with the hole filling material 130, and the hole filling material 13 〇 The material is an insulating material exchanged with a plurality of brother-catalyst particles. Therefore, after the groove 112 is formed by laser burning, the inner wall 112& of the groove 112 has a plurality of activated second catalyst particles ( And the first catalyst, the chemical deposition process is directly opened in the groove 112 above the first through hole 114; into the first pad 14G. In other words, the embodiment is filled in the first through hole ι4 The hole-filling material 130 can contribute to the subsequent lamination process. Further, in the towel of the embodiment, the material of the first insulating layer n〇 is filled with the material of the material; 3 (4) is an insulation doped with a plurality of catalyst particles. Materials, and therefore, this embodiment can be used in a laser-based manner (or other means suitable for activating catalyst particles) Directly defining the position where the conductive layer 12〇 and the first interface H0 are predetermined to be formed without using an expensive mask process to pattern the conductive layer' can reduce the manufacturing cost and reduce the process steps. After that, the β-A? 2F, in the present embodiment, can be in the first insulating layer 201105187 0905001 31551 twf doc / n
no上形成一第二絕緣層160。接著，形成貫穿第二絕緣層 160的一第二通孔162,且第二通孔162暴露出部分第一接 墊140。然後，於第二絕緣層16〇上形成一線路結構乙， 線路結構L包括一導電結構182、一第三接墊17〇以及一 線路。P刀190，其中導電結構182配置於第二通孔162中 並連接第一接墊140，第三接墊17〇配置於導電結構182 上亚位於第二絕緣層160之遠離第一絕緣層110的一表面 164上’線路部分19〇齔置於表面164上並與第三接墊 相連接。形成線路結構L的方法例如是先在第二絕緣層16〇 包括第二通孔162中）全面形成一導電層（未緣示）， 然後，圖案化導電層。 ‘上所述’由於本發明在第—絕緣層的第—通孔中填 的絕:孔I:的材質為摻有多個第二觸媒顆粒 一接巷。施士 本發明可在第一通孔上方直接形成第 孔#斗，兔^之，將填孔材料填入第一通孔中可有利於疊 間。再者，而可，加線路的設計彈性以及線路的佈局空 i有多個觸緣層的材質與填孔材料的材質皆為 钱的方式緣材料’因此’本發明可以雷射燒 出預定形成導電於化觸媒顆粒的方式）直接定義 光罩製程來圖接塾的位置’而毋須使用昂貴的 步驟。 本等笔層，故可降低製作成本並減少製程 雖然本發明 本發明’任何所 已以貫施例揭露如上，然其並非用以限定 屬技術領域中具有通常知識者，在不脫離 11 201105187 〇y〇5UUI 31551twf.doc/n 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1綠示本發明一實施例之線路板的剖面圖。 圖2A〜圖2F繪不本發明一實施例之線路板的製作流 程的剖面圖。A second insulating layer 160 is formed on the no. Next, a second via hole 162 is formed through the second insulating layer 160, and the second via hole 162 exposes a portion of the first via pad 140. Then, a circuit structure B is formed on the second insulating layer 16A. The circuit structure L includes a conductive structure 182, a third pad 17A, and a line. The P-knife 190, wherein the conductive structure 182 is disposed in the second via hole 162 and connected to the first pad 140, and the third pad 17 is disposed on the conductive structure 182 at a distance from the first insulating layer 110 of the second insulating layer 160. On a surface 164, the 'line portion 19' is placed on the surface 164 and connected to the third pad. The method of forming the wiring structure L is, for example, first forming a conductive layer (not shown) in the second insulating layer 16A including the second via hole 162, and then patterning the conductive layer. The above description is made by the present invention in the first through hole of the first insulating layer: the material of the hole I: is doped with a plurality of second catalyst particles. In the present invention, the first hole can be directly formed above the first through hole, and the filling of the hole filling material into the first through hole can facilitate the stack. Furthermore, the design flexibility of the added line and the layout of the line have a plurality of material of the contact layer and the material of the hole-filling material are all of the way of the material. Therefore, the present invention can be formed by laser firing. The way to conduct the catalyst particles is to directly define the mask process to map the location of the crucible' without the use of expensive steps. The present invention can be used to reduce the production cost and reduce the number of processes. Although the invention of the present invention has been disclosed in the above embodiments, it is not intended to limit the ordinary knowledge in the technical field, and does not deviate from 11 201105187 〇 y〇5UUI 31551twf.doc/n The scope of protection of the present invention is defined by the scope of the appended claims, and the scope of the invention is subject to the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a circuit board according to an embodiment of the present invention. 2A to 2F are cross-sectional views showing a manufacturing process of a wiring board according to an embodiment of the present invention.
150 線路基板 152 第二接墊 160 第二絕緣層 162 第二通孔 170 弟三接墊 180 導電通道 182 導電結構 190 線路部分 A :增層結構 L:線路結構150 circuit substrate 152 second pad 160 second insulation layer 162 second through hole 170 third pad 180 conductive channel 182 conductive structure 190 line part A: build-up structure L: line structure
【主要元件符號說明】 100 ·線路板 no :第一絕緣層 112 :凹槽 112a :底部 114 :第一通孔 114a :内壁 114b :開放端 116、164 :表面 120 :導電層 130 :填孔材料 140 :第一接墊 12[Main component symbol description] 100 • Circuit board no: First insulating layer 112: Groove 112a: Bottom 114: First through hole 114a: Inner wall 114b: Open end 116, 164: Surface 120: Conductive layer 130: Hole filling material 140: first pad 12