201104815 六、發明說明： 【發明所^之技術領域】 本&明係有關一種封裝基板，尤指一種具有較高之植 焊球良率之封農基板。 【先前技術] 隨著雷1 J2L戈 ^ 產業的蓬勃發展，電子產品也逐漸邁向多功 的趨勢。而為了滿S半導體封裝件高整合度 g n )及微型化（miniaturization )的封裝需求， 以供更夕主、破動元件及線路載接，半導體封裝基板亦逐 漸由雙層電路板演變成多層電路板（multi-layer board)， 以在有限的空間下運用層間連接技術（interlayer connect·)來擴大半導體封裝基板上可供利用的線路佈局 面積，並配合高線路密度之積體.電路（nnegmed⑽則 需要’而能達到封袭件輕薄短小及提高電性功能之目的。 、了而由於外路於封裝基板最外層的電性接觸塾的周 圍通常仍職Ϊ線路，因此必須以絕緣保護層（如防焊綠 漆層）R時覆盍於該線路與電性接觸墊的部並 於該絕緣保護層形成有外露部分電性接觸声 開孔，而該絕緣保護層係用以保護線路層及電性 分表面不受外界環境之空氣與水 觸。p 著封裝基板中的線路愈來愈細，電:接 來越小，藉以符合細線寬（flnellne) έ間之間距也越 的使用要求，但受限於現今曝光顯料：£(flnepitCh) 成較小之絕緣保護層開孔以顯 ^㈣，如欲形 r接觸塾之部分表面，201104815 VI. Description of the Invention: [Technical Fields of the Invention] This & Ming is related to a package substrate, especially a sealing substrate having a high yield of a solder ball. [Prior Art] With the booming development of the Ray 1 J2L Ge industry, electronic products are gradually moving toward multi-functionality. In order to meet the packaging requirements of high-integration gn and miniaturization of S-semiconductor packages, the semiconductor package substrate is gradually evolved from a two-layer circuit board into a multi-layer circuit for the main assembly, the broken component and the line carrier. Multi-layer board, which uses the interlayer connection technology to expand the layout area available on the semiconductor package substrate in a limited space, and cooperates with the high line density. Circuit (nnegmed(10) Need to 'can achieve the purpose of the light and thin parts and improve the electrical function. And because the external contact of the outermost layer of the electrical contact with the outer layer of the package is usually still working, so the insulation layer must be The anti-welding green lacquer layer) is covered with the portion of the circuit and the electrical contact pad, and the exposed protective portion is formed with an exposed portion electrically contacting the acoustic opening, and the insulating protective layer is used for protecting the circuit layer and the electric layer. The surface of the character is not exposed to the air and water of the external environment. The line in the package substrate is getting finer and finer, and the electricity is smaller, which is in line with the fine line width (flnellne). Also from the use requirements, but significantly limited by the current exposure material: £ (flnepitCh) into smaller openings in the insulating protective layer portion substantially iv ^, r To form the contact surfaces of Sook,
A 111284 201104815 常有對位不率 ^ ⑽移或是題甚::成-緣保護層開 或焊球’故業界遂發;Γ==觸面積，凸塊 直接形成外部電1 一種於該增層線路層之㈣ 圖。、用前述技術的習知封裝基板6:艾^ 如第1圖戶斤-. 層線路結構 < 其丁白知之封裝基板係包括：内邻| * 二二 笛 是數弟—電性連接墊lla蛊筻^ 〇 知叹於該第〜表面 ，、弟—線路12a， -表面他、該此第2 介電層A，，'設㈣第 複數乐―電性接觸墊】 二弟一線路仏 連接墊…位置之第—介電声又於各該第-電性 塾…藉由設於該第一介料13的^該第一電性接觸 =性連接至各該第-電性連接墊lla /電盲孔⑸ 3 llb與第二線路〗2b，係設於該第」：數第二電性連 m與該些第二線路】㉛上，·複數第二〜電性連接 對應設於各該第二電性連接墊】】b 性接觸墊】仆， 】3b上，且該第二電性接觸塾]4b與由：置之第二介電層 ^中的第二導電盲孔15b以電性該第二介電層 11 b ;焊球16 a，係設於各該第忒弟二電性連接 踢凸塊⑽’係設於各該 ：接，上β 电注接觸墊Mb上；以及半 111284 5 201104815 導體晶片18’係接置於該基板本體川' 該半導體晶片18係具有作用面l8a，第二表面10b上， 18a上的電極墊181，該些電極墊丨幻錡複數設於該作用面 以電性連接至各該第二電性接觸墊糸藉由焊錫凸塊16b 惟，習知技術係於原有的第一及。A 111284 201104815 There is often a mismatch rate ^ (10) shift or the question is very:: into the edge protection layer open or solder ball 'the industry burst; Γ = = contact area, the bump directly forms external electricity 1 (4) diagram of the layer circuit layer. The conventional package substrate 6 using the foregoing technology: Ai ^, as shown in Fig. 1 - layer circuit structure < Ding Bai Zhizhi package substrate system includes: inner neighbor | * two two flutes are several brothers - electrical connection pads Lla蛊筻^ 〇 〇 该 该 该 表面 表面 表面 表面 表面 表面 表面 表面 表面 表面 表面 表面 表面 表面 表面 表面 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路Connecting the pad...the first part of the position - the dielectric sound is further connected to each of the first electrical contacts by the first electrical contact provided on the first dielectric 13 Lla / electric blind hole (5) 3 llb and second line 〖2b, is set in the first: the second electrical connection m and the second line] 31, the second plurality of electrical connections are correspondingly Each of the second electrical connection pads 】b-type contact pads servants, 】 3b, and the second electrical contact 塾 4b and: the second conductive blind holes 15b in the second dielectric layer The second dielectric layer 11b is electrically connected to each of the second electrical connection kicking bumps (10)' on each of the upper and lower beta electrical contact pads Mb. ; and half 111284 5 201104815 The conductor wafer 18' is connected to the substrate body. The semiconductor wafer 18 has an active surface 18a, an electrode pad 181 on the second surface 10b, 18a, and the electrode pads are disposed on the active surface. Electrically connected to each of the second electrical contact pads by solder bumps 16b, the prior art is based on the original first.
Ub上的第一、第二介電層〜電性連接墊na， 板外部第一及第二電性接觸墊j4a，if面分別形成封裝基 外表面並未佈設線路層，故其最外枣4b，由於封裝基板最 保護層，而可完全顯露第一及第二雷面不再另外施加絕緣 表面，藉以避免原本於絕.緣保護層開接觸堅14a，州 部分之表面時，會有對位不準及^以顯露電性接觸整 成絕緣保護層開孔偏料是顯露開2衫佳、甚而造 於智知技術並未有絕緣保護層開孔=等=題’但由 該第-電性接觸墊14a表面時，於二焊球他於 球1 ~過私·中’會使該焊 王現液態’而導致焊無絕緣保護層開孔之區域 /而產生溢流；又由於該第一電性接觸塾…表面平 且無絕緣保護層開孔偈限一空間，易使該焊球！ 6 &產 〜脫落掉球的情況，並使得植設該焊球16 a之製程不易進 ""^而造成該焊球脫洛或焊料溢流導致橋接等問題。 因此，如何避免習知技術中外部之電性接觸塾容易造 成後續焊球的脫落或焊料溢流導致橋接等問題，實已成為 目珂亟欲解決的課題。 【發明内容] 鍛於上述習知技術之種種缺失，本發明之一目的係提 111284 6 201104815 供一種能避免焊球脫落之封裝基板。 •本發明之又一目的係提供—種能避免焊料溢流導致 橋接之封裝基板。 為達上述及其他目的，本發明揭露一種封褒基板，係 •包括：基板本體，係具有第-表面及對應該第一表面之第 二表面；複數第-電性連接墊，係設於該第—表面上；第 二=\係設於該第-表面與該些第—電性連接塾上， 二二:電層之表面具有複數對應各該第 弧:凹部;以及複數第1性接觸墊，係對庵設於 各邊弟一弧形凹部上，且各兮 mu、 第—介電； ^弟'電性接觸墊藉由設於該 前述之封裝基板中，復包//具有第二弧形凹部。 表面上’且該第-介電層並設於t:第一=路:設於該第-The first and second dielectric layers on the Ub are electrically connected to the pad na, and the first and second electrical contact pads j4a on the outer surface of the board respectively form the outer surface of the package base, and no circuit layer is disposed, so the outermost date 4b, due to the most protective layer of the package substrate, the first and second lightning surfaces can be completely exposed without additionally applying an insulating surface, so as to avoid the original surface of the state portion of the protective layer Inaccurate and ^ to expose the electrical contact, the integrity of the protective layer of the opening material is revealed to open 2 shirts, even made in the wisdom of technology does not have insulation protective layer opening = equal = title 'but by the first - When the surface of the contact pad 14a is electrically contacted, in the case of the second solder ball, the ball will be in a liquid state, which will cause the soldering king to be in a liquid state, resulting in an area where the insulating layer is not opened and overflowing; The first electrical contact 塾...the surface is flat and there is no insulation protection. The opening is limited to a space, which makes the solder ball easy! 6 & production ~ the situation of falling off the ball, and making the process of planting the solder ball 16 a difficult to enter "" ^ caused the solder ball detachment or solder overflow caused by bridging and other issues. Therefore, it has become a problem to be solved by how to avoid the external electrical contact in the prior art, which is liable to cause the subsequent solder ball falling off or the solder overflow to cause bridging. SUMMARY OF THE INVENTION For the above-mentioned various deficiencies of the prior art, one of the objects of the present invention is to provide a package substrate capable of preventing solder balls from falling off. Another object of the present invention is to provide a package substrate that avoids solder overflow resulting in bridging. To achieve the above and other objects, the present invention discloses a package substrate, comprising: a substrate body having a first surface and a second surface corresponding to the first surface; and a plurality of first electrical connection pads disposed thereon On the first surface, the second surface is disposed on the first surface and the first electrical connection ports, and the surface of the second electrical layer has a plurality of corresponding arcs: a concave portion; and a plurality of first sexual contacts The pad is disposed on an arcuate recess of each of the brothers, and each of the 兮mu, the first dielectric; the brother's electrical contact pad is provided in the aforementioned package substrate, and has a Two curved recesses. On the surface and the first dielectric layer is disposed at t: first = way: set in the first
上，又復可包括笛- A 二表面與該些第二電性連接墊上。1電層，係設於該第 第 塾 上 二復可包括第二線路，係設於該 依上所述之封裳X:層f設於該第二線路上。 ’係對應設於各心：了包括複數第二電性接觸 ，且各該第二電連接塾位置之第二介電層 導電盲孔以電性連接至第::::該第二介電層中的第 又於前述之封W板；/ 弟〜導電盲孔係可由第— 111284 7 201104815 =料層與_所疊合構成’而該第—焊料層钱連接第二 兔性連接塾’又該_電性祕帛：紐接觸塾。The upper surface may further include a flute-A surface and the second electrical connection pads. An electrical layer is disposed on the first layer. The second layer may include a second line, and the layer X is disposed on the second line. The system is disposed in each core: a second dielectric contact blind hole including a plurality of second electrical contacts, and the second dielectric layer conductive blind holes of each of the second electrical connection ports are electrically connected to the first:::: the second dielectric The first layer in the layer is the same as the above-mentioned sealing W plate; / Di ~ conductive blind hole can be composed of - 111284 7 201104815 = material layer and _ overlap and the first - solder layer money connection second rabbit connection 塾 ' Another _ electrical secret: New Zealand contact.
引叙封裝基板復可包括第二焊料層，係設於該第二 堯性接觸塾上，且復可肖括裳_·、ρθ M 性接觸塾上。设了匕括弟二㈣層，係設於該第一電 傳星揭露另-種縣基板，係包括：基板本體， 海：有士-表面；複數第一電性連接塾，係設於該第一表 接塾/ —^層’ _於_ —表面與該些第—電性連 第一,^介電層之表面具有複數對應外露出各該 *，c:第:弧形凹部;以及複數第-電性接觸 T'彳應⑧於各該第—弧形凹部上 各该第-電性連㈣H㈣^ 接紐連接至 第二^^部。 各該弟-電性接觸塾之表面具有 表面Γ=Γ=’復包括第一線路，係設於該第- 且該第一）,電層並設於該第一線路上。 連接备上，之基板中’該基板本體復可包括複數第Ί 係設二表面上;又復可包括第二介;Γ ;該弟二表面與該些第二電性連接塾上。 e’ 第二===復可包括第二線路〜 於本發明之另-實施=1中設於該第二線路上。The package substrate may include a second solder layer disposed on the second conductive contact, and may be disposed on the contact surface. The second (four) layer is set up in the first electronic transmission star to expose another substrate of the county, including: the substrate body, the sea: the gentleman-surface; the plurality of first electrical connections, which are The first surface of the first layer is connected to the surface of the first layer, and the surface of the dielectric layer has a plurality of corresponding surfaces to expose the respective *, c:: arcuate recesses; The plurality of first-electrode contacts T' 88 are connected to the second portion of each of the first-electrical (4) H(four)^ contacts on each of the first arcuate recesses. The surface of each of the electrical-contact pads has a surface Γ = Γ = 'including a first line, which is disposed at the first - and the first), and the electrical layer is disposed on the first line. In the substrate, the substrate body can include a plurality of second surface structures; and a second dielectric layer; and the second surface is connected to the second electrical connections. e' The second === complex may include the second line ~ is set on the second line in the other embodiment of the present invention.
隹觸苳，係對應設於各該第；:设可包括複數第二電性 !上，-且各該第二電性接接 卑-導電盲孔以電性連接至該苐二電"，广亥弟一介電層中> ηΐ284 8 201104815 , 又於前述之封裝基板中，玆曾 焊料層與銅層所A八燼 蛤笔目孔係可由第- 電性連接塾，又電性連接第二 前述之封裝基板中復可包：：性接觸墊。 二電性接觸墊上，且復 料層，係設於該第 電性接觸墊上。 —·θ料層，係設於該第一 層内苦^第可知=發明之封裝基板係於覆蓋於該第一介電 心二的上方對應形成外部之第-電： 的第二:電性連接塾係藉由設於該第一介雷居Φ =卓—導電盲切電性連接至 ^ 4層中 於該外部^2觸塾之表面具有弧形凹部，因而後續 形成焊球以供接复复:::二:成第二焊料層’經回焊後 性接觸塾的接觸二該焊球與外部之第-電 3之_著力較二而不易有==.= 動範圍，使得各該焊二 壯，X 匕接觸而泣成橋接等問題。故相較於羽4 二《明:封裝基板具有能增進後續植焊球之二 、良十，亚有利於細間距之產品設計等優點。 、 【實施方式】 以下藉由寸定的具體實施例說明本發明之實 L ’热悉此技人士可由本說明書 瞭解本發明之其他優點及功效。 易地 一實施例] 111284 9 201104815 請參閱第2A及2B F1义么也 圖，係為本發明所揭露之一種封 I基板的剖視示意圖，1中 ^ ^ 八中，弟2B圖係為第2A圖之封萝 土板形成焊球與接置半導體晶片後<剖視示意圖。、 A板:二2:及示，本發明之封裝基板，係包括: 基板“20、碰第—電性連㈣… 以及複數第一電性接觸墊24a。 电《 23a、 =之基板本體第，施及 表面2〇a之第二表面2%。 ^弟 所述之複數第-電性連接墊 2〇之第-表面2Ga上。 係叹於該基板本體 ，面/广，第Η A層、_於該基板本體2。之第-表面20:與該些第1性連接塾％上， 23a之表面具有複數對應各該第1性 4層 弧形凹部230a。 a之弟一 所述之複數第-電性接 弧形凹部230a上，且各兮笛 仏對I又於各該第― 莖入年 各該第—電性接觸墊24a藉由 弟—介電層23a中之第—導 碏由D又於该 -電性連接墊2U，且各：：目:L…以電性連接至該第 有第二弧形凹部240a 4一电性接觸塾％之表面具 於本發明之封裝基板中 之第二表面20b上之第括。又於該基板本體2〇 弟一電性連接墊2ib。 依上射之封f基板，該基板本體2 上设設有複數第一線路22a，而該㊉弟表面2〇a 該第一線路22a上.4 1 μ "电層23a亦設於 上，且喊板本體20之第二表面應上亦 111284 10 201104815 設有複數第二線路22b。 所述之封裝基板復包括第—八 板本體20之第二表面m、第，係設ί該基 路22b上；且復包括複數第^21b與第二線 於各該第二電性連接墊21b =觸f糾，係對應設 各該第二電性接總—意之弟二介電層23b上，且 第二導電盲孔25b f错由设於該第二介電層2儿中的 於本實::中以， 251 b與銅層252b所電盲孔25b係由第—嬋料層 曰所璺合構成，令筮.θ ,. 接該第二電性連接墊21b，而，：弟一㈣層251b電性連 電性接觸墊24b n μ層咖電性連接該第二 .,然而，於其他實施例中，哕篦-道+亡 = 25b與第二電性接觸墊爲亦可為 導笔目 式表示），並不限於上t ”體所構成（未以圖 第二之封I基板復可包括第二烊料層 一电性接墒墊24b上，且復可包括第_ °又；k 於該第-電性接物如上 弟二焊料層27’係設 第三么裝基板中’復可將第—電性接觸塾24a上的 杯抖層27經高溫回焊後形成焊球 凡件，如第2B圖所示。 乂供接置外部電子 【於前述之封裝基板中，復可於該基板本體2 、面2〇b上接置半導體晶片28，該 、 有作用面如與複數設於該作用* ^系具 該些電極伽係藉由第二焊料層 二電性接觸塾細，如第2B圖所示。❹連接至各該第 111284 11 201104815 [第二實施例j 請參閱第3圖， 的剖視示意圖。 本發明所揭露之另-種封裝基板 如第3圖所示， 體20、複數第—電性連;妾:之:裝基板，係包括:基板本 複數第一電性接觸墊24a。 弟—介電層23a、以及 所述之基板本體二 一表面2〇a之第二表面2%、 表面2如及對應該第 所述之複數第一 20a上。 連接墊21a係設於該第—表面 所述之第—介雷展 ^ 表面2Ga與該此第J 3係設於該基板本體20之第一 一弟一電性連接塾 =之表面具有複數對應外露出各該弟一介電層 之第一弧形凹部23〇a。 “乐包性連接墊21a 孤形St第;電性，塾加鱗 21a，且各該第—電性d連接至各該第-電性連接塾 24〇a。 墊4a之表面具有第二弧形凹部 一表面2〇b上之第二電性連接塾⑽。 弟 ^本，施例中，該基板本體2G之第一表面施上復 =弟-線路办，而該第一介電層仏亦設於該第' 線 ，且該基板本體20之第二表面20b上亦設有第二 線路22b。 111284 12 201104815 Λ 所ki之封裝基板4复包括第二人泰 板本體20之第二表面％ 丨电自23b，係設於該基 路22b上，·且復包括複數第-1=連接塾2ib與第二線 於各該第二電性連接塾置：麵 =二電性接觸墊24b藉由設於==上，且 弟二導電盲a、系弟一介電層23b中之 於4中以電性連接至該第二電_ 、c*例中’該第二違_ 亡^ 52仆係-體所構成；然二』===二電性接觸 】盲孔㈣可由第-焊料層舆銅m二導 焊料層電性連接該第二電 構成’其中該 括第二焊料層I T 又所述之封錄板復可包 可包括第三焊料層(未以圖t::二:久上’且復 接觸墊24a上。 ’、 ’卞°又衣5玄第一電性 層内部之發明之封裝基板係於覆蓋於該第-介带 接觸塾，且該：！連接塾的上方對應形成外部之第〜電= 的第—導+ :昂電性連接塾係藉由設於該第-介電声ψ 上弟h盲孔以電性連接至1電層中 Θ外部之第 d接觸| ’又 於該外部之第ι=:具有弧形凹部，因而後續 形成焊球叫接t接触上形成第二焊•，經回焊後 性接觸塾的接觸子裝置，該焊球與外部之第一電 觸塾之間的接大，使該焊球與外部之第1性接 該弧形凹部也會限焊球脫落之情形；再者， 制。玄烊球的移動範圍，使得各該焊球 111284 201104815 易掉球、或因彼此接觸而造成橋接等問題。故相較於習知 技術，本發明之封裝基板具有能增進後續植焊球之加工製 程的良率並有利於細間距之產品設計等優點。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利、保護範圍，應如後述之申請專利範 圍所列。 [圖式簡單説明] 第1圖係為習知之封裝基板的剖視示意圖； 第2A及2B圖係為本發明之封裝基板之第一實施例 的剖視示意圖，其中，第2B圖係為第2A圖之封裝基板形 成焊球與接置半導體晶片後之剖視示意圖；以及 第3圖係為本發明之封裝基板之第二實施例的剖視示 意圖。 【主要元件符號說明】 10 ' 20 基板本體 10a ' 20a 第一表面 10b 、 20b 弟—表^面 11a ' 21a 第一電性連接墊. lib 、 21b 第二電性連接墊 12a、22a 第一線路 12b ' 22b 第二線路 13a、23a 第一介電層 14 111284 201104815 '13b 、 23b ' 14a、24a 14b 、 24b 15a ' 25a 15b 、 25b 16a 16b 18、28 # 18a > 28a 181 、 281 230a 240a 251b 252b 26 第二介電層 第一電性接觸墊 第二電性接觸墊 第一導電盲孔 第二導電盲孔 焊球 焊錫凸塊 半導體晶片 作用面 電極墊 第一弧形凹部 第二弧形凹部 第一焊料層 銅層 第二焊料層 第三焊料層 15 111284隹 苳 苳 苳 苳 苳 苳 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : , 广ΐ弟一 dielectric layer> ηΐ284 8 201104815 , and in the above-mentioned package substrate, the solder layer and the copper layer A can be connected to the first electrical connection, and electrically Connecting the second package substrate in the foregoing package:: a sexual contact pad. The second electrical contact pad and the composite layer are disposed on the first electrical contact pad. The θ material layer is provided in the first layer. The package substrate of the invention is connected to the first dielectric core 2 to form an external first electric: second: electrical The connecting lanthanum has an arc-shaped recess on the surface of the external yoke by being disposed in the first smear-conducting-conductive blind-cut electrical connection to the layer 4, thereby forming a solder ball for subsequent connection Reconstruction:::2: into the second solder layer 'after the reflow soldering contact 塾 contact two, the solder ball and the external first - electricity 3 _ force is less than easy ==.= moving range, so that each The welding is strong, X 匕 contact and weeping into a bridge. Therefore, compared with Yu 4 2 "Ming: the package substrate has the advantages of improving the subsequent welding of the ball, the good ten, and the sub-optimal fine pitch product design. [Embodiment] The following description of the present invention will be made by the specific embodiments of the present invention. Other advantages and effects of the present invention will become apparent to those skilled in the art. An embodiment of the invention] 111284 9 201104815 Please refer to the 2A and 2B F1, which is a schematic cross-sectional view of a sealed I substrate disclosed in the present invention, wherein 1 ^ 8 is in the middle, and 2B is the first 2A is a schematic cross-sectional view showing the formation of a solder ball and a semiconductor wafer after the formation of the solder ball. , A board: 2: and shown, the package substrate of the present invention includes: a substrate "20, a touch-electro-connection (four) ... and a plurality of first electrical contact pads 24a. Electric "23a, = substrate body Applying the second surface of the surface 2〇a to 2%. ^The plurality of first-electrical connection pads 2' on the surface-surface 2Ga. The system is sighed by the substrate body, surface/wide, and the third layer The first surface 20 of the substrate body 2 has a plurality of surfaces corresponding to the first and fourth arcuate concave portions 230a on the surface of the first surface connection 塾%. a plurality of first-electrode arcuate recesses 230a, and each of the cymbal cymbal pairs I in each of the first stalks of the first electrical contact pads 24a is guided by the first in the dielectric layer 23a碏D is further connected to the electrical connection pad 2U, and each of:: mesh: L... is electrically connected to the second second arcuate recess 240a. The surface of the electrical contact 塾% is provided in the package of the present invention. The second surface 20b of the substrate is included in the substrate. The substrate body 2 is electrically connected to the pad 2ib. The substrate body 2 is provided with a plurality of first lines 22a. The tenth surface 2〇a of the first line 22a is disposed on the first line 22a. The electric layer 23a is also disposed on the upper surface, and the second surface of the board body 20 is also 111284 10 201104815. The second line 22b is provided. The package substrate includes a second surface m of the eighth-plate body 20, and is provided on the base 22b; and includes a plurality of 21b and the second wire on each of the second electrical connection pads 21b = touch f correction, corresponding to each of the second electrical connection - the second dielectric layer 23b, and the second conductive blind hole 25b f is provided in the second dielectric layer 2 In the present embodiment: 251b and the copper layer 252b, the electric blind hole 25b is formed by the first layer of the tantalum layer, so that 筮.θ,. is connected to the second electrical connection pad 21b, The second (four) layer 251b electrically connected contact pads 24b n μ layer is electrically connected to the second. However, in other embodiments, the 哕篦-channel + death = 25b and the second electrical contact pad are It can also be represented by a guide pen), and is not limited to the upper t" body (not including the second cover of the I substrate, including the second layer of an electrical contact pad 24b, and the The first _ ° again; k in the The first electrical contact is as described above, and the second solder layer 27' is provided in the third package substrate, and the cup shake layer 27 on the first electrical contact 塾 24a is reflowed by high temperature to form a solder ball piece, such as 2B is a view of the external electronic device. [In the above-mentioned package substrate, the semiconductor wafer 28 can be attached to the substrate body 2 and the surface 2b, and the active surface is provided in the plurality. The function * ^ is the electrode galaxies which are thinned by the second solder layer, as shown in Fig. 2B. ❹Connected to each of the 111284 11 201104815 [Second Embodiment j See FIG. 3, a schematic cross-sectional view. Another type of package substrate disclosed in the present invention is as shown in Fig. 3, the body 20, the plurality of first electrical connections, and the substrate: the substrate includes a plurality of first electrical contact pads 24a. The dielectric layer 23a, and the second surface 2% of the surface 2a of the substrate body 2, the surface 2 and the plurality of first 20a corresponding to the first. The connection pad 21a is disposed on the surface of the first surface, and the surface of the first surface of the substrate body 20 is electrically connected to the surface of the first substrate The first curved recess 23a of each of the dielectric layers of the younger brother is exposed. "Legging connection pad 21a is solitary St; electrical, 塾 scaled 21a, and each of the first electrical connection d is connected to each of the first electrical connection ports 24A. The surface of the pad 4a has a second arc a second electrical connection 塾(10) on a surface 2〇b of the concave portion. In the embodiment, the first surface of the substrate body 2G is applied with a second dielectric layer, and the first dielectric layer is The second line 22b is also disposed on the second surface 20b of the substrate body 20. 111284 12 201104815 封装 The package substrate 4 of the ki includes the second surface of the second person board body 20 % 丨 from 23b, is disposed on the base 22b, and includes a plurality of -1=connecting 塾2ib and a second line in each of the second electrical connections: face=two electrical contact pads 24b By setting it on ==, and the second conductive blind a, the middle of a dielectric layer 23b is electrically connected to the second electrical _, c* in the case of the second violation _ die ^ 52 servant-body composition; second two === two electrical contact] blind hole (four) can be electrically connected to the second electrical layer by the first solder layer 舆 copper m two-conductive solder layer 'where the second solder layer IT said the seal The multi-layer package may include a third solder layer (not shown in the figure t:: two: long on the complex contact pad 24a. ', '卞° 又 又 5 第一 玄 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一Covering the first-dielectric contact 塾, and the upper portion of the :: connection 塾 corresponds to forming an external first-to-electrical-conductance +: an galvanic connection 藉 is provided by the first-dielectric sonar The blind hole of the upper brother is electrically connected to the dth contact outside the outer layer of the electric layer | 'and the first dimension of the outer portion has an arc-shaped recess, so that the subsequent formation of the solder ball is called the contact of the t-contact to form the second solder. • After the reflowed contact contact device, the connection between the solder ball and the external first contact is large, so that the first ball of the solder ball and the outer portion of the arc is also limited. In the case of the ball falling off; in addition, the movement range of the Xuanqi ball makes the solder balls 111284 201104815 easy to drop the ball, or cause bridging due to contact with each other, so the package of the present invention is compared with the prior art. The substrate has the advantages of improving the yield of the subsequent processing process of the solder ball and facilitating the product design of the fine pitch. The present invention is exemplified to exemplify the principles of the present invention and its effects, and is not intended to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. The scope of the invention and the scope of protection should be as described in the scope of the patent application described below. [Simplified illustration of the drawings] Fig. 1 is a schematic cross-sectional view of a conventional package substrate; Figs. 2A and 2B are package substrates of the present invention. FIG. 2B is a cross-sectional view showing a package substrate of FIG. 2A after forming a solder ball and a semiconductor wafer; and FIG. 3 is a package substrate of the present invention. A schematic cross-sectional view of a second embodiment. [Main component symbol description] 10 ' 20 substrate body 10a ' 20a first surface 10b, 20b - surface 11a ' 21a first electrical connection pad. lib, 21b second electrical connection pad 12a, 22a first line 12b ' 22b second line 13a, 23a first dielectric layer 14 111284 201104815 '13b , 23b ' 14a, 24a 14b , 24b 15a ' 25a 15b , 25b 16a 16b 18 , 28 # 18a > 28a 181 , 281 230a 240a 251b 252b 26 second dielectric layer first electrical contact pad second electrical contact pad first conductive blind hole second conductive blind hole solder ball solder bump semiconductor wafer active surface electrode pad first curved recess second curved recess First solder layer copper layer second solder layer third solder layer 15 111284