201104813 八、發明說明： 【發明所屬之技術領域】 本發__-種縣基板及其製法，尤指 見象及提供細間距線路之繼板及其製法 於-騎刷電路板或半導體封裝基板中之金屬層形 ^路圖案化之線路層時，_即為經常使用之方式:其 之濕姓刻法（Wet Etching)乃為經濟 八 故為最早被採用在封錄板製程中之量產方法/技術’ 請，第1A請圖，係為f知縣基板之渴關 衣法不思圖。如第1A圖所示，提供一雙面具有㈣ ^核心板1〇 ’於該核心板10中先形成貫穿之通孔職 再於該銅WOa及軌⑽^孔壁上 及金屬層12’以於該核心板1。之通孔 孔·如第1B圖所示，於該金屬,12上以 (以㈣叩ing)形成係為乾膜之圖案化阻層13 ,且㈤且= 13具有複數開口區13〇,以外露出部分之金 =k 即藉由該阻層13以覆芸住欲带点古 ^ 表面， WCFH i 化之線路結構；如 弟1C圖所不’再以濕關移除各該開口^ 層12、導電層1丨及銅m㈣成電性連接該導電Z 1〇0之線路層14;如第1D圖所示，移除該阻層13=i 出該線路層14及部份核心板1〇表面。 卜路 ，惟，由於上述濕I虫刻法係藉由姓刻液與特定材料 學反應所致，該蝕刻液對於材料侵蝕並沒有特定的方向 η201104813 VIII. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a substrate of a county and a method for manufacturing the same, and more particularly to a substrate and a method for manufacturing a fine pitch line and a method for manufacturing the same on a brushed circuit board or a semiconductor package substrate In the case of the metal layer-shaped patterned circuit layer, _ is the method of frequent use: its Wet Etching method is the first mass production of the economy in the process of the seal plate process. Method/Technology' Please, please refer to the 1st AA. As shown in FIG. 1A, a double-sided (4) core plate 1〇' is formed in the core plate 10 to form a through hole and a hole is formed on the copper WOa and the rail (10) hole wall and the metal layer 12'. On the core board 1. Through hole hole, as shown in FIG. 1B, a patterned resist layer 13 which is a dry film is formed on the metal 12 by (four) , ing, and (f) and = 13 have a plurality of open regions 13 〇, The exposed part of the gold = k is covered by the resist layer 13 to cover the surface of the ancient surface, WCFH i line structure; if the brother 1C figure does not 'remove the opening ^ layer 12 The conductive layer 1丨 and the copper m(4) are electrically connected to the circuit layer 14 of the conductive Z 1〇0; as shown in FIG. 1D, the resist layer 13=i is removed from the circuit layer 14 and a part of the core board 1〇 surface. Bu Lu, however, because the above wet I insect engraving method is caused by the reaction of the surname engraving with the specific material, the etching solution has no specific direction for material erosion.
J ]】】278 201104813 性，而為一等向性（Isotropic)蝕刻；因此，當向下蝕刻 時，將導致如第1C圖所示之阻層13底部有部分線路層14 被侵姓而損失線寬，而產生底切（Undercut)現象C，因 此在濕蝕刻法中需預留更大的線寬，以彌補該底切現象C 之線寬損失，故無法形成細小的線寬及線距。 為避免底切現象的發生，遂發展出其他利用I虫刻法之 製程，例如圖案轉移（patterning )製程或半加成（SAP ) 製程。 請參閱第2A至2D圖’係為習知封装基板之圖案轉 移製法示意圖。如第2A圖所示，提供一雙面具有銅箔2〇a 之核心板20 ’且於該核心板20中形成通孔2〇〇a，並於該 銅羯20a及通孔200a之孔壁上形成導電層21，再於該導 電層21上形成係為乾膜之阻層2 開口區230，以外霪屮都公 〇，且該阻層23形成複數J]] 278 201104813, but an isotropic etching; therefore, when etched down, it will cause part of the circuit layer 14 at the bottom of the resist layer 13 as shown in Fig. 1C to be invaded The line width produces an undercut phenomenon C. Therefore, a larger line width is reserved in the wet etching method to compensate for the line width loss of the undercut phenomenon C, so that a small line width and line spacing cannot be formed. . In order to avoid the undercut phenomenon, other processes using the I-like method, such as a patterning process or a semi-additive (SAP) process, have been developed. Please refer to FIGS. 2A to 2D for a schematic diagram of a pattern transfer method of a conventional package substrate. As shown in FIG. 2A, a core plate 20' having a copper foil 2〇a on both sides is provided, and a through hole 2〇〇a is formed in the core plate 20, and a hole wall of the copper plate 20a and the through hole 200a is formed. A conductive layer 21 is formed thereon, and an open region 230 of the resist layer 2 which is a dry film is formed on the conductive layer 21, and the outer layer is open, and the resist layer 23 forms a plurality
板30中形成通孔300a，並於該核心 ]]]278 4 201104813 板30及通孔300a之孔壁上形成導電層31，再於該導電層 .31上形成係為乾膜之阻層33，且該阻層33形成複數開口 區330，以外露出部分之導電層31表面；如第3B圖所示， 於各該開口區330中之導電層31上電鍍形成金屬層32; 如第3C圖所示，移除該阻層33，以露出未為該金屬詹32 所覆蓋之導電層31表面；如第3D圖所示，#刻移除該外 露之導電層31及金屬層32之部分表面，以於該核心板30 上形成線路層34，且於該通孔300a中形成電性連接該線 •路層34之導電通孔300。 惟，習知圖案轉移及半加成之製法中，該阻層23,33 係作為電鍍阻層，以電鍍金屬於該開口區230,330中之導 電層21,31上；當移除該阻層23,33時，該阻層23,33之乾 膜材易殘留於該線路層24,34之間，即所謂之夾膜現象， 以致於當蝕刻移除該阻層23,33所覆蓋之導電層21,31 時，無法完全移除乾淨，如第2D及3D圖所示之乾膜材及 φ 其覆蓋之導電材S，該線路層24,34易電性導通殘存之導 電材S而造成短路；前述夾膜現象於細間距線路製程影響 更為明顯，意即因線路之間的間距更為狹小，以致於線路 之間的阻層23,33及其所覆蓋的導電層21,31更不易移除 乾淨，而該線路層24,34更易因殘存之導電材S而發生短 路，因此限制了細間距線路製程的發展。 因此，鑒於上述之問題，如何避免習知技術中之底切 現象及夾膜現象所衍生之問題，實已成目前亟欲解決的課 題。 111278 201104813 【發明内容】 鑑於上述習知技術之種種缺失，本 供一種避免發生底切現象之封裳基板及其製法。 本發明之另一目的係才法 板及其製法。 &供種細間距線路之封裝基 為達上述及其他目的，本 包括:基板本發’係具有貫穿之通”基板’係 該通孔中，且係由導電層及、入h通孔，係設於 層，係設於該基板本體：，：雷二蜀層所構成；以及線路 今fla上以電性連接带 線路層係由銅層、導電層及電鍍金屬 电、，“ 路層之導電詹係覆於該銅層之 S f成’其中該線 完整包覆唁導雷思 * 表面，而該電鐘金屬層並 兀正已復3導電層之上表面與銅層之 具有複數電性接觸墊。 表面，又該線路層 刖述之封裴基板中’該基板本體係 板或具有内部線路之線路板，且該 ^夕層板、兩層 線塾、覆晶燁塾或植球塾。 _ ^接觸塾係可為打 則返之封I基板復可包括防焊層 及線路層上，且該防焊層中具有複數開孔，以二本肢 觸塾露出於該開孔；較佳地，復可包 7 °玄電性接 於各該電性接觸塾上，且形成該表面處係設 自由化學鍍鎳/金、化鎳浸金（ENIq) '材抖尨可選 (ENEPIG)、仆與辦.下.、 化錄鈀浸金 所組成之群組;^機州_ 本务明彳是揭露一種封裝基板之製法， 了'包括：提供一 1Π278 6 201104813 基板本體；於該基板本體上形成 成阻芦，g ,;该導電層上形 攻阻盾且5玄阻層具有複數開口區以 層；蝕刻移除該開口區中之導泰 。刀之ν電 該導電声上mm 移除該阻層；以及於 〜層上包鍍形成金屬層，以於該基 層，且該線路層具有複數電性接觸墊。 形成、、泉路 前述之製法中，該基板本體係可為多層板、兩層μA through hole 300a is formed in the plate 30, and a conductive layer 31 is formed on the hole wall of the core 30] and the through hole 300a, and a resist layer 33 which is a dry film is formed on the conductive layer .31. And the resist layer 33 forms a plurality of open regions 330, and exposes a portion of the surface of the conductive layer 31; as shown in FIG. 3B, a metal layer 32 is plated on the conductive layer 31 in each of the open regions 330; as shown in FIG. 3C As shown, the resist layer 33 is removed to expose the surface of the conductive layer 31 that is not covered by the metal 32; as shown in FIG. 3D, the exposed conductive layer 31 and portions of the metal layer 32 are removed. A circuit layer 34 is formed on the core board 30, and a conductive via 300 electrically connected to the line layer 34 is formed in the through hole 300a. However, in the conventional pattern transfer and semi-additive method, the resist layers 23, 33 serve as a plating resist layer for plating metal on the conductive layers 21, 31 in the open regions 230, 330; when the resist layer 23 is removed At 33 o'clock, the dry film of the resist layers 23, 33 tends to remain between the circuit layers 24, 34, so-called sandwich phenomenon, so that the conductive layer covered by the resist layers 23, 33 is removed by etching. At 21,31, it is impossible to completely remove the clean material, such as the dry film material shown in Figures 2D and 3D and the conductive material S covered by φ. The circuit layer 24, 34 electrically turns on the remaining conductive material S to cause a short circuit. The aforementioned film phenomenon is more obvious in the fine pitch line process, which means that the spacing between the lines is narrower, so that the resist layers 23, 33 between the lines and the conductive layers 21, 31 covered by the lines are more difficult. The removal is clean, and the circuit layers 24, 34 are more susceptible to short-circuiting due to the remaining conductive material S, thus limiting the development of the fine pitch line process. Therefore, in view of the above problems, how to avoid the problems caused by undercutting and filming in the prior art has become a problem that is currently being solved. 111278 201104813 SUMMARY OF THE INVENTION In view of the above-mentioned various deficiencies of the prior art, a cover substrate which avoids undercutting and a method of manufacturing the same are provided. Another object of the present invention is a method and method of making the same. The package base for the fine pitch line is for the above and other purposes, and the present invention includes: the substrate of the present invention has a through-substrate 'substrate' in the through hole, and is made of a conductive layer and a through hole. The system is disposed on the substrate body, and is composed of: a Lei Di layer; and the line is electrically connected to the fla layer by a copper layer, a conductive layer and a plated metal. Conductively coated with the copper layer S f into 'where the line is completely covered with the surface of the Lei Si*, and the metal layer of the electric clock is 已 已 3 has a plurality of layers on the upper surface of the conductive layer and the copper layer Sexual contact pads. The surface, and the circuit layer, in the package substrate described above, the substrate of the substrate or the circuit board having internal wiring, and the layer, the two layers of turns, the flip chip or the bulb. The contact 塾 system may include a solder resist layer and a circuit layer, and the solder resist layer has a plurality of openings therein, and the two limbs are exposed to the opening; Ground, 7 ° can be electrically connected to each of the electrical contact rafts, and the surface is formed with free electroless nickel/gold, nickel immersion gold (ENIq) 'material shake optional (ENEPIG) , servant and office. Under., group recorded by palladium immersion gold; ^ machine state _ this is a method of exposing a package substrate, 'includes: provide a 1 Π 278 6 201104813 substrate body; on the substrate Forming a resisting reed on the body, g; the conductive layer has a top-impact shield and the 5 meta-resistive layer has a plurality of open areas as a layer; etching removes the guide in the open area. The electric resistance of the knife is removed from the conductive layer by mm; and a metal layer is formed on the layer to form the metal layer for the base layer, and the circuit layer has a plurality of electrical contact pads. Forming, spring road In the above-mentioned manufacturing method, the substrate can be a multi-layer board, two layers of μ
-有内部線路之線路板’且該電性接觸祕可為打線塾、 覆晶焊墊或植球墊。 前述之製法中，該基板本體之表面復可具有㈣，且 具有複數貫穿縣板本體之魏，又科電層係形成於該 鋼辖及通孔之孔壁上；該製法復可包括蝴㈣該開口區 中之導電層及其覆蓋之鋼羯，以令保留之銅具有上表面 與侧表面及該保留之銅结上覆有導電層，該保留之銅箱係 為銅層，且該電鍍金屬層可完整包覆該導電層之上表面與 鋼層之側表面，並於該通孔中形成導電通孔。 前述之製法復可包括於該基板本體及線路層上形成 防焊層，該防焊層可為具有防焊效果之樹脂層或介電層， 以供保護其下之線路層，且該防焊層中形成複數開孔，以 令該電性接觸墊露出於該開孔；較佳地，復可包括於各該 %性接觸墊上形成表面處理層，且形成該表面處理層之材 科係可選自由化學鍍鎳/金、化鎳浸金（ENIG)、化鎳鈀 《金（ENEPIG)、化學鍍錫（immersi〇n Tin)及有機保 埤劑（OSP)所組成之群組中之其中一者。 由上可知，本發明藉由該阻層覆蓋於線路雛形（即保 1Π278 7 201104813 留的銅结及覆於其上之導電層）上，以作為姓刻阻層，相 較於習知圖案轉移及半加成製法的阻層係作為電鑛阻層， 本發明之㈣阻層易於移除，不會殘留該阻層之乾膜材於 該基板本體表面，不會發生_轉移及半加錢法的電鑛 阻層及其所覆蓋的導電層殘存於線路層之間，即夾膜現象 之發生；本發明之阻層僅覆於線路雛形上而易於移除，且 該線路層之間不易殘留導電層，可避免線路層之間發生短 路，更可提高細間距線路技術之發展。 再者，本發明係先形成線路雛形，再令該電鍍金屬層 完整包覆於該線路卿上，以製成線路層；相較於習㈣ 刻衣法’本發明之線路成型最後步驟係為電鍍而非蝕刻， 可達到避免發生底切現象之目的。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 二解j此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 ”月麥閱第4A至41圖，係為本發明所揭露之 基板之製法。 裡封裝 如第4A圖所不，提供一基板本體,該基板本體 兩層板或具有㈣輯之線路板，且該基板 之表面具有銅落4〇a;然，於其他實施例中， 板本版40之表面亦可不具有銅落偷，又 : 贊述。 業界所周知，且其非本案技術特徵，故不再- a circuit board having an internal circuit and the electrical contact may be a wire bond, a flip chip or a ball pad. In the above method, the surface of the substrate body may have (4), and has a plurality of Weis running through the body of the county plate, and the electrical layer is formed on the wall of the steel and the through hole; the method may include a butterfly (4) a conductive layer in the open area and the steel rim thereof covered so that the retained copper has an upper surface and a side surface, and the remaining copper joint is covered with a conductive layer, the reserved copper box is a copper layer, and the plating The metal layer can completely cover the upper surface of the conductive layer and the side surface of the steel layer, and form a conductive via in the through hole. The foregoing method may include forming a solder resist layer on the substrate body and the circuit layer, and the solder resist layer may be a resin layer or a dielectric layer having a solder resist effect for protecting the underlying circuit layer, and the solder resist Forming a plurality of openings in the layer to expose the electrical contact pads to the openings; preferably, forming a surface treatment layer on each of the % contact pads, and forming a surface treatment layer Selected from the group consisting of electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium gold (ENEPIG), electroless tin plating (immersi〇n Tin) and organic pesticide (OSP). One. As can be seen from the above, the present invention is covered by the resist layer (ie, the copper layer remaining on 1 278 7 201104813 and the conductive layer overlying it) as a surname resist layer, which is transferred from the conventional pattern. And the resistive layer of the semi-additive method is used as the electro-mineral resist layer, and the (4) resist layer of the invention is easy to remove, and the dry film material of the resist layer is not left on the surface of the substrate body, and no transfer or half-addition occurs. The electro-mineral resist layer of the method and the conductive layer covered by the method remain between the circuit layers, that is, the phenomenon of the interlayer film is formed; the resist layer of the present invention covers only the line prototype and is easy to remove, and the line layer is not easy to be removed. Residual conductive layer can avoid short circuit between circuit layers, and can improve the development of fine pitch circuit technology. Furthermore, the present invention first forms a circuit prototype, and then the electroplated metal layer is completely coated on the circuit to form a circuit layer; compared with the Xi (4) engraving method, the final step of the line forming process of the present invention is Electroplating, rather than etching, can achieve the purpose of avoiding undercutting. [Embodiment] The following is a description of the embodiments of the present invention by way of specific specific embodiments. Those skilled in the art can readily understand other advantages and functions of the present invention from the disclosure of the present disclosure. 4A to 41 are the method of manufacturing the substrate disclosed in the present invention. The package is provided as shown in FIG. 4A, and provides a substrate body, the substrate body has two layers or a circuit board having (4) series, and The surface of the substrate has a copper drop 4;a; however, in other embodiments, the surface of the plate 40 may not have a copper smear, and it is also said: As is well known in the industry, and it is not a technical feature of the present invention, it is not again
S 111278 201104813 如第牝戶斤示，於該基板本體4〇中形成複數貫穿之通 孔 400a。 如第4C圖所示，再於該銅箔40a及該些通孔40(^之 孔壁上形成導電層41。 如第4D圖所示，於該導電層41上形成係為乾膜之阻 層43，且該阻層43具有複數開口區43〇以外露出部分之 導電層41。本發明之阻層43係作為餘刻阻層，以名虫刻該 開口區430中之導電材料，而保留該阻層43下之導電材料。 如第4E圖所示’蝕刻移除該開口區43〇中之導電層 41及其覆盖之銅箱40a ’以令保留之銅箔4〇a具有上表面 與側表面41b及該保留鋼箔4〇a上覆有導電層41，該導電 層41具有上表面4la;其中，保留之銅箔4〇a係定義為銅 層 41，。 如第4F圖所示，移除該阻層43，以露出該銅層41， 上之導電層41。 如第4G圖所不，於該導電層41上電鍍形成金屬層 42，以於該基板本體4〇上形成線路層44，且該基板本體 4〇之通孔400a形成導電通孔4〇〇 ;其中，該線路層44之 電鑛金屬層42係完整包覆該導電層41之上表面4U與銅 層41之側表面41b ’且該線路層44具有複數電性接觸 墊，忒電性接觸墊係為打線墊44〇a '覆晶焊墊（未以圖式 表示）或植球塾440b。 如第4H圖所示’於該基板本體40上形成防焊層47， 且5玄防焊層47中形成複數開孔470,以令各該打線墊440a 9 111278 201104813 及植球墊440b露出於該開孔470。 另外，於各該打線墊440a及植球墊440b之外露表面 上可形成表面處理層48，且形成該表面處理層48之材料 係選自由化學鑛鎳/金、化鎳浸金（ENIG )、化錄把浸金 (ENEPIG )、化學鍍錫（Immersion Tin )及有機保焊劑（OSP) 所組成之群組中之其中一者。 本發明藉由先完成圖案化線路雛形（即保留的銅箔 40a及覆於其上之導電層41 )，使該阻層43覆蓋於該線路 雛形之導電層41上，如第4E圖所示；相較於習知圖案轉 移及半加成製法之電鍍阻層，本發明之阻層43係作為蝕刻 阻層，僅覆於線路雛形上而易於移除，且該線路層44之間 不易殘留導電層41，可避免該線路層44之間發生短路。 再者，因不會發生夾膜現象，故不會影響細間距線路 製程之發展，意即不論線路之間的間距多小，該線路層44 之間均不易殘存導電層41之材料，而避免線路層44之間 發生短路。 又本發明係先形成該線路層44之圖案化線路雛形， 且該圖案化線路雛形係由該銅層4Γ及其上之導電層41所 構成（如第4F圖所示），再令該電鐘金屬層42完整包覆 於該圖案化雛形上，俾以製成該線路層44 ;相較於習知蝕 刻製法，本發明之線路成型最後步驟係為電鍍金屬，而未 使用蝕刻法，因而有效避免該線路層44發生底切的現象。 本發明復提供一種封裝基板，係包括基板本體40、導 電通孔400以及線路層44。 201104813 所述之基板本體40係為多層板或兩層板，並具 穿之通孔4〇〇a。 、’ _ 所述之導電通孔400係設於該通孔4〇〇a中，並由導 電層41及電鍍金屬層42所構成。 所述之線路層44係設於該基板本體4〇上，並電性連 接至該導電通孔400，且該線路層44係由鋼層41,甩導電 層41及電鍍金屬層42所構成，其中該線路層44之導電層 41係覆於該銅層41，之上表面，而該電鍍金屬層仏並^^ 包覆該導電層41之上表面41a與銅層41,之側表面仙； 又該線路層44具有複數電性接觸墊，且該些電性接觸塾係 為打線墊440a、覆晶焊墊或植球墊44〇b。 所述之封裝基板復包括防焊層47，係設於該基板本體 40及線路層44上，且該防焊層47中具有複數開孔销， 以令各該電性接觸墊露出於各該開孔47()。另外， 括表面處理層48,係設於外露於該開孔梢之電性接觸^ 上，且形成該表面處理g 48之材料係選自由化 金、化錄浸金（腿G)、麵m(ENEpiG)、’二S 111278 201104813 As shown in the following figure, a plurality of through holes 400a are formed in the substrate body 4A. As shown in FIG. 4C, a conductive layer 41 is formed on the copper foil 40a and the via holes 40. As shown in FIG. 4D, a resist is formed on the conductive layer 41 as a dry film. The layer 43 has a conductive layer 41 exposed outside the plurality of open regions 43. The resist layer 43 of the present invention acts as a resist layer to insulate the conductive material in the open region 430 while retaining The conductive material under the resist layer 43. As shown in FIG. 4E, the conductive layer 41 in the open region 43A and the copper case 40a covered therein are removed by etching to make the remaining copper foil 4〇a have an upper surface and The side surface 41b and the retained steel foil 4〇a are covered with a conductive layer 41 having an upper surface 41a; wherein the remaining copper foil 4〇a is defined as a copper layer 41. As shown in FIG. 4F The resist layer 43 is removed to expose the conductive layer 41 on the copper layer 41. As shown in FIG. 4G, a metal layer 42 is formed on the conductive layer 41 to form a line on the substrate body 4 a layer 44, and the via hole 400a of the substrate body 4 defines a conductive via 4; wherein the electrodeposited metal layer 42 of the circuit layer 44 completely encapsulates the conductive layer 4 1 upper surface 4U and side surface 41b' of copper layer 41 and the circuit layer 44 has a plurality of electrical contact pads, and the electrical contact pads are wire bonding pads 44〇a 'cladding pads (not shown) Or the ball 塾 440b. As shown in FIG. 4H, a solder resist layer 47 is formed on the substrate body 40, and a plurality of openings 470 are formed in the 5 mymetic solder layer 47, so that the wire pads 440a 9 111278 201104813 and The ball processing pad 440b is exposed to the opening 470. Further, a surface treatment layer 48 may be formed on the exposed surface of each of the wire bonding pad 440a and the ball bonding pad 440b, and the material forming the surface treatment layer 48 is selected from the group consisting of chemical mineral nickel. / Gold, nickel immersion gold (ENIG), one of the group consisting of immersion gold (ENEPIG), electroless tin plating (Immersion Tin) and organic solder resist (OSP). Finishing the patterned circuit prototype (ie, the remaining copper foil 40a and the conductive layer 41 overlying it), so that the resist layer 43 covers the conductive layer 41 of the line prototype, as shown in FIG. 4E; Knowing the plating resist layer of the pattern transfer and semi-additive method, the resist layer 43 of the present invention serves as an etching resist layer and is only covered by The road shape is easy to remove, and the conductive layer 41 is not easily left between the circuit layers 44, so that short circuit between the circuit layers 44 can be avoided. Moreover, since the film phenomenon does not occur, the fine pitch line is not affected. The development of the process means that no matter how small the spacing between the lines is, the material of the conductive layer 41 is not easily left between the circuit layers 44, and the short circuit between the circuit layers 44 is avoided. The present invention first forms the circuit layer 44. The patterned circuit is formed by the copper layer 4 and the conductive layer 41 thereon (as shown in FIG. 4F), and the metal layer 42 is completely covered by the pattern. The circuit layer 44 is formed by forming a circuit layer 44. Compared with the conventional etching method, the final step of the wire forming process of the present invention is a plating metal without using an etching method, thereby effectively avoiding the undercut of the circuit layer 44. phenomenon. The present invention further provides a package substrate comprising a substrate body 40, a via hole 400, and a wiring layer 44. The substrate body 40 described in 201104813 is a multi-layer board or a two-layer board, and has a through hole 4〇〇a. The conductive via 400 described in the above is disposed in the via hole 4〇〇a and is composed of the conductive layer 41 and the plated metal layer 42. The circuit layer 44 is disposed on the substrate body 4 and electrically connected to the conductive via 400, and the circuit layer 44 is composed of a steel layer 41, a germanium conductive layer 41 and a plated metal layer 42. The conductive layer 41 of the circuit layer 44 is applied to the upper surface of the copper layer 41, and the plating metal layer is coated and coated with the upper surface 41a and the copper layer 41 of the conductive layer 41. The circuit layer 44 has a plurality of electrical contact pads, and the electrical contact contacts are a wire pad 440a, a flip chip or a ball pad 44〇b. The package substrate further includes a solder resist layer 47 disposed on the substrate body 40 and the circuit layer 44, and the solder resist layer 47 has a plurality of open-hole pins, so that the electrical contact pads are exposed to each of the pads. Opening 47 (). In addition, the surface treatment layer 48 is disposed on the electrical contact exposed to the opening, and the material forming the surface treatment g 48 is selected from the group consisting of gold, chemical immersion gold (leg G), surface m (ENEpiG), 'two
鍵錫（ΙΐΏ__ Tm)及有機保焊劑（QSP)所組成之群: 中之其中一者。 I 练上所述’本發明之ρ且層僅覆於線路雛形上而易 除’且該線路層之間不易殘留導電層，可避免線路層之) 發生短路。 θ 再者，本發明因不會發生失膜現象，故不論線路之門 的間距多+，該線路之間均不易殘存導電層之材料，因而 Π1278 201104813 有效提高細間距線路技術之發展。 又本赍明係先形成該線路層之圖案化雛形，再令該電 鑛金屬層完整包覆於關純_彡上，以製成線路層。，因 本發明之線路成型最後步驟料電錢金屬而賴刻法，故 有效達到避免發生底切現象之目的。 上述實施例係用以例示性說明本發明之原理及其功 效’ 1非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下’對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1A至1D圖係為習知封裝基板之濕蝕刻製法示音 圖； ~ 第2A至2D圖係為習知封裝基板之圖案轉移製法示 意圖； 第3A至3D圖係為習知封裝基板之半加成製法示专 圖；以及 〜 【主要元件符號說明】 10,20,30 核心板 10a,20a,40a 銅箔 100a，200a，300a，400a 通孔 100,200,300,400 導電通孔 11,21,31,41 導電層 第4A至4H圖係為本發明封裝基板之製法示意圖。 1Π278 12 201104813One of the group consisting of bond tin (ΙΐΏ__ Tm) and organic solder resist (QSP). I practice the above-mentioned "p of the present invention and the layer is only overlaid on the line prototype and is easy to remove" and the conductive layer is not easily left between the circuit layers to avoid short circuit of the circuit layer. θ Furthermore, in the present invention, since the film loss phenomenon does not occur, the material of the conductive layer is less likely to remain between the lines regardless of the pitch of the gate of the line. Therefore, Π1278 201104813 effectively improves the development of fine pitch line technology. In addition, Benming Ming first formed the patterned prototype of the circuit layer, and then the metal layer of the electric ore was completely coated on the Guan _ , to form a circuit layer. Because the final step of the wire forming process of the invention is based on the electric money metal, the method of avoiding undercutting is effectively achieved. The above-described embodiments are intended to exemplify the principles of the present invention and the functions thereof are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are diagrams showing a wet etching method of a conventional package substrate; ~ 2A to 2D are schematic diagrams of a pattern transfer method of a conventional package substrate; FIGS. 3A to 3D are A half-addition method for a conventional package substrate; and ~ [Major component symbol description] 10, 20, 30 core plates 10a, 20a, 40a copper foil 100a, 200a, 300a, 400a through holes 100, 200, 300, 400 conductive vias 11, 21, 31, 41 Conductive Layers 4A to 4H are schematic views of the method of manufacturing the package substrate of the present invention. 1Π278 12 201104813
12,22,32 金屬層 13,23,33,43 阻層 130,230,330,430 開口區 14,24,34,44 線路層 40 基板本體 41， 銅層 41a 上表面 41b 側表面 42 電鑛金屬層 440a 打線墊 440b 植球墊 47 防焊層 470 開孔 48 表面處理層 C 底切現象 s 導電材12,22,32 metal layer 13,23,33,43 resist layer 130,230,330,430 open area 14,24,34,44 circuit layer 40 substrate body 41, copper layer 41a upper surface 41b side surface 42 electro-mineral metal layer 440a wire pad 440b Ball pad 47 solder mask 470 opening 48 surface treatment layer C undercut phenomenon s conductive material