201039417 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種導電凸塊結構及顯示面板之晶片接合結構， 尤指-種包括具有缺口設計之絕緣緩衝結構的導“塊結二顯示 面板之晶片接合結構。 【先前技術】 COG(chip on g㈣技術係指將晶片直接與玻璃基板上之連接塾 接合的技術’而由於術具有低成本的優勢，因此目前已廣 泛地應用在顯示面板的晶片接合製作上。根據現行c〇G技術，: 片上設置有金導電凸塊結構，且晶片與顯示面板係藉由異方性導曰^201039417 VI. Description of the Invention: [Technical Field] The present invention relates to a conductive bump structure and a wafer bonding structure of a display panel, and more particularly to a conductive "blocking two display panel including an insulating buffer structure having a notch design" Wafer bonding structure. [Prior Art] COG (chip on g (four) technology refers to the technology of bonding a wafer directly to a connection port on a glass substrate] and has been widely used in display panels due to its low cost advantage. Wafer bonding fabrication. According to the current c〇G technology, a gold conductive bump structure is provided on the chip, and the wafer and the display panel are guided by an anisotropy.
膠_純接合’錢金_猶構與齡破之連接塾 以達到電性連接的效果。 人異方料電料獅成本偏高，造成晶片的接 合的製作縣無_-步_。耻，⑺㈣術 究發展，以節作成本。 [發明内容】 3 201039417 本發明之目的之-在於提供一種導電凸塊結構及顯示面板之晶 片接合結構，以解決習知C0G技術所面臨之問題。 • 為達上述目的，本發明提供—種導電凸塊結構，設置於_上， -導電凸塊結構包純數懈墊、絕緣緩衝結構與複數辦電薄膜。 焊塾係設置於基底上；_緩衝結構橫轉錢部分碰各焊塾； 導電薄膜係設置於絕緣緩衝結構上並分顺各·紐連接。絕緣 〇緩衝結構具有複數個缺口，至少位於部分兩相鄰之導電薄膜之間， 形成排膠通道。 為達上述目的，本發明另提供一種顯示面板之晶片接合結構， 包括基板、複數個連触、晶片與非導電性賴。基板包括焊接區， 連接塾係設置於焊接區内。晶片包括至少一導電凸塊結構，且導電 凸塊結構包括複數個焊塾、絕緣緩衝結構與複數個導電薄膜。焊塾 係設置於；上；_緩衝結顯跨焊錢部分覆蓋各焊塾；導電 薄臈係設置於絕緣緩衝結構上並分別與各焊墊電性連接。非導電性 膠體係設置於基板與晶片之間，並將晶片黏著於基板上。絕緣緩衝 結構具有複數個缺口，至少位於部分之兩相鄰之導電薄膜之間，形 、成非導電性膠體之排膠通道。 y 八树明之導電凸塊結構具有絕緣緩衝結構，有助於緩衝晶片壓 σ製私所產生的壓著應力。此外，絕緣緩衝結構具有缺口設計，可 增加非導電性膠體之排膠通道，故可提升晶片壓合製程^率與晶 4 201039417 片接合結構的可靠度。 【實施方式】 • 為使麵"本發明所屬細躺之-般祕者缺進—步了解本 下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳 、’田°兒月本發明的構成内容及所欲達成之功效。 〇 ^ 卜 =參考第1圖至第3圖。第1圖至第3圖為本發明—較佳實施 例之2¾凸塊結構之示意圖’其中第1圖繪示了導電凸塊結構之外 觀不思圖、第2圖綠示了導電凸塊結構之上視圖，第3圖緣示了導 電凸塊結構沿第2圖之剖線从，之剖面示意圖。如第丨圖至第3圖 所不，本實施例之導電凸塊結構10係設置於基底I2上，且導電凸 塊、、°構12包括複數個焊墊14、絕緣緩衝結構16，以及複數個導電 薄膜18綷墊μ係設置於基底12，且在本實施例中，基底Η可為 片而太干墊14則可與晶片之内部連線(圖未示)電性連接。絕緣 緩衝結構16係設置於基底12上並橫跨焊整14，其中本實施例之絕 緣緩衝結構16具有條狀結構，但不以此為⑯，且絕緣緩衝結構部分 ·=蓋各坏墊14 ’並曝露出部分之各焊墊丨4。在本實施例中，絕緣緩 衝…構16係由有彈性之絕緣材質所構成，例如高分子材質，且較佳 係使用感光性材質，例如感光性聚醯亞胺(p〇lyimide，pi)，藉此可藉 由曝光暨顯影製程加以製作並定義出其圖案，但並不以此為限。導 電薄膜18係設置於絕緣緩衝結構16上並分別與對應之各焊墊14 5 201039417 祕連接。在本實施财，導f _ 18的材質可 亚與絕緣緩賊構16具有良好接著效果之材料，例以電性佳 為限。導電薄膜18的作用在於將焊墊14 金’但不以此 構16之表面，以作進—步的對外連接。 接至絕緣緩衝結 本發明之導電凸塊結構10主要句 與導電薄膜Μ。絕緣緩衝結構16係作為導^緣緩衝結構16 ,, 节外兩¥電凸塊結構10的Φ盈萁 ❹Glue_pure joints' money gold _ jujube and age-breaking connection 塾 to achieve the effect of electrical connection. The cost of the human material lion is too high, causing the production of the wafer to be produced in the county without _step _. Shame, (7) (4) The development of the study, with the cost of the festival. SUMMARY OF THE INVENTION 3 201039417 The object of the present invention is to provide a conductive bump structure and a wafer bonding structure of a display panel to solve the problems faced by the conventional COG technology. In order to achieve the above object, the present invention provides a conductive bump structure, which is disposed on the _, and the conductive bump structure comprises a pure pad, an insulating buffer structure and a plurality of dielectric films. The soldering system is disposed on the substrate; the buffer structure crosses the money portion and touches each of the solder bumps; the conductive film is disposed on the insulating buffer structure and is branched and connected. The insulating buffer structure has a plurality of notches at least between a portion of two adjacent conductive films to form a discharge passage. To achieve the above object, the present invention further provides a wafer bonding structure for a display panel, comprising a substrate, a plurality of contacts, a wafer, and a non-conductive layer. The substrate includes a soldering region, and the connecting lanthanum is disposed in the soldering region. The wafer includes at least one conductive bump structure, and the conductive bump structure includes a plurality of solder bumps, an insulating buffer structure, and a plurality of conductive films. The soldering system is disposed on the upper portion; the buffering portion is covered with the soldering portion to cover the respective soldering rafts; the conductive thin lanthanum is disposed on the insulating buffer structure and electrically connected to the respective pads. A non-conductive glue system is disposed between the substrate and the wafer and adheres the wafer to the substrate. The insulating buffer structure has a plurality of notches, at least between a portion of the two adjacent conductive films, forming a discharge passage for the non-conductive colloid. y Yashuming's conductive bump structure has an insulating buffer structure, which helps to buffer the compressive stress generated by the wafer pressure. In addition, the insulating buffer structure has a notch design, which can increase the discharge passage of the non-conductive colloid, thereby improving the reliability of the wafer bonding process and the bonding structure of the crystal wafer 201039417. [Embodiment] • In order to make the face "the present invention belongs to the squat-like secrets, the following is a detailed description of several preferred embodiments of the present invention, and in conjunction with the drawings, ° 儿月 The composition of the invention and the desired effect. 〇 ^ Bu = Refer to Figures 1 to 3. 1 to 3 are schematic views of a 23⁄4 bump structure of the preferred embodiment of the present invention. FIG. 1 is a view showing the appearance of the conductive bump structure, and FIG. 2 is a green conductive bump structure. In the top view, the third figure shows a schematic cross-sectional view of the conductive bump structure taken along the line of Fig. 2. As shown in the third to third embodiments, the conductive bump structure 10 of the present embodiment is disposed on the substrate I2, and the conductive bumps, the structure 12 includes a plurality of pads 14, the insulating buffer structure 16, and a plurality of The conductive film 18 is provided on the substrate 12, and in this embodiment, the substrate can be a sheet and the dry pad 14 can be electrically connected to an internal connection (not shown) of the wafer. The insulating buffer structure 16 is disposed on the substrate 12 and spans the soldering 14 . The insulating buffer structure 16 of the embodiment has a strip structure, but is not 16 , and the insulating buffer structure portion includes a cover pad 14 . 'And expose some of the pads 丨4. In the present embodiment, the insulating buffer 16 is composed of a resilient insulating material, such as a polymer material, and preferably a photosensitive material such as a photosensitive polyimine (pi), Thereby, the pattern can be produced and defined by the exposure and development process, but not limited thereto. The conductive film 18 is disposed on the insulating buffer structure 16 and is respectively connected to the corresponding pads 14 5 201039417. In this implementation, the material of the material f _ 18 can be used as a material with a good adhesion effect, for example, the electrical property is good. The function of the conductive film 18 is to make the pad 14 gold 'but not the surface of the structure 16 for the external connection of the step. Connected to the insulating buffer junction The conductive bump structure 10 of the present invention is mainly associated with a conductive film. The insulating buffer structure 16 is used as the guiding edge buffer structure 16, and the Φ surplus of the two outer electric bump structures 10
G 材之用’其具有成本低與易於圖案化的優點而可減少導 = 用，此外絕緣緩衝結構16亦具有緩衝晶片壓合製程時所產生的摩力 的效果。另外，導電薄膜18的作用為將焊㈣的;；== 緩衝結構16的表面，以利用後續的對外連接。 、’ 本發日狀_塊結構1G_緣緩衝結構％具有複數個缺口 〇 ’至少位於部分之兩相鄰之導電薄膜18之間。缺口加係作為後 、^曰曰片壓合製程時非導電性膠體的排膠通道，使多餘之非導電性膠 體得以順利排出。在本實施财’各缺σ 2Q_成於任兩相鄰之導 電溥膜18之間的絕緣緩衝結構16、缺口 2〇的深度小於絕緣緩衝結 構16之高度，例如缺口 2〇的深度係為絕緣緩衝結構16之高度的一 半，且缺口 20具有弧形截面，但缺口 2〇的位置、深度、尺寸、形 狀與數目等並不以此為限’而可視娜效果作適度變更。 明再參考第4圖與第5圖。第4圖與第5圖為本發明另兩較佳 實施例之導電凸塊結構之剖面示意圖，其中為簡化說明並比較各實 6 201039417 施例之間的異同，第4 _第5圖之實 之元件符號標注相同之元#+ _使用相同 明。如第4 B所几件並僅針對各實施例之相異處進行說 U 4圖所則⑽緩衝結構16之細2()並不限於圓弧截面， 而可視娜效果域何職面，例如四邊職喊其它幾何形載 面。如弟5圖所示，相鄰之導電薄膜18之間的缺口 2〇的數目並不 限於-個’ *可視郷效果加以變更或組合設計。 ❹ /參考第6圖與第7圖，並—併參考第1圖至第3圖。第6圖 搶:了本發明一較佳實施例之顯示面板之晶片接合結構於接合前之 示意圖’第7圖綠示了本發明一較佳實施例之顯示面板之晶片接合 結構於接合後之示意圖。如第6圖所示，本實施例之顯示面板之晶 片接合結構30包括基板32、複數個連接墊34、至少一晶片4〇，以 及非導電性膠體50。基板％係為顯示面板之基板、例如薄膜電晶 體基板’且其包括一焊接區36’而連接墊34係設置於焊接區36内， 用以將顯示面板之導線例如資料線或閘極線(圖未示)之電性連接至 ❹焊接區36以便於對外連接。另外，焊接區36係位於顯示面板之非 金屬端子區。晶片40包括至少一導電凸塊結構1〇，其中導電凸塊 結構10包括複數個焊墊14(如第1圖與第2圖所示)、絕緣緩衝結構 • 16，以及複數個導電薄膜18。焊墊Η可與晶片40之内部連線(圖 未示)電性連接。絕緣緩衝結構16橫跨焊墊14且部分覆蓋各焊墊 14而曝露出部分之各焊墊14。導電薄膜18設置於絕緣緩衝結構16 上並分別與對應之各焊墊14電性連接。非導電性膠體5〇設置於基 板32與晶片40之間，並將晶片40黏著於基板32上。 7 201039417 Ο 本實施例之顯示面板之晶片接合結構3〇的導電 為前述任-實施綱揭露之導電凸塊結構1Q或其變化^樣離7 評細說明如上文所述，在此不再重覆贅述。導電凸塊結仙之= 缓衝結構具有複數個缺口 20，且缺口 2〇至少位於部分之、^ 之導電薄膜18之間，藉此形成非導電性_5()之排膠通道兩= 絕緣緩衝結構I6之缺π 2〇 ’在晶;^ 4〇與顯軸板之基板曰〜 晶片麼合製程時，非導電性膠體5G除了可經由相鄰之絕緣緩衝= 16之間的空_出之外，亦可_各絕緣緩衝結構16的缺口 出而不會產生非導電性膠體5〇無法順利排膠的問題，因此晶片 40與顯示面板之基板32可順利接合，如第7圖所示。 "τ'上所述’本發明之顯不面板之晶丨接合結構所使用之導電凸 塊結構具有絕緣緩衝結構，有助於緩衝晶片壓合製程所產生的壓著 應力。另外，絕緣緩衝、结構具有缺口設計，可增加非導電性膠體之 郷通道’故可提升晶丨壓合製㈣&頓晶牌合結構的可靠 度。另外’絕緣緩衝結構可選用感光性材料，因此缺口的形成可藉 由曝光暨顯影技術輕易達成而不需增加額外成本。 " 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均㈣化與修飾’皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 8 201039417 第1圖至第3目林㈣—較佳實關之 第4圖盘第$阁氐士政 电0塊結構之不意圖。 二為本發8一實施例之導電凸塊結構之二 Ο 合W片接合結構於接 第：:=—較佳實施例之顯示面板之晶片― 【主要元件符號說明】 導電凸塊結構 12 基底 焊墊 16 絕緣緩衝結構 導電薄臈 20 缺α 顯示面板之晶片接合結構 32 基板 連接墊 36 焊接區 晶片 50 非導電性膠體 10 14 18 30 Ο 34 40The use of the G material has the advantages of low cost and easy patterning, and can reduce the conduction. Moreover, the insulating buffer structure 16 also has the effect of buffering the friction generated during the wafer pressing process. In addition, the conductive film 18 functions to weld (four);; = the surface of the buffer structure 16 to utilize subsequent external connections. The present invention has a plurality of notches 〇 ' at least between the two adjacent conductive films 18 of the portion. The gap is added as a discharge passage for the non-conductive colloid during the post-pressing process, so that the excess non-conductive colloid can be smoothly discharged. In the present embodiment, the thickness of the insulating buffer structure 16 and the notch 2〇 between the two adjacent conductive films 18 is smaller than the height of the insulating buffer structure 16, for example, the depth of the notch 2〇 is The height of the insulating buffer structure 16 is half, and the notch 20 has an arc-shaped cross section, but the position, depth, size, shape and number of the notch 2〇 are not limited thereto, and the visible effect is moderately changed. Refer to Figures 4 and 5 again. 4 and 5 are schematic cross-sectional views showing the structure of the conductive bumps according to another preferred embodiment of the present invention, wherein the simplified and the similarities and differences between the embodiments of the real 6 201039417 are shown in Fig. 4 and Fig. 5 The component symbol is labeled with the same element #+ _ using the same clear. As for the parts of the 4th B and only for the differences of the respective embodiments, the U 4 figure is used. (10) The thinness 2() of the buffer structure 16 is not limited to the circular cross section, and the visual effect field, for example, The four sides shouted other geometric shapes. As shown in Fig. 5, the number of notches 2〇 between adjacent conductive films 18 is not limited to a single one. ❹ / Refer to Figures 6 and 7, and - and refer to Figures 1 to 3. FIG. 6 is a schematic view of a wafer bonding structure of a display panel according to a preferred embodiment of the present invention. FIG. 7 is a view showing a wafer bonding structure of a display panel according to a preferred embodiment of the present invention after bonding. schematic diagram. As shown in Fig. 6, the wafer bonding structure 30 of the display panel of the present embodiment includes a substrate 32, a plurality of connection pads 34, at least one wafer 4, and a non-conductive paste 50. The substrate % is a substrate of the display panel, such as a thin film transistor substrate 'and includes a solder pad 36 ′ and the connection pad 34 is disposed in the solder pad 36 for connecting the wires of the display panel such as a data line or a gate line ( The figure is not shown) electrically connected to the tantalum weld zone 36 for external connection. Additionally, the land 36 is located in the non-metallic terminal region of the display panel. The wafer 40 includes at least one conductive bump structure 1 , wherein the conductive bump structure 10 includes a plurality of pads 14 (as shown in FIGS. 1 and 2), an insulating buffer structure 16 , and a plurality of conductive films 18 . The pad Η can be electrically connected to an internal connection (not shown) of the wafer 40. The insulating buffer structure 16 spans the pads 14 and partially covers the pads 14 to expose portions of the pads 14. The conductive film 18 is disposed on the insulating buffer structure 16 and electrically connected to the corresponding pads 14 respectively. The non-conductive colloid 5 is disposed between the substrate 32 and the wafer 40, and the wafer 40 is adhered to the substrate 32. 7 201039417 导电 The conductive structure of the wafer bonding structure 3 of the display panel of the present embodiment is the conductive bump structure 1Q disclosed in any of the above-mentioned embodiments, or the variation thereof is as described above, and is not described here. Overwrite the statement. The conductive bumps have a plurality of notches 20, and the notches 2〇 are located at least between the portions of the conductive film 18, thereby forming a non-conductive _5 () discharge channel two = insulation When the buffer structure I6 lacks π 2〇' in the crystal; ^ 4〇 and the substrate of the display plate 曰 ~ wafer, the non-conductive colloid 5G can pass through the adjacent insulation buffer = 16 between the empty_out In addition, the gaps of the insulating buffer structures 16 can be eliminated without causing the problem that the non-conductive colloids 5 cannot be smoothly discharged. Therefore, the wafer 40 and the substrate 32 of the display panel can be smoothly joined, as shown in FIG. . The conductive bump structure used in the wafer bonding structure of the panel of the present invention has an insulating buffer structure to help buffer the compressive stress generated by the wafer bonding process. In addition, the insulation buffer and the structure have a notch design, which can increase the 郷 channel of the non-conductive colloid, so that the reliability of the wafer bonding (4) & In addition, the insulating buffer structure can be made of a photosensitive material, so that the formation of the notch can be easily achieved by exposure and development techniques without additional cost. The above description is only the preferred embodiment of the present invention, and all the modifications and modifications made by the scope of the present invention should be within the scope of the present invention. [Simple diagram of the diagram] 8 201039417 1st to 3rd forest (4) - better practice of the 4th disc of the $ 阁 氐 政 政 政 0 0 0 0 。 。 。 。 。 The two-piece W-die bonding structure of the conductive bump structure of the first embodiment of the present invention is connected to the following:: = - the wafer of the display panel of the preferred embodiment - [Description of main component symbols] conductive bump structure 12 substrate Pad 16 Insulation Buffer Structure Conductive Thin Twist 20 Defective α Display Panel Wafer Bonding Structure 32 Substrate Connection Pad 36 Solder Area Wafer 50 Non-Conductive Colloid 10 14 18 30 Ο 34 40