201038152 六、發明說明： 【發明所屬之技術領域】 本發明係有_電路減術領域，_是有觀路板中的 内層導通薄板或内層連結板的製作方法。201038152 VI. Description of the Invention: [Technical Field of the Invention] The present invention is in the field of _circuit reduction, _ is a method of manufacturing an inner-layer conduction sheet or an inner layer connection sheet in a viewing board.
Ο 【先前技術】 電路板是電腦、手機等電子裝置林可或缺的_組件，主要負 =内部電子元件之咖峨傳遞、連結，並提供散熱魏。在電子 二置不斷追求輕馳小_勢下，電路板上的導_線寬也不斷跟 者M、’因此業者莫不戮力於研究如何突破製程、材料等限制因素， 以祕低成本、_具備高可信财、高性能㈣路板。。 依應闕域’電路板她⑽單面板、雙面板 層板及軟板等等。—舻 上夕 接點腳數越多，：子產叩功能越複雜、迴路距離越長、 資訊及通訊產^ _數_，例如高階輯性電子、 記型電腦、照相機、汽車儀表等。例如筆 201038152 用雷射直接鑽孔(dld)技術，直接雷射成孔，然後再電鍍填孔。其 中，成孔電鍍的規格通常有二：一者為一般盲孔電鍍（非填孔型）， 另一種為填孔電鐘。 上述兩種成孔電鍍的規格均有其缺點，例如，一般盲孔電鍍的缺 點在於電鑛的金屬層厚度不足以應用於高密度、高散熱需求領域； 而填孔電鍍的缺點在於絕緣層厚度增加造成電鍍填孔的困難度、板 〇 面平整性及後續的品質信賴度問題’例如’空洞及氣泡等電鐵品質 不佳現象，且電鍍填孔的品質易受孔徑大小影響。 另外，在與本發明相關的技術文獻中，中國專利授權公告號 CNl〇53785C彼露了 -種嵌人凸塊互連技術（Buried Bump 1时肌0嶋_丁__取），其為東芝(丁〇祕_發的一麵的增 層技術，步驟包括：在—底板上形成编在鋪圖案上重複 ❹ 印刷銀膏，形成接近圓錐狀的導體凸塊；接著將絕緣層，例如，合 成樹脂’壓合在圓錐導體凸塊上，並使圓錐導體凸塊貫穿絕緣層； 接者將另-定義有㈣_的基板對準_導體凸塊並進行熱壓 合；最後，去除底板。 然而此專利的缺點在於，其利用銀膠重複印刷構成的圓錐狀導 體凸塊的導熱性差，·轉與㈣㈣少心丨鄕麟®錐狀¥ 中亦嫌不足H細/ _接合力在高可靠性應用 的=而儀印刷方式形成_導體凸塊有其印刷密度上 201038152 【發明内容】 於是’本發明的目的在提供一種改良的電路板製造方法，可以降 低成本代替過去成孔及電鍍填孔之作法，而不會受到通孔縱橫比的 限制’也不會有通孔電鍍氣泡的不良品質信賴性影響。 為達上述目的’本發明提供一種電路板的製作方法，包含有：提 〇 ^ /、有錐狀金屬凸塊結構的基板，金屬凸塊例如為銅或銀金屬； 使該基板與一絕緣層壓合，該錐狀金屬凸塊結構刺穿該絕緣層，並 路出一尖端部位；壓合一金屬層，使該尖端部位受擠壓，形成一鈍 化部位；平坦化該金屬層及鈍化部位；於該絕緣層上形成一導電層， 接觸該鈍化部位；於該導電層上形成一光阻圖案，該光阻圖案包含 有開口，暴鉻出部分的該導電層；在該開口中形成一電鑛銅層；將 該光阻圖案剝除，留下該電鍍銅層，並暴露出部分的該導電層；以 及蝕除暴露出來的該導電層，形成一圖案化線路。 ) ~為了使貴審查委員能更進-步了解本發明之特徵及技術内 各，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅供 參考與輔助說明用，並非用來對本發明加以限制者。 【實施方式】 清參閱第1圖至第10圖’其為依據本發明較佳實施例所繪示的 6 201038152 電路板的製作方法示意圖。如第1圖所示，首弁描征 根據本發明讀佳實關，雜金屬6塊 鑛、_或模板印刷等方式形成者，例如 包括電 Ο 今屑几4·ΑΛ丄Μ …、U f生树月日，面向錐肤 :=:=:Γ14與基板10貼合，™ L構12會·絕緣層14，而露出其尖端部位12a。 Ο =树明之另—較佳實施例’形成_ 14的作 用液喊龄倾術。 狀金屬第几3 81及第4騎不’接著_—金屬層15進行壓合，使錐 壓r九”。構12刺穿絕緣層14，而露出的尖端部位12a受到擠 =㈣’形成鈍化部位12b。根據本發明之較佳實施例，厚金屬 它金屬勺厚度約介於65微米至250微米之間，其可以是銅、銘或其 ^圖所示，接著，在高溫下，例如，190°C至200。(：，將含 201038152 有Β階段熱固性樹脂的絕緣層14高溫固化成C階段（C_stage)熱 固性樹脂’然後將金屬層15及·^位⑶進行全平面⑽薄化， 或者以研磨方式將其平坦化或共平面化。 經過共平面化之後，此時，鈍化部位既其暴露出來的上表面與 絕緣層14的表面為共平面’而且鈍化部位⑽實質上不會凸出於絕 緣層14的表面。 Ο :第6圖所不，在完成共平面化之後’接著形成—導電層μ， =柯以是彻麵法（包括化學銅層與電鍍鋼層）、物理氣相沈 材料11㈣deP〇Sltl〇n，PV〇)法、賤鍍法或者利用特殊覆膜 例如’帶樹脂導體箱（Primer coated f0il)。 〇分的導電層16。 《義出圖案化線路的位置，並暴露出部 成電錢銅層 =進订電錄製程，在光阻圖案20的開口施中形 如弟9圖所示，接莫脸， 暴露出部分的導電層16圖案2〇剝除’留下電鑛銅層22，並 201038152 如第ίο圖所示，最後蝕除暴露出來的部分的導電層16，形成圖 案化線路24 (包括導電層16與電鑛銅層22)。 ° 第11圖至第13圖繪示本發明另—實施例的示意圖^如第^圖 及第12圖所不，在基板10上形成複數個錐狀金屬凸塊結構ο ,金 屬凸塊例如為鋼或銀金屬，並且形成絕緣層14之後，隨即利用一鋼 板模具35將尖端部位i2a擠壓成鈍化部位12b。 'Ο [Prior Art] The circuit board is a component that can be used in electronic devices such as computers and mobile phones. It is mainly negative = the internal electronic components of the curry transfer, connection, and provide heat dissipation. In the electronic second set of constant pursuit of light and small _ potential, the guide line width on the circuit board is also constantly followed by M, 'so the industry is not trying to study how to break through the limitations of process, materials and other factors, secret low cost, _ With high credibility, high performance (four) road board. . She (10) single-panel, double-panel laminate and soft board, etc. —舻 On the eve, the more the number of contacts, the more complex the childbirth function, the longer the loop distance, the information and communication products, such as high-end electronic, notebook computers, cameras, car instruments, etc. For example, pen 201038152 uses laser direct drilling (dld) technology, direct laser into holes, and then electroplating holes. Among them, there are usually two specifications for hole-forming plating: one is a general blind hole plating (non-filled type), and the other is a hole-filling electric clock. The above two types of hole-forming plating have their disadvantages. For example, the general blind hole plating has the disadvantage that the thickness of the metal layer of the electric ore is not sufficient for the application of high density and high heat dissipation requirements; and the disadvantage of the hole plating is the thickness of the insulation layer. Increasing the difficulty of plating and filling holes, the flatness of the board surface and the subsequent reliability of the quality problem, such as the poor quality of the electric iron such as voids and bubbles, and the quality of the electroplating and filling holes is susceptible to the pore size. In addition, in the technical literature related to the present invention, the Chinese Patent Licensing Bulletin No. CNl〇53785C reveals a kind of embedded bump interconnection technology (Buried Bump 1 muscle 0嶋_丁__取), which is Toshiba (Ding 〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The resin is pressed onto the conical conductor bumps and the conical conductor bumps are inserted through the insulating layer; the substrate is further defined with the (4)_ substrate aligned and thermally pressed; finally, the bottom plate is removed. The disadvantage of this patent is that the conical conductor bumps formed by repeated printing using silver glue have poor thermal conductivity, and the transfer to (4) (4) less heart Kirin® cone shape is also insufficient H fine / _ joint force in high reliability Application of the printing method to form a conductor bump having a printing density of 201038152 [Invention] Therefore, the object of the present invention is to provide an improved circuit board manufacturing method, which can reduce the cost of replacing the hole and the plating hole. practice, It is not limited by the aspect ratio of the through hole. There is no adverse quality reliability effect of the through hole plating bubble. To achieve the above object, the present invention provides a method for manufacturing a circuit board, which comprises: lifting 〇 ^ /, having a cone a metal bump structure substrate, the metal bump is, for example, copper or silver metal; the substrate is laminated with an insulation, the tapered metal bump structure pierces the insulating layer, and a tip portion is formed; a metal layer, the tip portion is pressed to form a passivation portion; the metal layer and the passivation portion are planarized; a conductive layer is formed on the insulating layer to contact the passivation portion; and a photoresist is formed on the conductive layer a pattern, the photoresist pattern includes an opening, a portion of the conductive layer that is chrome-plated; forming an electro-mineralized copper layer in the opening; stripping the photoresist pattern, leaving the electroplated copper layer, and exposing a portion of the The conductive layer; and the exposed conductive layer to form a patterned circuit.) - In order to enable the reviewing committee to further understand the features and technologies of the present invention, please refer to the following detailed description of the present invention. Description and drawing. However, the drawings are for illustrative purposes only and are not intended to limit the invention. [Embodiment] Referring to Figures 1 to 10, a schematic diagram of a method for fabricating a 6 201038152 circuit board according to a preferred embodiment of the present invention is shown. As shown in Fig. 1, the first smear is formed according to the present invention, and is formed by a method such as a 6-mine ore, _ or stencil printing of a miscellaneous metal, for example, including an electric sputum, a smear, and a U. On the day of the tree, the skin is facing the cone: =:=: The crucible 14 is bonded to the substrate 10, and the TM L structure 12 is covered with the insulating layer 14 to expose the tip end portion 12a. Ο = ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ _ _ _ _ _ _ The metal 3rd 81 and the 4th rider are not 'continuously_-the metal layer 15 is pressed to make the taper pressure r9". The structure 12 pierces the insulating layer 14, and the exposed tip portion 12a is squeezed = (four) 'is passivated Portion 12b. According to a preferred embodiment of the invention, the thick metal has a metal spoon thickness between about 65 microns and 250 microns, which may be as shown by copper, Ming or its figure, and then, at elevated temperatures, for example, 190 ° C to 200. (:, the insulating layer 14 containing the 201038152 enamel-stage thermosetting resin is cured at a high temperature into a C-stage thermosetting resin, and then the metal layer 15 and the (3) are thinned all-plane (10), or It is planarized or coplanarized by grinding. After coplanarization, at this time, the exposed upper surface of the passivation portion is coplanar with the surface of the insulating layer 14 and the passivation portion (10) does not substantially protrude. On the surface of the insulating layer 14. Ο : Figure 6 does not, after the completion of the coplanarization, 'subsequently formed — the conductive layer μ, = Ke is the surface method (including chemical copper layer and galvanized steel layer), physical gas phase Shen material 11 (four) deP〇Sltl〇n, PV〇) method, bismuth plating method Special coatings are used, for example, 'Primer coated f0il'. The conductive layer 16 is divided. "The position of the patterned circuit is sensed, and the electricity is exposed to the copper layer = the order recording process. The opening of the photoresist pattern 20 is shaped as shown in FIG. 9, and the surface of the conductive layer 16 is exposed, and the pattern of the conductive layer 16 is removed, and the copper layer 22 is left behind, and 201038152 is as shown in FIG. Finally, the exposed portion of the conductive layer 16 is etched to form a patterned line 24 (including the conductive layer 16 and the electroderaline layer 22). [Fig. 11 to Fig. 13 are views showing another embodiment of the present invention. In the first and fourth figures, a plurality of tapered metal bump structures ο are formed on the substrate 10, and the metal bumps are, for example, steel or silver metal, and after the insulating layer 14 is formed, the tip is then applied by a steel plate mold 35. The portion i2a is extruded into the passivation portion 12b.
接著，如第13圖所示，在高溫下，例如，19(TC至20(TC，將含 有B階段熱固性樹脂的絕緣層14高溫固化成c階段熱固性樹脂，3 然後將鈍化部位1¾進行㈣薄化，或者以研磨方式將其平坦化或 共平面化。㈣共平面化之後，㈣，鈍化雜⑶縣露出耗 上表面與絕緣層14的表面為共平面，而且鈍化部位12b實質上不會Next, as shown in Fig. 13, at a high temperature, for example, 19 (TC to 20 (TC, the insulating layer 14 containing the B-stage thermosetting resin is cured at a high temperature into a c-stage thermosetting resin, 3 and then the passivation portion 13⁄4 is made (four) thin. Or planarizing or coplanarizing it by grinding. (4) After coplanarization, (4), the passivation impurity (3) county exposes the surface and the surface of the insulating layer 14 to be coplanar, and the passivation portion 12b is substantially not
凸出於絕緣層Μ的表面。共平面化後的後續步侧同第6圖至第 忉圖所示者，因此不再重複。 相較於先前技術，本發明至少提供了以下的優點：例如 六⑴基板10上所形成的錐狀金屬凸塊結構12，乃是利用電鑛、姓 4或挺板印御方式形成者，故能與銅财絕佳的接合力，此外， 用電鑛、綱等方式形成的錐狀金屬凸塊結構丨2亦提供更佳的導 '、’、〖生使得電路板具備更好的散熱能力、效能與信賴性。 j2)利用厚金屬層15進行壓合，擠壓錐狀金屬凸塊結構η刺穿絕 、'層W而露出的尖端部位12a，並且進行全平面_薄化，或者以 9 201038152 ===:=一成· 做Γ均上本發日㈣佳實施例，凡依本發日⑽專利範圍所 u之㈣f化與修飾’皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第log為依據本發明較佳實施__的電路板的製 法示意圖。 第11圖至第U圖為依據本發明另—較佳實施例所繪示的電路板的 製作方法示意圖。 【主要元件符號說明】 〇 10基板 12錐狀金屬凸塊結構 ' 12a尖端部位 12b鈍化部位 14絕緣層 15金屬層 16導電層 20 光阻圖案 201038152 20a 開口 22電鍍銅層 24圖案化線路 35鋼板模具A surface that protrudes from the insulating layer. The subsequent step side after coplanarization is the same as that shown in Fig. 6 to Fig. 2, and therefore will not be repeated. Compared with the prior art, the present invention at least provides the following advantages: for example, the tapered metal bump structure 12 formed on the six (1) substrate 10 is formed by using an electric ore, a surname 4 or a slab-printing method. It is excellent in bonding strength with copper. In addition, the tapered metal bump structure 丨2 formed by electric ore, etc. also provides better guidance, ', ', and enables the circuit board to have better heat dissipation capability. , performance and reliability. J2) Pressing the thick metal layer 15 to press the tapered metal bump structure η to pierce the tip portion 12a exposed by the layer W, and perform full-plane thinning, or 9 201038152 ===: =一成· Γ Γ 本 本 本 本 ( ( ( ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through log are schematic diagrams showing the fabrication of a circuit board in accordance with a preferred embodiment of the present invention. 11 to U are schematic views showing a method of fabricating a circuit board according to another preferred embodiment of the present invention. [Main component symbol description] 〇 10 substrate 12 tapered metal bump structure '12a tip portion 12b passivation portion 14 insulating layer 15 metal layer 16 conductive layer 20 photoresist pattern 201038152 20a opening 22 electroplated copper layer 24 patterned circuit 35 steel plate mold