201036116 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種覆晶封裝之製造方法及其結構，特 別係關於一種基板芯材上具開槽之覆晶封裝之製造方法及 其結構。 【先前技術】 習知半導體晶片與基板之覆晶接合技術，其係將晶片 具有凸塊之主動面朝下並加熱壓接在一基板上，由於晶片 與基板兩者之間熱膨脹係數不相匹配。為了防止在晶片與 基板之間的凸塊承受熱應力，導致凸塊熱疲勞（thermal fatigue)與電性連接失敗’常見地在晶片與基板之間的間 隙填充一種具有電絕性及熱固性之底部填充材（ underfilling material)。 該底部填充材係為可毛細流動之液態膠體，用以保護 晶片之線路及凸塊。並可黏接晶片與基板，提供適當之機 械接著強度’以防止應力之局部集中。 習知之底部填充材之塗施技術，係在晶片與基板覆晶 接合後才以點膠（dispensing )方式注入間隙内，可沿著晶 片週邊在基板上塗施「L」或「U」形塗膠圖案之底部填充 材。藉由毛細作用’塗施之底部填充材會流動並漸漸擴及 晶片及基板之間。但此種方式較為費時，要等到底部填充 材慢慢充滿整個間隙，因此影響製程之單位時間產出效率 。且又容易形成内包之空氣氣泡，該氣泡受熱會膨脹而造 成局部焊接點或接著界面之應力破壞。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a structure for fabricating a flip chip package, and more particularly to a method and a structure for fabricating a flip chip package having a slot on a substrate core. [Prior Art] A conventional method of flip chip bonding of a semiconductor wafer and a substrate is to bond the wafer with the active side of the bump facing down and heat-bonded to a substrate, because the thermal expansion coefficients between the wafer and the substrate do not match. . In order to prevent the bump between the wafer and the substrate from being subjected to thermal stress, causing thermal fatigue and electrical connection failure of the bump, the gap between the wafer and the substrate is commonly filled with a bottom having electrical extinction and thermosetting. Underfilling material. The underfill is a liquid colloid that can be capillaryly flowed to protect the wiring and bumps of the wafer. The wafer and substrate can be bonded to provide proper mechanical strength to prevent localized concentration of stress. The coating technique of the underfill material is applied to the gap after the wafer and the substrate are flip-chip bonded, and the "L" or "U"-shaped glue can be applied on the substrate along the periphery of the wafer. The bottom filler of the pattern. The underfill material applied by capillary action will flow and gradually spread between the wafer and the substrate. However, this method is more time consuming, and it is necessary to wait until the bottom filler material slowly fills the entire gap, thus affecting the unit time efficiency of the process. Moreover, it is easy to form an air bubble which is inflated, and the bubble is expanded by heat to cause localized solder joints or stress damage at the interface.
Z-137399.DOC •4- 201036116 綜上所述，提昇覆晶封裝之底部填充材之塗佈效率仍 有限制瓶頸，若能省去底部填充材之塗佈則更為有助於增 進覆晶封裝之製造’故此實為目前覆晶封裝技術所丞待克 服之重要課題。 【發明内容】 本發明之一範例係提供一種覆晶封裝之製造方法及其 結構，藉由封裝基板上、晶片覆蓋處預先形成一凹槽，藉 ◎ 由該凹槽能省去底部填充材之塗佈製程，並且能兼顧晶片 及封裝基板間空隙之填滿品質。 综上所述，本發明揭露之覆晶封裝包含一基板、一晶 片以及複數個凸塊。該基板包含一絕緣層、一線路層複 數個導通柱及複數個第二接墊。該絕緣層具有一開槽及複 數個通孔。該線路層設於該絕緣層之表面，且該線路層具 有延伸於該開槽上之複數個第一接墊及和該複數個第一接 墊相連接之複數個連接線路。該些導通柱設於該複數個通 Q 孔内，並和該複數個連接線路相連接。該些第二接墊設於 相對於β亥線路層之該絕緣層的另一表面，並和該複數個導 通柱相連接。該晶片藉由該複數個凸塊電性連接該複數個 第一接墊。 根據本發明一實施例，前述之絕緣層係可撓性基板。 本發明揭露覆晶封裝之製造方法，包含下列步驟：於 一絕緣層之中間形成一開槽及複數個通孔；壓合兩金屬薄 膜於該絕緣層之兩個表面；圖案化一該金屬薄膜為複數個 第一接墊及複數個連接線路，及圖案化另一該金屬薄膜為Z-137399.DOC •4- 201036116 In summary, there is still a limit bottleneck in improving the coating efficiency of the underfill of the flip chip package. If the underfill material is omitted, it will help to improve the flip chip. The manufacture of packages is therefore an important issue that needs to be overcome in the current flip chip packaging technology. SUMMARY OF THE INVENTION An example of the present invention provides a method for fabricating a flip chip package and a structure thereof. A recess is formed in advance on a package substrate and a wafer cover portion, and the underfill material can be omitted by the groove. The coating process can balance the filling quality of the gap between the wafer and the package substrate. In summary, the flip chip package disclosed in the present invention comprises a substrate, a wafer, and a plurality of bumps. The substrate comprises an insulating layer, a plurality of conductive pillars of the circuit layer and a plurality of second pads. The insulating layer has a slot and a plurality of through holes. The circuit layer is disposed on a surface of the insulating layer, and the circuit layer has a plurality of first pads extending on the slots and a plurality of connecting lines connected to the plurality of first pads. The conductive pillars are disposed in the plurality of through holes and connected to the plurality of connecting lines. The second pads are disposed on the other surface of the insulating layer with respect to the β-circuit layer and are connected to the plurality of via posts. The plurality of bumps are electrically connected to the plurality of first pads by the plurality of bumps. According to an embodiment of the invention, the insulating layer is a flexible substrate. The invention discloses a method for manufacturing a flip chip package, comprising the steps of: forming a groove and a plurality of through holes in the middle of an insulating layer; pressing two metal films on two surfaces of the insulating layer; and patterning the metal film a plurality of first pads and a plurality of connecting lines, and patterning the other metal film as
厶 137399.DOC 201036116 複數個第二接墊，其中該複數個第一接墊係延伸於該開槽 上’並和該複數個連接線路相連接；於該複數個通孔填充 複數個導通柱以連接該複數個連接線路及該複數個第二接 墊；以及將一晶片覆晶接合於該複數個第一接墊上。 【實施方式】 圖1A〜1E係本發明一實施例之覆晶封裝之製造方法 之流程示意圖。如圖1A所示，首先提供一絕緣層13，並於 ◎ 該絕緣層13上形成一開槽131及複數個通孔132。本實施例 中，開槽131例如為一矩形，且設於絕緣層13中間處，複數 個通孔132排列於開槽131兩側，可呈現直線排列或者式矩 陣式排列。絕緣層13之材質可為BT樹脂（ Bismaleimide-Triazine resin)或一可撓基板（例如：聚乙 醯安（polyimide))。 參見圖1B，於絕緣層13之兩相對表面上，分別設置金 屬薄膜1 Γ和12'，然後，將該等金屬薄膜11'和12,壓合於絕 〇 緣層13之相對應之表面。較佳地，金屬薄膜11’和12'為銅猪 ’而金屬薄膜II1和I2·係以銅猪壓合製程（process of copper foil lamination)壓合於絕緣層13之表面。 參見圖1C，對金屬薄膜1Γ以相對應之預定電路圖案進 行蝕刻，以獲得線路層11，其中線路層11可包含具有延伸 於該開槽131上之複數個第一接墊112、和該複數個第一接 墊112相連接之複數個連接線路ill以及複數個空接塾（ dummy pad) 113。該些空接墊113和該線路層11係在該絕緣 層13之相同表面。本實施例中，該些第一接墊112分別排列 厶 137399.DOC -6 - 201036116 於開槽m兩侧，該些第一接塾112例如可對稱設置，該此 通孔132與該些第-接塾112相對應地設置，連接線路⑴相 對應地連接著該些第-接墊112與該些通孔132。同樣地， 對金屬薄膜12，以相對應之預定電路圖案進行㈣，以獲得 複數個第二接墊12。一實施例中，該些第二接_係與該 些通孔132相對應。本實施例中，該些第二接墊砂別位於 相對應的該些通孔132之開口上。 ❹厶 137399.DOC 201036116 a plurality of second pads, wherein the plurality of first pads extend on the slot and are connected to the plurality of connecting lines; wherein the plurality of through holes are filled with a plurality of conductive posts Connecting the plurality of connection lines and the plurality of second pads; and bonding a wafer to the plurality of first pads. [Embodiment] Figs. 1A to 1E are schematic flow charts showing a method of manufacturing a flip chip package according to an embodiment of the present invention. As shown in FIG. 1A, an insulating layer 13 is first provided, and a slit 131 and a plurality of through holes 132 are formed in the insulating layer 13. In this embodiment, the slot 131 is, for example, a rectangle, and is disposed at the middle of the insulating layer 13. The plurality of through holes 132 are arranged on both sides of the slot 131, and may be arranged in a straight line or in a matrix arrangement. The material of the insulating layer 13 may be a BT resin (Bismaleimide-Triazine resin) or a flexible substrate (for example, polyimide). Referring to Fig. 1B, on the opposite surfaces of the insulating layer 13, metal thin films 1 and 12' are respectively provided, and then the metal thin films 11' and 12 are press-bonded to the corresponding surfaces of the insulating layer 13. Preferably, the metal films 11' and 12' are copper pigs and the metal films II1 and I2 are pressed against the surface of the insulating layer 13 by a process of copper foil lamination. Referring to FIG. 1C, the metal thin film 1 is etched in a corresponding predetermined circuit pattern to obtain a wiring layer 11, wherein the wiring layer 11 may include a plurality of first pads 112 extending from the opening 131, and the plurality The first pads 112 are connected to a plurality of connection lines ill and a plurality of dummy pads 113. The dummy pads 113 and the wiring layer 11 are on the same surface of the insulating layer 13. In this embodiment, the first pads 112 are respectively arranged on the two sides of the slot 135. The first interface 112 can be symmetrically disposed, and the through holes 132 and the first The interface 112 is correspondingly disposed, and the connection pads (1) are correspondingly connected to the first pads 112 and the through holes 132. Similarly, the metal thin film 12 is subjected to (four) in a predetermined circuit pattern to obtain a plurality of second pads 12. In an embodiment, the second connections correspond to the through holes 132. In this embodiment, the second pads are located on the openings of the corresponding through holes 132. ❹
將金屬薄膜11'和12,圖案化後，接著，進行貫孔電鑛製 程’使該些通孔填充，以形成分別用於連接該些連接線路 111與該些第二接墊12之複數個導通柱14。由於第一接墊 112與第二接墊12係位於兩相對表面’藉由前述之製程，可 使第一接墊112相對應地與第二接墊12間電性導通。最後， 對絕緣層13兩相對表面上之電路圖案塗佈一保護層2〇。本 實施例中，該保護層20係綠漆。本實施例中，該些空接墊 113可分別設置於絕緣層13兩相對邊附近，靠近兩相對側邊 之該些空接墊113可於數量上 '或幾何排列上實質地對稱。 參見圖1D，於完成電路圖案後，於第二接墊12侧處， 提供一治具80。該治具80具有一支持部81，支持部81伸入 開槽13 1中。然後，一晶片} 5藉由複數個凸塊j 7將晶片】$ 之複數個接點（未繪示）覆晶接合於該些第一接墊122上， 以及該些空接墊113上》該複數個接點（未繪示）可位於晶 片15之中央處。當晶片ls接合時，支持部81頂抵住該些第 一接墊112，使該些第一接墊122與晶片15間得以牢固地完 成接合。晶片15藉由虛擬（dummy)凸塊21與空接墊113接合After the metal thin films 11' and 12 are patterned, and then, the through-hole electrowinning process is performed to fill the through holes to form a plurality of connecting wires 111 and the second pads 12, respectively. The column 14 is turned on. Since the first pad 112 and the second pad 12 are located on opposite surfaces, the first pad 112 can be electrically connected to the second pad 12 correspondingly by the foregoing process. Finally, a protective layer 2 is applied to the circuit patterns on the opposite surfaces of the insulating layer 13. In this embodiment, the protective layer 20 is green lacquer. In this embodiment, the vacant pads 113 may be respectively disposed near opposite sides of the insulating layer 13. The vacant pads 113 adjacent to the opposite sides may be substantially symmetrical in quantity or geometric arrangement. Referring to FIG. 1D, after the circuit pattern is completed, a jig 80 is provided at the side of the second pad 12. The jig 80 has a support portion 81 into which the support portion 81 projects. Then, a wafer} 5 is flip-chip bonded to the first pads 122 by a plurality of bumps (not shown) of the wafer by a plurality of bumps j 7 , and the dummy pads 113 The plurality of contacts (not shown) may be located at the center of the wafer 15. When the wafers ls are bonded, the supporting portion 81 abuts against the first pads 112 to firmly bond the first pads 122 and the wafers 15. The wafer 15 is bonded to the dummy pad 113 by dummy bumps 21
厶 137399DOC -7- 201036116 ，使晶片15兩相對側邊獲得支撐而穩固，使其不至於發生 擺動的情形而損壞晶片15與第一接塾112間之接合。.該些第 一接墊112係根據晶片15接點對應設置，該些空接墊113之 作用主要係使接合後之晶片15穩固’該些空接塾113之設置 可依實際需求設置，不限於本案揭示之態樣。 參見圖1E，覆蓋一封裝膠體16於晶片15、開槽131、該 些第一接墊112及該些連接線路hi上，並藉由烘烤或其他 製程使該封裝膠體16固化。然後，分別配置複數個錫球j 8 〇 於該基板19上之第二接墊12，該複數個錫球18係作為覆晶 封裝10之I/O接點。 參見圖1E ’基板19上設有一開槽131，晶片15覆蓋於該 開槽131上’封裝膠體16可以自開槽131及晶片15四周填充 晶片15和基板19間之空隙，而不需要再另外利用底部填充 膠去填滿該空隙’故能省去底部填充製程所需之時間及成 本。晶片15底部設開槽131更可使封裝膠體16滲入該空隙時 ❹ ’不會發生内包之空氣氣泡’導致氣泡受熱會膨脹，而造 成局部焊接點或接著界面之應力破壞。 參照圖2，本發明揭示之覆晶封裝3〇包含一撓性基板32 、日日片34及複數個凸塊36。該撓性基板（flexible circuit board)32 ’其包含一絕緣層38、一線路層40、以及複數個導 通柱42 ’内可充填一導電料例如銅材或其他金屬材料。絕 緣層38具有一開槽44及複數個通孔46。線路層40設於絕緣 層38之一表面，其具有如圖1C所示之延伸於開槽44上之複 數個接墊（未繪示），以及與該複數個接墊相連接之複數137 137399DOC -7- 201036116, the two opposite sides of the wafer 15 are supported and stabilized so that they do not wobble and damage the bonding between the wafer 15 and the first interface 112. The first pads 112 are arranged according to the contacts of the wafers 15. The functions of the empty pads 113 are mainly to stabilize the bonded wafers 15. The settings of the blanks 113 can be set according to actual needs, Limited to the aspects revealed in this case. Referring to FIG. 1E, an encapsulant 16 is applied over the wafer 15, the trench 131, the first pads 112, and the connection lines hi, and the encapsulant 16 is cured by baking or other processes. Then, a plurality of solder balls j 8 are respectively disposed on the second pads 12 on the substrate 19, and the plurality of solder balls 18 serve as I/O contacts of the flip chip package 10. Referring to FIG. 1E, the substrate 19 is provided with a slit 131 on which the wafer 15 covers. The encapsulant 16 can fill the gap between the wafer 15 and the substrate 19 from the trench 131 and the periphery of the wafer 15 without additional The underfill is used to fill the voids, thus eliminating the time and cost of the underfill process. The bottom surface of the wafer 15 is provided with a groove 131 so that the encapsulant 16 can penetrate into the gap, and 内 ' does not cause air bubbles to be entrapped, causing the bubble to expand due to heat, causing stress damage at the local solder joint or the interface. Referring to FIG. 2, the flip chip package 3A of the present invention comprises a flexible substrate 32, a day sheet 34 and a plurality of bumps 36. The flexible circuit board 32' includes an insulating layer 38, a wiring layer 40, and a plurality of conductive pillars 42' which may be filled with a conductive material such as copper or other metal material. The insulating layer 38 has a slot 44 and a plurality of through holes 46. The circuit layer 40 is disposed on a surface of the insulating layer 38, and has a plurality of pads (not shown) extending from the slots 44 as shown in FIG. 1C, and a plurality of pads connected to the plurality of pads.
厶 137399.DOC 201036116 個連接線路。複數個導通柱42設於相對應之通孔46内，並 與該複數個連接線路相連接。於其他實施例中，該通孔46 可不需配置導通柱42。 複數個凸塊36相對應地設置於該些接墊（未繪示）， 設於晶片中央之接點（未繪示）連接至該些凸塊36上，並 藉此與連接線路電性相連。線路層4〇上可另包含複數個空 接塾（未緣不），其中該複數個空接墊和該線路層40係在 〇 該絕緣層38之相同表面，並藉由相對應之複數個虛擬 (dummy)凸塊31和晶片34相結合，藉此穩固設置於可撓基板 32上之晶片34。 覆晶封裝30另包含一封裝膠體，其係包覆該晶片34、 開槽44、凸塊（36和31)及線路層40。覆晶封裝3〇可另包含複 數個外部端子48例如是錫球，該些外部端子48位於該絕緣 層38之另一表面且電性連接該導通柱42。於其他實施例中 ，該些通孔也46可不需配置導通柱42，該些外部端子“可 ❹ 透過該通孔46而直接與該線路層4〇電性連接。 根據圖2實施例之覆晶封裝，本發明揭示一種覆晶封裝 之製造方法，其包含下步驟：於一可挽基板之中間形成一 開槽及複數個通孔；於絕緣層之一表面上形成金屬薄膜； 圖案化該金屬薄膜，使其形成一線路層並具複數個接塾及 複數個連接線路，其中該複數個第一接塾係延伸於該開槽 上’並和該複數個連接線路相連接；於該複數個通孔填充 複數個導通柱以連接該複數個連接線路，然而於其他實施 例也可不充填導itm治具置入該開槽内以頂抵該 厶 137399.DOC -9 - 201036116 複數個第一接墊’使一晶片覆晶接合於該複數個第一接墊 上’絕緣層之另一表面上，配置複數個外部端子以電性連 接該二導通柱或者該些外部端子係透過該通孔而直接電性 連接該線路層；以及形成一封裝膠體包覆該晶片、該開槽 、該凸塊、該複數個第一接墊及該複數個連接線路。 參照圖3’本發明另一實施例揭示一覆晶封裝5〇，其包 含一基板52、一晶片54、以及複數個凸塊56。基板52包含 0 一絕緣層58、一雙層線路層60、複數個導通柱64、及複數 個第二接墊66。絕緣層58具有一開槽68及複數個通孔70。 雙層線路層60設於絕緣層58之表面，其具有複數個第一接 塾（未繪示），該些第一接墊延伸於開槽68上，且與雙層 線路層60内之複數個連接線路電性連接。該些導通柱料分 別設於該些通孔7 〇中，且於複數個連接線路電性相連。第 二接塾66設於絕緣層58之另一表面，並分別與該些導通柱 64電性相連。該些凸塊56則分別用於電性連接晶片54及該 ◎ 些第一接墊（未繪示）。 覆晶封裝50另具有一黏著層72，其係設於晶片54與基 板52間，用於穩固封裝後之晶片54。封裝膠體74覆蓋於晶 片54、凸塊56、開槽68及雙層線路層60，而各第二接墊66 上可分別設有相對應之外部端子76例如是錫球。本實施例 中’該基板52可為一BT基板或者是可撓性基板。 本發明之技術内容及技術特點已揭示如上，然而熟悉 本項技術之人士仍可能基於本發明之教示及揭示而作種種 不背離本發明精神之替換及修飾。因此，本發明之保護範 厶 137399DOC -10- 201036116 圍應不限於實施例所揭示者，而應包括各種不背離 之替換及修飾，並為以下之申請專利範圍所涵蓋離本發明 【圖式簡要說明】 圖1A〜1E係本發明一實施例之覆晶封裝之製造方法 之流程示意圖； 圖2係本發明一實施例之覆晶封裝之示意圖；及 圖3係本發明另一實施例之覆晶封裝之示意圖。 【主要元件符號說明】 10 覆晶封裝 11 線路層 11' 金屬薄膜 12 第二接墊 12' 金屬薄膜 13 絕緣層 14 導通柱 15 晶片 16 封裝膠體 17 凸塊 18 錫球 19 基板 20 保護層 21 虛擬凸塊 30 覆晶封裝 31 虛擬凸塊 32 可挽基板厶 137399.DOC 201036116 connection lines. A plurality of conductive posts 42 are disposed in the corresponding through holes 46 and connected to the plurality of connecting lines. In other embodiments, the through hole 46 may not need to be configured with the conductive post 42. A plurality of bumps 36 are correspondingly disposed on the pads (not shown), and contacts (not shown) disposed at the center of the wafer are connected to the bumps 36, thereby being electrically connected to the connecting lines. . The circuit layer 4 can further include a plurality of blanks (not edged), wherein the plurality of empty pads and the circuit layer 40 are on the same surface of the insulating layer 38, and by a plurality of corresponding ones A dummy bump 31 is bonded to the wafer 34, whereby the wafer 34 is stably disposed on the flexible substrate 32. The flip chip package 30 further includes an encapsulant that encapsulates the wafer 34, the trenches 44, the bumps (36 and 31), and the wiring layer 40. The flip chip package 3 can further include a plurality of external terminals 48, such as solder balls, which are located on the other surface of the insulating layer 38 and are electrically connected to the via posts 42. In other embodiments, the through holes 46 do not need to be disposed with the conductive posts 42. The external terminals are “directly connected to the circuit layer 4 透过 through the through holes 46. According to the embodiment of FIG. 2 The present invention discloses a method for manufacturing a flip chip package, comprising the steps of: forming a slot and a plurality of through holes in a middle of a pullable substrate; forming a metal film on one surface of the insulating layer; patterning the a metal film, which is formed into a circuit layer and has a plurality of interfaces and a plurality of connecting lines, wherein the plurality of first interfaces extend on the slot and are connected to the plurality of connecting lines; The through holes are filled with a plurality of conductive posts to connect the plurality of connecting lines. However, in other embodiments, the filling is not inserted into the slots to reach the 厶137399.DOC -9 - 201036116 The pad is configured to bond a wafer to the other surface of the insulating layer on the plurality of first pads, and a plurality of external terminals are disposed to electrically connect the two conductive posts or the external terminals pass through the through holes. direct Electrically connecting the circuit layer; and forming an encapsulant covering the wafer, the slot, the bump, the plurality of first pads, and the plurality of connecting lines. Referring to FIG. 3, another embodiment of the present invention discloses A flip chip package 5A includes a substrate 52, a wafer 54, and a plurality of bumps 56. The substrate 52 includes an insulating layer 58, a double layer 60, a plurality of vias 64, and a plurality of The second pad 66. The insulating layer 58 has a slot 68 and a plurality of through holes 70. The double layer circuit layer 60 is disposed on the surface of the insulating layer 58 and has a plurality of first interfaces (not shown). A pad extends on the slot 68 and is electrically connected to a plurality of connecting lines in the double-layer circuit layer 60. The conductive pillars are respectively disposed in the through holes 7 , and are electrically connected to the plurality of connecting lines The second interface 66 is disposed on the other surface of the insulating layer 58 and electrically connected to the conductive pillars 64. The bumps 56 are respectively used for electrically connecting the wafers 54 and the first ones. a pad (not shown). The flip chip package 50 further has an adhesive layer 72 which is attached to the wafer 54 and the base. 52 is used for stabilizing the packaged wafer 54. The encapsulant 74 covers the wafer 54, the bump 56, the slot 68 and the double layer circuit layer 60, and each of the second pads 66 can be respectively provided with a corresponding external portion. The terminal 76 is, for example, a solder ball. In the present embodiment, the substrate 52 can be a BT substrate or a flexible substrate. The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still be based on the present invention. The invention is not limited to the embodiments of the present invention, and the present invention is not limited to the embodiments disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1E are schematic diagrams showing a method of manufacturing a flip chip package according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a method for fabricating a flip chip package according to an embodiment of the present invention; A schematic diagram of a flip chip package; and FIG. 3 is a schematic view of a flip chip package according to another embodiment of the present invention. [Main component symbol description] 10 Flip chip package 11 Circuit layer 11' Metal film 12 Second pad 12' Metal film 13 Insulation layer 14 Conduction post 15 Wafer 16 Package colloid 17 Bump 18 Tin ball 19 Substrate 20 Protective layer 21 Virtual Bump 30 flip chip package 31 dummy bump 32 pullable substrate
厶 137399.DOC 201036116厶 137399.DOC 201036116
34 晶片 36 凸塊 38 絕緣層 40 線路層 42 導通柱 44 開槽 46 通孔 48 外部端子 50 覆晶封裝 52 基板 54 晶片 56 凸塊 58 絕緣層 60 雙層線路層 64 導通柱 66 第二接墊 68 開槽 70 通孔 72 黏著層 74 封裝膠體 76 外部端子 80 治具 81 支持部 111 連接線路 112 第一接墊 厶 137399.DOC -12 201036116 113 空接墊 131 開槽 132 通孔34 Wafer 36 Bump 38 Insulation 40 Wafer Layer 42 Via Post 44 Slot 46 Through Hole 48 External Terminal 50 Flip Chip Package 52 Substrate 54 Wafer 56 Bump 58 Insulation Layer 60 Double Layer Layer 64 Conductor Post 66 Second Pad 68 Slotted 70 Through Hole 72 Adhesive Layer 74 Encapsulant 76 External Terminal 80 Fixture 81 Support 111 Connection Line 112 First Pad 厶137399.DOC -12 201036116 113 Empty Pad 131 Slot 132 Through Hole
厶 137399.DOC -13-厶 137399.DOC -13-