201024949 六、發明說明： 【發明所屬之技術領域】 本發明疋有關於一種產生電流槽（currentsink)與電 流參考的電路以及一種產生電流槽的方法，且特別是（但 並非唯獨）有關於產生電流槽給驅動器以驅動液晶顯示器 (liquid crystal display，LCD)背光源（backlight)中的多 個發光二極體（light-emitting diodes，LEDs)。 【先前技術】 在驅動液晶顯示器背光源所用的多條串聯發光二極體 鏈（chains)時’需要有可靠的、精確的、連貫的、恒定 的電流。電流槽或電流源可用來提供這種電流。用來灌入 (sinking)單條發光二極體鏈之驅動電流的一種習知的恒 定電流槽電路的示例繪示在圖1中。 此電流槽電路100包括參考電壓101。此參考電壓101 之輸出連接至運算放大器103之輸入之一。此運算放大器 1〇3之輸出連接至電晶體1〇5之閘極（gate)。此電晶體 105之源極（source)連接至感測電阻器1()7之第一端 (terminal)。此感測電阻器1〇7之第二端接地。感測電阻 器107之第一端也連接至運算放大器1〇3之第二輸入。電 晶體105之汲極（drain)連接至輸出端109。此輸出端109 連接至發光二極體鏈。 操作時，與輸出端109相連的發光二極體鏈中的電流 流經感測電阻器107。在一個閉合回饋環路配置中，比較 器103將感測電阻器1〇7兩端的電壓降（voltage drop)與 201024949 從參考電壓101中輸出的參考電壓進行比較。運算放大器 之輸出致使電晶體105改變發光二極體鍵的電流拉出 (current drawn) ’進而改變發光二極體鏈的電流灌入 (current sink)。 要想獨立地驅動多條這樣的發光二極體鏈，就需要多 個這樣的電路。另外，在整合圖1之電流槽電路時，電阻 器作為外接元件，使得發光二極體驅動電路的設計變得複 鲁 雜此外，感測電阻器的公差（tolerances)給電流槽帶來 不精確性。再者，電流槽的電流無法進行數位選擇。 【發明内容】 本發明的目的是提供一種減少上述缺點的簡化的全 面整合電流槽。 依照第一觀點’此目的是透過一種電流槽電路來實 現，此電流槽電路包括：相互並聯的多個電流槽，這些電 流槽中的每個電流槽連接至串級（cascoded)開關元件， _ 多個電流槽之每個電流槽與串級開關元件經切換以灌入第 一電流，以及總和節點（summing n〇de )，用以灌入第二 電流’此第二電流是多路第一電流之總和。 例如’在本實施例中，每個電流槽連接至其各自的串 級開關元件。如此一來，輸出電流可藉由切換多個並聯的 電流槽來進行選擇。另外，因為所有的電流槽電晶體都具 有與電流參考電晶體相同的構造與取向，所以多個輸出級 之間具有精確的電流匹配（current matching )。此外，所 有的驅動器區塊都能夠獨立地切換接通與斷開。在無不均 5 201024949 勻電流分配的别長下，右需要高於驅動級（driver stage) 極限的電流，則可將多個驅動級並聯起來。另外，一種單 一裝置被用來充當串級開關。因此，不需要單獨的切換裝 置，因為互補金屬氧化物半導體積體電路被賦予更有效的 設計，所以會減少等待時間（latenCy )，降低頂部空間要 求，簡化製造過程》 在一實施例中，電流槽是由多個相同的可切換電流槽 來組成，這些電流槽相互並聯，且具有共用參考電流，使 得每個電流槽能夠灌入相等的單位電流（unit current)。 此單位電流是用參考電流電路來設定。與每個電流槽串聯 的開關所用的控制閘以二進位方式進行分組，使得i個、2 個、4個、8個、16個或32個電流槽可接通，或從！至2η-ι 的任意組合可接通。如此一來，就能夠按一個電流單位的 步長（steps)來切換丨至個電流槽。此外，多個輸出 級之間具有精確的電流匹配。 所有電流槽的公共節點連接至發光二極體的陰極或 串發光二極體中的最後一個發光二極體的陰極。發光二 極趙的陽極或-串發光二極體中的第一個發光二極體的陽 極連接至可調節的正電壓，以致於當這些發光二極體接通 (即，一個或多個電流槽切換接通）時，最後一個發光二 極逋的陰極（電流槽的公共連接點）之處的電壓是1伏特。 $流槽電晶體兩端的電壓選為〖伏特是為了使驅動級的消 耗達到最小化，而不會降低電流槽的功能。 要驅動更多的發光二極體或發光二極體串（strings)， 201024949 j2y»Dpif 可實，多個驅動單元。若發光二極體或發光二極體串 的電、抓大^-驅動單元能夠提供的電流，則可將 多個驅動單元或輪出節點並聯起來且加在電流槽上。在^ 不均勻電流分配的前提下，若需要高於驅動級極限的電 流，則可將多個驅動級並聯起來。201024949 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a circuit for generating a current sink and a current reference, and a method for generating a current sink, and particularly, but not exclusively, for generating The current sinks drive the driver to drive a plurality of light-emitting diodes (LEDs) in a liquid crystal display (LCD) backlight. [Prior Art] A reliable, accurate, consistent, constant current is required when driving a plurality of series of light-emitting diode chains used in a backlight of a liquid crystal display. A current sink or current source can be used to provide this current. An example of a conventional constant current sink circuit for sinking a single LED dipole chain is shown in FIG. This current sink circuit 100 includes a reference voltage 101. The output of this reference voltage 101 is coupled to one of the inputs of operational amplifier 103. The output of this operational amplifier 1〇3 is connected to the gate of the transistor 1〇5. The source of this transistor 105 is connected to the first terminal of the sense resistor 1 () 7. The second end of the sense resistor 1〇7 is grounded. The first end of the sense resistor 107 is also coupled to the second input of the operational amplifier 1〇3. A drain of the transistor 105 is connected to the output 109. This output 109 is connected to the LED chain. In operation, current in the LED chain connected to output 109 flows through sense resistor 107. In a closed feedback loop configuration, comparator 103 compares the voltage drop across sense resistor 1〇7 with the reference voltage output from reference voltage 101 in 201024949. The output of the operational amplifier causes the transistor 105 to change the current drawn of the LED contacts and thereby change the current sink of the LED chain. To drive multiple such LED chains independently, multiple such circuits are required. In addition, when the current tank circuit of FIG. 1 is integrated, the resistor acts as an external component, so that the design of the LED driving circuit becomes complicated. In addition, the tolerance of the sensing resistor brings inaccuracy to the current sink. Sex. Furthermore, the current in the current sink cannot be digitally selected. SUMMARY OF THE INVENTION It is an object of the present invention to provide a simplified fully integrated current sink that reduces the above disadvantages. According to a first aspect, the object is achieved by a current tank circuit comprising: a plurality of current slots connected in parallel with each other, each of the current slots being connected to a cascoded switching element, _ Each of the plurality of current slots and the cascade switching element are switched to sink a first current, and a summing node (summing n〇de) for sinking a second current 'this second current is multi-channel first The sum of the currents. For example, in the present embodiment, each current sink is connected to its respective cascade switching element. In this way, the output current can be selected by switching a plurality of parallel current sinks. In addition, because all current cell transistors have the same configuration and orientation as the current reference transistor, there is accurate current matching between the multiple output stages. In addition, all drive blocks can be switched on and off independently. In the case of no unevenness 5 201024949, the current distribution is higher than the limit of the driver stage, and multiple drive stages can be connected in parallel. In addition, a single device is used to act as a cascade switch. Therefore, a separate switching device is not required because the complementary metal oxide semiconductor integrated circuit is given a more efficient design, so the latency (latenCy) is reduced, the headspace requirement is reduced, and the manufacturing process is simplified. In one embodiment, the current The slot is composed of a plurality of identical switchable current slots that are connected in parallel with each other and have a common reference current such that each current slot can be filled with an equal unit current. This unit current is set by the reference current circuit. The control gates used for the switches in series with each current sink are grouped in binary mode so that i, 2, 4, 8, 16, or 32 current slots can be turned on, or from! Any combination up to 2η-ι can be turned on. In this way, it is possible to switch the current tank to one current step by one step. In addition, there is precise current matching between multiple output stages. The common node of all current sinks is connected to the cathode of the light-emitting diode or the cathode of the last one of the string of light-emitting diodes. The anode of the first LED of the luminescent diode or the string of LEDs is connected to an adjustable positive voltage such that when the LEDs are turned on (ie, one or more currents) When the slot switch is turned on, the voltage at the cathode of the last LED (the common connection point of the current sink) is 1 volt. The voltage across the slot cell is chosen to be volts in order to minimize the consumption of the driver stage without reducing the function of the current sink. To drive more LEDs or strings of LEDs, 201024949 j2y»Dpif can be implemented with multiple drive units. If the current of the light-emitting diode or the light-emitting diode string can be supplied by the large driving unit, a plurality of driving units or wheel-out nodes can be connected in parallel and applied to the current tank. In the case of uneven current distribution, if more current is required than the drive stage limit, multiple drive stages can be connected in parallel.
在此情形下，每個電流槽的開關可利用-個6位元暫 存器（register)來進行數位控制。此暫存器中載入一數值， 指=有多少電流槽接通。暫存器之輸出的致能（咖此） 使得所有電赌it件賴或騎隨字接通，從而使輸 電流向發光二極體發出脈衝（pulsing)。 電流參考電路可連接至多個電流槽之每個電流槽，以 輸出共用參考電流給多㈣流槽。因此，電流槽是透過單 次參考（singlereference)來限定，且傳播至電流槽。 因此，參考電流是利用一個功能區塊來產生並分配 給多電晶體（multi-transistor)輸出區塊。與透過設計來限 定電流的其他方案相同的是，每個區塊中不對輸出電流進 行取樣或測量。 在一實施例中，參考電晶體與多個鏡像電晶體（mirr〇r transistors)是實質上相同的。因為具相等端電壓的相等尺 寸電晶體會有相等的電流流經電晶體，所以藉由整定 (settingup)流經第一電晶體的規定電流，且將第一電晶 體的閘極連接至其他相同尺寸的電晶體的閘極，那麼第二 電晶體就會有相等的電流流過其汲極/源極之間。 依照本發明的另一觀點，本發明的目的也可透過多個 7 201024949 jzyoopii 發光二極體所用驅動器來實現，此驅動器包括以上第一觀 點所述的用來灌入電流以驅動多個發光二極體的電流槽電 路。 在標準的互補金屬氧化物半導體（complementary metal oxide semiconductor，CMOS)製程中，以上觀點所述 的電路適合以積體電路的形式來實施。 為讓本發明之上述特徵和優點能更明顯易僅，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 下面將參照圖2來描述一種電流槽電路的實施例。此 電流槽電路200包括參考輸入端201。此參考輸入端201 連接至第一參考電晶體203的汲極與閘極。第一參考電晶 體203是一個二極體連接形式的η型電晶體。第一參考電 晶體203的源極接地。 電流槽電路200更包括多個切換輸入端207_1至 207_4。雖然此處繪示為四個切換輸入端，但是值得注意的 是，根據要切換的電流槽群組的數量，可提供任何數量的 切換輸入端。 第一切換輸入端207_1連接至第一群組209_1的第一 η型電晶體（串級開關元件）211_1的閘極。第一群組2〇9_1 的第一 η型電晶體211一1的汲極連接至總和節點215。第 一群組209_1的第一 η型電晶體211一1的源極連接至第一 群組209_1的第二η型電晶體213_1 (電流槽）的汲極。 第一群組209一1的第二η型電晶髏213 j的源極接地。第 201024949 j/yeDpif 金ίΐΓΙ—1的第二n型電晶體213」的閘極連接至β 參考電晶髏203的閘極。 第二切換輸入端2(2連接至第二群组2〇9 2的一對 f订連接的第一 η型電晶體（串級開關元件）211 2的閘In this case, each current slot switch can be digitally controlled using a 6-bit register. A value is loaded in this register, which means = how many current slots are connected. The enablement of the output of the register allows the power to be pulsed to the light-emitting diode. A current reference circuit can be connected to each of the plurality of current sinks to output a common reference current to the multiple (four) flow cell. Therefore, the current sink is defined by a single reference and propagates to the current sink. Therefore, the reference current is generated using a functional block and distributed to a multi-transistor output block. As with other schemes that limit the current through design, the output current is not sampled or measured in each block. In an embodiment, the reference transistor is substantially identical to the plurality of mirror transistors. Since equal-sized transistors with equal terminal voltages have equal current flowing through the transistor, the prescribed current flowing through the first transistor is set and the gate of the first transistor is connected to the other The gate of a sized transistor, then the second transistor will have an equal current flowing between its drain/source. According to another aspect of the present invention, the object of the present invention can also be achieved by a plurality of drivers for a 7 201024949 jzyoopii light-emitting diode, the driver comprising the above-mentioned first point of view for sinking current to drive a plurality of light-emitting diodes. The current tank circuit of the polar body. In a standard complementary metal oxide semiconductor (CMOS) process, the circuit described above is suitable for implementation in the form of an integrated circuit. The above described features and advantages of the present invention will become more apparent and obvious. [Embodiment] An embodiment of a current tank circuit will be described below with reference to FIG. This current sink circuit 200 includes a reference input 201. This reference input terminal 201 is connected to the drain and gate of the first reference transistor 203. The first reference transistor 203 is an n-type transistor in the form of a diode connection. The source of the first reference transistor 203 is grounded. Current tank circuit 200 further includes a plurality of switching inputs 207_1 through 207_4. Although shown here as four switching inputs, it is worth noting that any number of switching inputs can be provided depending on the number of current slot groups to be switched. The first switching input terminal 207_1 is connected to the gate of the first n-type transistor (cascade switching element) 211_1 of the first group 209_1. The drain of the first n-type transistor 211-1 of the first group 2〇9_1 is connected to the sum node 215. The source of the first n-type transistor 211-1 of the first group 209_1 is connected to the drain of the second n-type transistor 213_1 (current sink) of the first group 209_1. The source of the second n-type transistor 213 j of the first group 209-1 is grounded. The gate of the second n-type transistor 213" of the 2010/24 DJ/yeDpif jin ΐΓΙ 连接 is connected to the gate of the β reference transistor 203. The second switching input terminal 2 (2 is connected to the pair of f-joined first n-type transistors (cascade switching elements) 211 2 of the second group 2〇9 2
L第二群ί 2。9—2的這對第一 η型電晶體211—2—的汲極 連接至總和_ 215 1二群組2()9—2的這對第二η型電 晶體211_2之每個源極連接至第二群組2〇9一2 #一對並行 連接的第二η型電晶艘（電流槽）213—2的各別汲極。第 二群組209—2 #這對第二η型電晶體213_2的源極接地。 第二群組209_2的這對第二η型電晶體213一2的閘極連接 至η型參考電晶體2〇3的閘極。 ，第二切換輸入端207一3連接至第三群組2〇9_3的四個 並行連接的第- η型電晶體（串級開關元件）2U」的開 極。第二群組209一3的這四個第一 電晶體2η—3的汲 極連接至總和節點215。第三群組2〇9__3的這四個第一 n 型電晶體211_2中的每個第一 η型電晶體211_3的源極連 接至第二群組209_2的四個並行連接的第電晶體（電 流槽）213_3的各別汲極。第三群組2〇9-3的這四個第二^ 型電晶體213_3的源極接地。第三群組2〇9一3的這四個第 二η型電晶體213一3的閘極連接至n型參考電晶體2〇3的 閘極。 第四切換輸入端207一4連接至第四群組2〇9_4的八個 並行連接的第一 η型電晶體（串級開關元件）211一4的閘 極。由八個並行連接的第一 η型電晶體（開關）211一4與 9 201024949 ^ζ^δ^ριι 第二η型電晶體（電流槽）213—4組成的第四群組1〇9_4 按照先前群組的相同方式來連接。 必要時’額外的群組將包含16、32.....211.1個並行 連接的開關與電流槽’也就是說，在群組中，開關與電流 槽對（pairs)是以二進位方式來並聯起來。 總和節點215連接至輸入端217，而此輸入端217則 連接至發光二極體的陰極或由多個發光二極體所組成的發 光二極體串中的最後一個發光二極體的陰極。 本發明之一實施例所述之電流參考電路繪示於圖3 中。此電流參考電路300包括用以產生能帶隙參考電壓 (bandgap reference voltage)的裝置 301。此產生裝置 3〇1 之輸出連接至比較器305 (諸如運算放大器）的第一輸入 端303。此比較器305之輸出端3〇7連接至η型整定電晶 體309的閘極。此η型整定電晶體309的源極連接至電阻 為RSET的整定電阻器311的第一端。此整定電阻器 的第二端接地。整定電阻器311的第一端連接至比較器3〇5 的第二輸入端313 ’形成一個閉合回館環路配置^ η型整定 電晶體309的汲極連接至第二參考電晶體315。此第二參 考電晶體315是一個二極體連接形式的ρ型電晶體。第二 參考電晶體315的源極連接至共用電壓軌（v〇ltage rail) 317。第二參考電晶體315的閘極連接至多個相同的p型鏡 像電晶體319_1至319一8的閘極。雖然此處繪示為八個p 型鏡像電晶體，但是值得注意的是，根據電路的需要，可 使用任何數量的p型鏡像電晶體。這些p型鏡像電晶體 201024949 jzy»5pif 319一1至319_8的每個源極連接至共用電壓執3i7。這些p 型鏡像電晶體319—1至319—8的每個汲極連接至各別輸出 端 321_1 至 321—8。 操作時，電流參考電路3〇〇產生§路實暂t相蓉的| 考電流在輸出端321—i至321_8之每個輸出端上給每個電 流槽電路200，連接在對應的電流槽電路2〇〇的參考電流 輸入端201。這些參考電流是由第二參考電晶體315與多 ❿個p型鏡像電晶體319」至319一8之每個所構成的每個電 流鏡（current mirror)來產生。以致於每個輸出端32ij 至321一8輸出的參考電流與流經第二參考電晶體、整 定電晶體309以及整定電阻器311的電流（即，v电㈣ /RSET)相對應。 此電流槽電路的操作依賴於以下的前提條件：在相同 的碎片上有相同的取向且具有相同端電壓的相同尺寸的電 晶體會有相同的電流流過。所以，藉由整定流經第二參考 、電晶體315的規定電流，且將第二參考電晶體315的閘極 攀 連接至其他相同尺寸的鏡像電晶體319」至319—8的閘 極，鏡像電晶體319一 1至319_8就能使其汲極之間的相等 電流流向其各別輸出端321_1至321_8 » 此電流是用一個功能區塊來限定，且分配給多電晶體 輪出區塊。與透過設計來限定電流的其他方案相同的是， 不對輪出電流進行取樣或測量。當實施這些電流鏡裝置以 ，對其進行全面整合時’這些電流鏡裝置連接至電路塾 uit pad )，然後必須併入適當的靜電放電 11 201024949 ozyo^pif (Electro-Static Discharge, ESD)保護。 參考電路300包括供應給外接的1%公差電阻器311 的能帶隙電壓。供應給此電阻器311的電流為V /RSET。相等的電流流經第二參考電晶體315。這限定了 8 個鏡像電晶體319_1至319_8的閘極至源極電壓（gate to source voltage )，當這些鏡像電晶體319_1至319_8連接 至不同的電流槽，進而連接至驅動器時，就會再生出與第 二參考電晶體315相等的電流。 圖2之示意圖繪示為驅動器區塊的一部分。來自電流 © 參考電路300中之鏡像電晶體319_1至319_8之一的參考 電流流到電流槽電路200之輸入端201上，進而流到第一 參考電晶體203上。這就構成了供所有電流槽所用的《單 位電流”參考。由於電流槽是以二進位方式來連接成群組 配置，所以輸出的槽電流是所有“接通，，電流槽的電流總 和。這使得輸出電流等於“單位電流，，參考的乘積，而此 乘積則取決於驅動器中的電流槽數量。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 M 本發明之精神和範圍内’當可作些許之更動與潤飾，故本 發明之保護·當視後附之申請專利範_界定者為準。 【圖式簡單說明】 圖1是習知的一種電流槽的電路示意圖。 圖2是依照本發明之-實施例的—種電流槽電路 路示意圖。 12 201024949 W5Dplf 圖3是依照本發明之一實施例的一種電流參考電路的 電路示意圖。 【主要元件符號說明】 100、200 :電流槽電路 101 :參考電壓 103、305 :比較器 105、211_1 〜211_4、213_1 〜213_4、319—1 〜319_8 : _ 電晶體 107:感測電阻器 109、321_1 〜321_8 :輸出端 201 :參考輸入端 203、315 :參考電晶體 207_1〜207_4 :切換輸入端 209_1 〜209_4 :群組 215 :總和節點 217 :輸入端 參 300:電流參考電路 301 :能帶隙參考電壓產生裝置 303、313 :比較器輸入端 307 ··比較器輸出端 309 :整定電晶體 311 :整定電阻器 317 :共用電壓軌 13L the second group ί 2. 9-2 of the pair of first n-type transistors 211-2 - the drain is connected to the sum _ 215 1 two groups 2 () 9 - 2 of the pair of second n-type transistors Each source of 211_2 is connected to a second group 2〇9-2 2 pair of parallel poles of a second n-type electric crystallizer (current slot) 211-2 connected in parallel. The second group 209-2 # is connected to the source of the second n-type transistor 213_2. The gates of the pair of second n-type transistors 213-2 of the second group 209_2 are connected to the gates of the n-type reference transistor 2〇3. The second switching input terminal 207-3 is connected to the opening of the four parallel-connected n-th type transistors (cascade switching elements) 2U" of the third group 2〇9_3. The anodes of the four first transistors 2n-3 of the second group 209-3 are connected to the sum node 215. The source of each of the first n-type transistors 211_3 of the third group 2〇9__3 is connected to the four parallel connected transistors of the second group 209_2 (current Slot) 213_3 respective bungee. The sources of the four second transistor 213_3 of the third group 2〇9-3 are grounded. The gates of the four second n-type transistors 213-3 of the third group 2〇9-3 are connected to the gates of the n-type reference transistor 2〇3. The fourth switching input terminal 207 - 4 is connected to the gates of the eight parallel-connected first n-type transistors (cascade switching elements) 211 - 4 of the fourth group 2 〇 9_4. The fourth group 1〇9_4 consisting of eight parallel connected first n-type transistors (switches) 211-4 and 9 201024949 ^ζ^δ^ριι second n-type transistors (current slots) 213-4 Connected in the same way as the previous group. If necessary, the extra group will contain 16, 32.....211.1 parallel-connected switches and current slots. That is, in the group, the switches and current-slot pairs are in binary mode. Connected in parallel. The summing node 215 is connected to the input terminal 217, which is connected to the cathode of the light-emitting diode or the cathode of the last one of the light-emitting diodes composed of a plurality of light-emitting diodes. A current reference circuit according to an embodiment of the present invention is shown in FIG. This current reference circuit 300 includes means 301 for generating a bandgap reference voltage. The output of this generating device 3〇1 is coupled to a first input 303 of a comparator 305, such as an operational amplifier. The output terminal 3 of the comparator 305 is connected to the gate of the n-type setting transistor 309. The source of the n-type set transistor 309 is connected to the first end of the set resistor 311 having a resistance of RSET. The second end of the tuning resistor is grounded. The first end of the tuning resistor 311 is coupled to the second input 313' of the comparator 3〇5 to form a closed loop configuration. The drain of the n-type tuning transistor 309 is coupled to the second reference transistor 315. This second reference transistor 315 is a p-type transistor in the form of a diode connection. The source of the second reference transistor 315 is coupled to a common voltage rail (317). The gate of the second reference transistor 315 is connected to the gates of a plurality of identical p-type mirror transistors 319_1 to 319-8. Although illustrated herein as eight p-type mirrored transistors, it is worth noting that any number of p-type mirrored transistors can be used depending on the needs of the circuit. These p-type mirror transistors 201024949 jzy»5pif 319-1 to 319_8 each source is connected to the common voltage hold 3i7. Each of these p-type mirror transistors 317-1 to 319-8 is connected to respective output terminals 321_1 to 321-8. In operation, the current reference circuit 3 〇〇 generates a real-time t-phase | test current is applied to each of the output terminals 321 - i to 321 - 8 to each current slot circuit 200, connected to the corresponding current slot circuit 2〇〇 reference current input terminal 201. These reference currents are generated by each current mirror formed by the second reference transistor 315 and each of the plurality of p-type mirror transistors 319" to 319-8. The reference current output from each of the output terminals 32ij to 321-8 corresponds to the current flowing through the second reference transistor, the tuning transistor 309, and the setting resistor 311 (i.e., v (4) / RSET). The operation of this current sink circuit relies on the precondition that the same size of transistors having the same orientation on the same chip will have the same current flowing through the same size of the same terminal voltage. Therefore, by setting the prescribed current flowing through the second reference, the transistor 315, and connecting the gate of the second reference transistor 315 to the gates of other mirrored transistors 319" to 319-8 of the same size, mirroring The transistors 319-1 to 319_8 can cause their equal currents between the drains to flow to their respective output terminals 321_1 to 321_8. » This current is defined by a functional block and is assigned to the poly transistor wheel-out block. As with other schemes that limit the current through design, the wheel current is not sampled or measured. When these current mirror devices are implemented to fully integrate them, these current mirror devices are connected to the circuit pad and must be incorporated into an appropriate electrostatic discharge 11 201024949 ozyo^pif (Electro-Static Discharge, ESD) protection. The reference circuit 300 includes an energy bandgap voltage supplied to an external 1% tolerance resistor 311. The current supplied to this resistor 311 is V / RSET. Equal current flows through the second reference transistor 315. This defines the gate to source voltage of the eight mirrored transistors 319_1 through 319_8, which are regenerated when these mirrored transistors 319_1 through 319_8 are connected to different current slots and then connected to the driver. A current equal to the second reference transistor 315. The schematic of Figure 2 is shown as part of the driver block. The reference current from one of the mirrored transistors 319_1 to 319_8 in the current © reference circuit 300 flows to the input terminal 201 of the current tank circuit 200, and then flows to the first reference transistor 203. This constitutes the “unit current” reference for all current sinks. Since the current slots are connected in a binary configuration in a binary configuration, the output slot current is the sum of all “on, current sink currents. This causes the output current to be equal to the product of the unit current, the reference, and this product depends on the number of current slots in the driver. Although the invention has been disclosed above by way of example, it is not intended to limit the invention, any technical field Those of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the protection of the present invention shall be subject to the definition of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic circuit diagram of a conventional current sink. Fig. 2 is a schematic diagram of a current tank circuit in accordance with an embodiment of the present invention. 12 201024949 W5Dplf FIG. 3 is a diagram of an embodiment of the present invention. Schematic diagram of the current reference circuit. [Main component symbol description] 100, 200: Current tank circuit 101: Reference voltage 103, 305: Comparators 105, 211_1 211 211_4, 213_1 ～ 213_4, 319-1 to 319_8: _ transistor 107 : sense resistors 109, 321_1 ~ 321_8: output terminal 201: reference input terminals 203, 315: reference transistors 207_1 ~ 207_4: switching input terminals 209_1 ~ 209_4: group 2 15: sum node 217: input terminal reference 300: current reference circuit 301: band gap reference voltage generating means 303, 313: comparator input terminal 307 · comparator output terminal 309: tuning transistor 311: tuning resistor 317: Shared voltage rail 13