JP2008218825A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the chip area of an integrated circuit small by connecting other-polarity electrodes of a plurality of first diodes to an electrode of one of second diodes which has the same polarity with the other-polarity electrodes of the plurality of first diodes. <P>SOLUTION: The integrated circuit has a plurality of output terminals, a plurality of transistors such that one of two electrodes different from a control electrode is connected to the plurality of respective output terminals, the plurality of first diodes 31 to 35 which have one-polarity electrodes connected to the plurality of respective output terminals, and the one or more second diodes 40 less than the plurality of first diodes, the other-polarity electrodes of the plurality of first diodes being connected to the electrode of one of the second diode which has the same polarity with the other-polarity electrodes of the plurality of first diodes. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to integrated circuits.

  One cause of failure of integrated circuits is electrostatic breakdown. The electrostatic breakdown occurs when an external object having a high potential, such as a person or a device in a chip assembly line, contacts or approaches the input / output terminal of the chip, and the potential of the chip terminal changes greatly. In order to prevent this electrostatic breakdown, the integrated circuit is provided with an ESD (Electro Static Discharge) protection circuit (for example, Patent Documents 1 and 2).

  In an integrated circuit, in order to protect an open drain output MOS (Metal Oxide Semiconductor) transistor used for signal level shift and LED (Light Emitting Diode) driving, an ESD protection circuit as shown in FIG. 3 is generally used. It is used. The ESD protection circuit in FIG. 3 includes diodes 212 and 213 having the same polarity connected between the output terminal and the power supply Vdd, and a diode 214 connected between the output terminal and the ground GND.

A diode connected between the output terminal and the power supply Vdd and having the same polarity (see, for example, Patent Document 3) is for preventing the output terminal from rising too much above the power supply Vdd due to ESD. It is. The diode connected between the output terminal and the ground GND is for preventing the output terminal from being greatly lowered from the ground GND by ESD.
JP-A-8-275375 Japanese Patent Laid-Open No. 8-293583 JP 2007-28747 A

  By the way, in recent electronic devices, for example, mobile phones and in-vehicle displays tend to use a plurality of LEDs. As a result, there is a need for an integrated circuit with multiple open drain outputs that can drive multiple LEDs.

  However, for example, when the ESD protection circuit shown in FIG. 3 is applied to realize an integrated circuit having a plurality of open drain outputs, a pair of diodes (diodes 212 to 214) are required for each output terminal, and the chip area is large. To increase. Further, for an integrated circuit that requires a higher withstand voltage, such as for in-vehicle use, there is a problem that the chip area becomes large because it is necessary to increase the layout area of the diode itself constituting the protection circuit.

  The present invention has been made in view of the above problems, and an object thereof is to reduce a chip area in an integrated circuit.

  In order to achieve the above object, an integrated circuit of the present invention includes a plurality of output terminals and a plurality of transistors in which one of two electrodes different from the control electrode is connected to each of the plurality of output terminals; A plurality of first diodes having one polarity electrode connected to each of the plurality of output terminals, and one or more second diodes fewer than the plurality of first diodes; Each of the other polar electrodes is connected to one of the second diodes and the same polarity as the other polar electrode of the plurality of first diodes.

  According to the present invention, the chip area of an integrated circuit can be reduced.

At least the following matters will become apparent from the description of this specification and the accompanying drawings.
FIG. 1 is a diagram showing a configuration of an integrated circuit according to an embodiment of the present invention. The integrated circuit includes NMOSs 11 to 15, diodes 21 to 25, 31 to 35, 40, output terminals OUT1 to OUT5, a power supply Vdd, and a ground GND.

  The NMOSs 11 to 15 have source electrodes connected to GND and drain electrodes connected to output terminals OUT1 to OUT5, respectively. A control voltage capable of driving an external load connected to the output terminals OUT1 to OUT5 is applied to the gate electrodes of the NMOSs 11 to 15.

Each of the diodes 21 to 25 has an anode connected to GND and a cathode connected to the output terminals OUT1 to OUT5.
Each of the diodes 31 to 35 has an anode connected to the output terminals OUT <b> 1 to OUT <b> 5 and a cathode connected to the cathode of the diode 40.
The diode 40 has an anode connected to the power supply Vdd and a cathode connected to the cathodes of the diodes 31 to 35.

  The output terminals OUT1 to OUT5 are connected to the drain electrodes of the NMOSs 11 to 15, the cathodes of the diodes 21 to 25, and the anodes of the diodes 31 to 35. Further, external loads such as LEDs and resistors are connected to the plurality of output terminals.

The power supply Vdd is connected to the anode of the diode 40 and corresponds to the positive power supply in the integrated circuit.
The ground GND is connected to the source electrodes of the NMOSs 11 to 15 and the anodes of the diodes 21 to 25, and maintains 0 V (zero volts) which is a reference potential in the integrated circuit.

  The diodes 31 to 35 correspond to the first diode of the present invention, and the diode 40 corresponds to the second diode of the present invention.

  The operation of the embodiment of the integrated circuit shown in FIG. 1 will now be described. When ESD occurs such that the potential of the output terminals OUT1 to OUT5 decreases, the diodes 21 to 25 clamp the potential of the output terminals OUT1 to OUT5 at a potential lower than the ground GND by the forward voltage of the diodes 21 to 25, and output This prevents the potential of the terminals OUT1 to OUT5 from greatly decreasing from the ground GND. On the other hand, when ESD occurs so that the potentials of the output terminals OUT1 to OUT5 rise, the diodes 31 to 35 and 40 change the potentials of the output terminals OUT1 to OUT5 from the power supply Vdd to the forward voltages of the diodes 31 to 35 and the diode 40. The output terminal OUT1 to OUT5 is clamped at a potential higher by the sum of the reverse voltage and the output terminals OUT1 to OUT5 are prevented from rising more than the power supply Vdd. Therefore, the output terminals OUT1 to OUT5 are not greatly deviated from the potentials of the power supply Vdd and the ground GND, and the NMOSs 11 to 15 connected to the output terminals OUT1 to OUT5 are protected from ESD. Even when the diodes 31 to 35 are directly connected to the power supply Vdd, it is possible to obtain an effect of preventing the output terminal from being greatly increased above the power supply Vdd. However, the presence of the diode 40 prevents current from flowing from the output terminals OUT1 to OUT5 into the integrated circuit even when a voltage is applied to the output terminals OUT1 to OUT5 before the power supply Vdd rises. I can do things.

  As shown in FIG. 1, in contrast to the five diodes 31 to 35 whose anodes are connected to the output terminals OUT1 to OUT5, the diode whose anode is connected to the power supply Vdd is only one of the diodes 40. Compared with the case where a pair of diodes (diodes 212 and 213 in FIG. 3) are connected between the power supply and the power supply, the number of diodes can be reduced by four. As a result, the chip area can be reduced. In particular, in an in-vehicle integrated circuit that requires a high ESD withstand voltage, since the layout area of one diode is generally the same as that of one terminal pad, reducing the number of diodes greatly contributes to a reduction in chip area. .

  Although FIG. 1 shows an example in which only one diode 40 is used as the diode connected to the power supply Vdd, for example, two diodes are used instead of the diode 40, and the cathode of one of the diodes is used. Even if the cathodes of the diodes 31 to 33 and the cathode of the other diode are connected to the cathodes of the diodes 34 and 35, a pair of diodes (diodes 212 and 213 in FIG. 3) are connected between the output terminals and the power source. In this case, the chip area becomes smaller.

  However, in the case where a plurality of diodes connected to the power supply Vdd are used and the case where one diode is used, if the area of the diode is the same, the chip area can be made smaller in one case.

  In FIG. 1, the anode of the diode 40 is connected to the power supply Vdd, and the anodes of the diodes 31 to 35 are connected to the output terminals OUT1 to OUT5. However, the cathode of the diode 40 is connected to the power supply Vdd and the diodes 31 to 31 are connected to the output terminals OUT1 to OUT5. The same effect can be obtained by connecting the 35 cathodes and connecting the anodes of the diode 40 and the diodes 31 to 35 to each other.

  FIG. 2 is a diagram showing an embodiment of an integrated circuit for driving an LED to which the present invention is applied. The integrated circuit includes NMOSs 51 to 53, diodes 61 to 63, 71 to 73, 80, operational amplifiers 91 to 93, resistors R1 to R6, bias current sources Ib1 to Ib3, output terminals OUT11 to OUT13, a power supply Vdd1, and a ground GND. Consists of. The resistance values of the resistors R1 to R6 are R1 to R6, and the current values of the bias current sources Ib1 to Ib3 are Ib1 to Ib3, respectively.

  The drain electrodes of the NMOSs 51 to 53 are connected to the output terminals OUT11 to OUT13, the gate electrode is connected to the outputs of the operational amplifiers 91 to 93, and the source electrode is connected to one end of each of the resistors R2, R4, R6 and the inverting input of the operational amplifiers 91 to 93. ing. Here, the bulk electrodes of the NMOSs 51 to 53 are connected to the source electrodes of the NMOSs 51 to 53, respectively, but may be connected to the ground GND depending on the chip manufacturing process.

The diodes 61 to 63 have cathodes connected to the output terminals OUT11 to OUT13 and anodes connected to the ground GND, respectively.
The diodes 71 to 73 have anodes connected to the output terminals OUT11 to OUT13 and cathodes connected to the cathode of the diode 80, respectively.
The diode 80 has an anode connected to the power supply Vdd1 and a cathode connected to the cathodes of the diodes 71 to 73.

  The operational amplifiers 91 to 93 output to the gate electrodes of the NMOSs 51 to 53, the inverting input is one end of the resistors R2, R4, and R6 and the source electrode of the NMOS 51 to 53, and the non-inverting input is one end of the bias current sources Ib1 to Ib3 and the resistor It is connected to one end of each of R1, R3 and R5.

One ends of the resistors R1, R3, and R5 are connected to one ends of the bias current sources Ib1 to Ib3, the non-inverting inputs of the operational amplifiers 91 to 93, and the other ends connected to the ground GND.
One ends of the resistors R2, R4, and R6 are connected to the source electrodes of the NMOSs 51 to 53 and the inverting inputs of the operational amplifiers 91 to 93, and the other ends are connected to the ground GND.
One end of the bias current sources Ib1 to Ib3 is connected to the power supply Vdd1, and the other end is connected to the non-inverting input of the operational amplifiers 91 to 93 and one end of the resistors R1, R3, and R5.

  The output terminals OUT11 to OUT13 are connected to the drain electrodes of the NMOSs 51 to 53, the cathodes of the diodes 61 to 63, and the anodes of the diodes 71 to 73, respectively. Further, the output terminals OUT11 to OUT13 are connected to the LEDs 97 to 99, which are external loads supplied with power from the external power supply Vdd2 outside the chip.

The power supply Vdd1 is connected to the anode of the diode 80 and one end of the bias current sources Ib1 to Ib3, and corresponds to the positive power supply in the integrated circuit.
The ground GND is connected to one end of the resistors R1 to R6 and the anode of the diodes 61 to 63, and maintains 0V (zero volt) which is a reference potential in the integrated circuit.

  The diodes 71 to 73 correspond to the first diode of the present invention, and the diode 80 corresponds to the second diode of the present invention.

  Next, the operation of the circuit for driving the LED shown in FIG. 2 will be described. In FIG. 2, the three LEDs 97 to 99 are configured to be driven, and the operation of the circuits for driving the respective LEDs is the same. Therefore, only the operation of the circuit for driving the LEDs 97 will be described. The circuit that drives the LED 97 includes an NMOS 51, diodes 61, 71, and 80, an operational amplifier 91, resistors R1 and R2, a bias current source Ib1, an output terminal OUT11, a power supply Vdd1, and a ground GND. As already mentioned.

  When the current from the bias current source Ib1 flows through the resistor R1, a voltage of Ib1 × R1 is applied to the non-inverting input of the operational amplifier 91. Since the operational amplifier 91 is negatively fed back, the operational amplifier 91 controls the voltage applied to the gate electrode of the NMOS 51 to determine the current flowing through the resistor R2 so that the potential of the inverting input matches Ib1 × R1. Therefore, the current flowing through the resistor R2 is (Ib1 × R1) / R2, and the LED1 is driven by the current flowing through the resistor R2. Note that by changing the current value of the bias current source, the current value for driving the LED 97 is changed, and the luminance of the LED 97 can be adjusted.

  The roles of the diodes 61 to 63 correspond to the diodes 21 to 25 in FIG. 1, the roles of the diodes 71 to 73 correspond to the diodes 31 to 35 in FIG. 1, and the role of the diode 80 corresponds to the diode 40 in FIG.

  When the circuit configuration is organized here, the circuit for driving the LED 97 includes an NMOS 51 for adjusting the current of the LED 97, a circuit 101 for driving the NMOS 51 (the driving circuit 101 includes an operational amplifier 91, resistors R1 and R2, and a bias current source Ib1). It comprises diodes 61, 71, 80 that protect the NMOS 51. Further, comparing the circuit for driving the LED 97 with the circuits for driving the LEDs 98 and 99, the NMOS 51 has NMOSs 52 and 53, the driving circuit 101 has driving circuits 102 and 103, and the diode 61 has diodes 62 and 63. The diode 71 corresponds to the diodes 72 and 73, respectively. The LEDs 98 and 99 are also driven in the same manner as the LED 97.

  The configuration and operation of the embodiment shown in FIG. 2 have been described. As shown in FIG. 2, the diode connected between the power supply Vdd1 and the three output terminals OUT11 to OUT13 is the diode 80 and the diode at OUT11, respectively. 71 and OUT12 are the diode 80 and the diode 72, and OUT13 is the diode 80 and the diode 73. This is because the number of diodes can be reduced compared to the case where a pair of diodes (corresponding to the diodes 212 and 213 in FIG. 3) are connected between the power supply Vdd1 and the three output terminals OUT11 to OUT13, respectively. The chip area can be reduced.

  FIG. 2 shows an embodiment in which three LEDs are driven. For example, in recent mobile phones, white LEDs are used as backlights for displays and keyboards, and RGB output LEDs are used for camera flashes. More LEDs may be driven. Even when many LEDs are driven as described above, by applying this embodiment, each of the output terminals to which the LEDs are connected and the diodes facing each other connected to the power source of the integrated circuit are connected to the power source. Since the number of diodes can be reduced, the chip area can be reduced.

  The embodiment of the present invention has been described above. As described above, FIG. 1 shows an example in which only one diode 40 is used as the diode connected to the power supply Vdd. For example, two diodes are used instead of the diode 40, and one of the diodes is used. Are connected to the cathodes of the diodes 31 to 33 and the cathode of the other diode to the cathodes of the diodes 34 and 35, a pair of diodes (diodes 212 and 213 in FIG. 3) are connected between the output terminals and the power source. The chip area is smaller than that of the case of connecting the same.

  In FIG. 1, even when ESD occurs so that the potential of the output terminals OUT1 to OUT5 rises by connecting the anode of the diode 40 to the power supply Vdd, the potentials of the output terminals OUT1 to OUT5 are changed from the power supply Vdd. Clamping is performed at a potential that is higher by the sum of the forward voltage of the diodes 31 to 35 and the reverse voltage of the diode 40, and the output terminals OUT1 to OUT5 are prevented from rising more than the power supply Vdd.

  Further, as shown in FIG. 1, when one diode 40 having a cathode connected thereto is used with respect to the cathodes of the diodes 31 to 35 having anodes connected to the output terminals OUT1 to OUT5, the output terminals are connected to the power supply. As compared with the case where a pair of diodes (corresponding to the diodes 212 and 213 in FIG. 3) are connected between the two, the number of diodes can be reduced by four, and the chip area can be reduced.

  The above-described embodiments are for facilitating understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed / improved without departing from the spirit thereof, and the present invention includes equivalents thereof.

  For example, in order to limit the current flowing through the diodes 21 to 25, 31 to 35 and 40 in FIG. 1, the output terminals OUT1 to OUT5, the cathode electrodes of the diodes 21 to 25, the anode electrodes of the diodes 31 to 35, the NMOSs 11 to The same effect can be obtained in a circuit in which a resistor is inserted between the node connected to the 15 drain electrodes. It is also possible to use a PMOS or bipolar transistor instead of NMOS, or to apply to a circuit in which the source electrode is connected to the output terminal instead of the drain electrode of the MOS transistor.

It is a figure which shows the structure of the integrated circuit which is embodiment of this invention. It is a figure which shows embodiment of the integrated circuit which drives LED to which this invention is applied. It is a figure which shows the structural example of an ESD protection circuit.

Explanation of symbols

11-15, 51-53, 211 NMOS transistors 21-25, 31-35 Diodes 40, 61-63, 71-73, 80 Diodes 212-214 Diodes OUT1-OUT5 Output terminals OUT11-OUT13 Output terminals 91-93 Operational amplifier 97 ~ 99 LED
R1-R6 Resistors Ib1-Ib3 Bias current Vdd, Vdd1, Vdd2 Power supply GND Ground

Claims (3)

Multiple output terminals,
A plurality of transistors in which one of the two electrodes different from the control electrode is connected to each of the plurality of output terminals;
A plurality of first diodes having one polarity electrode connected to each of the plurality of output terminals;
One or more second diodes less than the plurality of first diodes;
With
Each of the electrodes of the other polarity of the plurality of first diodes is connected to one of the second diodes, the electrode having the same polarity as the electrode of the other polarity of the plurality of first diodes;
An integrated circuit characterized by. An electrode having the same polarity as that of the first diode of the second diode is an electrode connected to a power source;
An integrated circuit characterized by. An integrated circuit according to claim 1 or claim 2, wherein
The number of said 2nd diodes is one, The integrated circuit characterized by the above-mentioned.

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