201023520 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種脈波寬度調變(PWM)控制器，特 別是關於一種高效能PWM控制器，其可在電源轉換應用 中進行電源管理(power management)。 【先前技術】 要說明本案的先前技術’PWM控制器與一般電源轉換 應用之關係應先介紹。請參照圖1，其顯示一含PWM控 制器之典型電源轉換應用之架構。如圖1所示，該架構實 •現了一返馳式電源轉換器，其至少包括一PWM控制器 100、一輸入整流及滤波器1〇1、一主變壓器1〇2、一輸出 整流及濾波器103、一回授電路1〇4及一 NM0S電晶體 105。 在該架構中，該PWM控制器1〇〇係用以依一回授信 號Vfb產生一脈波信號Sp。 該輸入整流及濾波器101係用以依一 AC輸入電源產 生一第一 DC電壓。 該主變壓器1〇2和輸出整流及濾波器1〇3係用以將該 轚第一 DC電壓轉換成一 DC輸出電壓V〇。 该回授電路104係用以依該DC輸出電壓V〇產生該回 授信號VFB。 該NM0S電晶體105係用以依該脈波信號sP控制該 主變壓器102之能量轉換。 經由該PWM控制器1〇〇產生的脈波信號sP對該 NM0S電晶體105施行週期性的導通/斷路切換，該輸入 電源即可經由該主變壓器102轉換至輸出。該PWM控制 器1〇〇之操作原理將依圖2說明。圖2係一習知卩〜1\/1控 5 201023520 制器之電路圖，如圖所示’該電路至少包括：一鋸齒波信號 產生器200、一觸發信號產生器201、一閂鎖器202、一 反閘203、一反閘204、一重置產生器205及一輸出級206。 在該電路中’該鋸齒波信號產生器200係用以依一 ICKB信號及一 ICK信號產生一鋸齒波信號vSAW，其具有 一電流源丨up、一開關SWUP、一電容CT、一開關SWDN及 一電流源丨dn。當該開關SWUP導通，流入該電容（^之電 流源丨up會致使該鑛齒波信號VSAW線性上升；當該開關 SWDN導通，流出該電容CT之電流源丨⑽會致使該鑛齒波 _ 信號VsAW線性下降。 該觸發信號產生器201係用以依該鋸齒波信號vSAW 分別與一高位準VH及一低位準VL之比較結果產生一對觸 發信號，以觸發該閂鎖器202。 該閂鎖器202係用以依該對觸發信號產生一 CKB信 说及一 CK j吕號’其中該CKB信號與該CK信號互補。 該反閘203係用以依該CKB信號產生一 ICKB信號； 該反閘204係用以依該CK信號產生一 ICK信號。 _ s亥重置產生器205係用以依一線性上升信號\/s及一 與該回授信號VFB有關之V+信號產生一 RESET信號。當 該RESET信號為低邏輯電位，該輸出級206之脈波信號 Sp會被拉低至低邏輯電位以關閉該NMOS電晶體1〇5(示 於圖1中）。 該輸出級206係用以依該CK信號及該RESET信號 產生該脈波信號SP。關於該鋸齒波信號VSAW、CKB信號、 ▽+信號、線性上升信號Vs與脈波信號SP彼此間之時序關 係睛參照圖3。如圖3所示’因該線性上升期間與線性下 降期間均為固定，故該脈波信號SP之週期為固定。如此， 6 201023520 該NMOS電晶體1〇5(示於圖1中）i ;ϊίΐ;载狀況而以固定頻率切換:、ΐ: ’此0設計將浪費許多功率而背離節能之需求。 給帽⑽?需提供一高效能之口则控制器，其可調變 【發明内容】 之—目的係提供—種具有高效能電源管理機制 ❹應用之功^器’其可於輕載或空載時，降低一電源轉換 ㈣i發r之另—目的係進—步提供—種高效能之pwm ‘一二_/、可依—模式選擇信號而卫作於-第-模式或- 示一供式。 批制ί發，之另—目的係進—步提供—種高效能之pwm ，其具有—鑛齒波信號產生器，可於該第一模式產 骑了 信號或於該第二模式產生—第二鑛齒波信 二二/、ΐ,该第一鋸齒波信號具有一第一線性上升期間及 鬱一線性下降期間；該第二鑛齒波信號具有一第二線性 上升期間及一第二線性下降期間。 ^發明之所以能降低PWM控制器相關電源轉換應用 輕載或空載功耗，乃基於其鋸齒波信號產生器之設計， 亦即其新穎之鋸齒波信號產生器可於該第一模式產生一第 鋸齒波信號或於該第二模式產生一第二鋸齒波信號，其 :該等PWM控制器相關電源轉換應用可為AC/DC、 DC/DC、AC/AC 或 DC/AC。 本發明據此提出一高效能PWM控制器，用以在該等 電源轉換應用中進行電源管理。該高效能{3*1^控制器可 201023520 操作於該第一模式，☆丨 該第二模式，賴式，或操作於 |-線性下降期間;該;上:期間及-升期間及—第二線性下降期括了第二線性上 於該第-雜下^^ 1，且鄉二雜下降期間亦長 該第一線d -線性上升期間加上 上升期間加上該第二線以=， 其長於對應期ff絲婦能模式， 性下降_長於該第—線^下“二獨’且該第二線 及其=，步“本發明之結構、特徵 【實施方式】；較佳具體實施例之詳細說明如后。 ⑩ 在一切換電路中，其所含像電咸、At- $態功耗，乃隨_頻率上升而增力,mm 態功耗Pd可表為Pd=CTH2，甘如電Ct之動 VDD為跨於該電容之最大龍， 控制器職切: 切換職，將會消耗許多: 列各實施财詳細說明。 ，、鶴方式將於下 201023520 請參照圖5，其繪示本案一較佳實施例之ρ^Μ控制 器之方塊圖；如圖5所示，本發明之PWM控制器包&一 鋸齒波信號產生器500及一脈波產生器。 其中，該鋸齒波信號產生器500係用以依一模式選擇 信號sM0DE產生一對應之鋸齒波信號Vsaw，其包含:一定電 流源501、一定電流源502、一電壓至電流轉換器5〇3、 一電壓至電流轉換器504、一開關505、一開關5〇6、一 開關507、一開關508及一電容5〇9。 該疋電流源501係用以產生一定電流|up。 該定電流源502係用以產生一定電流|DN。 該電壓至電流轉換器503係用以依一回授信號vFB產 生一電流丨UPA。 該電壓至電流轉換器504係用以依一回授信號Vfb產 生一電流丨DNA。 該開關505係用以依賴式選擇信號3瞧連接該定 電流源501與該電壓至電流轉換器5〇4。當Sm〇de指示正 常模式’該開關505即斷路；當S_指示節能模式，該 開關505即導通。 該開關506係用以依賴式選擇信號s_連接該定 電流源與該電壓至電流轉換器5Q3。當s_e指示正 常模式’該開關506即斷路；當S_E指示節能模式，該 開關506即導通。 該開關507係用以依該丨CKB信號連接該定電流源 501與該電容509。 該開關508係用以依該丨CK信號連接該定電流源502 與該電容509。 該電容509係用以藉由電流積分建立該鑛齒波信號 201023520201023520 IX. Description of the Invention: [Technical Field] The present invention relates to a pulse width modulation (PWM) controller, and more particularly to a high performance PWM controller capable of power management in a power conversion application (power management). [Prior Art] The relationship between the prior art 'PWM controller' and the general power conversion application of this case should be described first. Please refer to Figure 1, which shows the architecture of a typical power conversion application with a PWM controller. As shown in FIG. 1 , the architecture implements a flyback power converter, which includes at least a PWM controller 100, an input rectification and filter 1〇1, a main transformer 1〇2, and an output rectification and The filter 103, a feedback circuit 1〇4, and an NM0S transistor 105. In this architecture, the PWM controller 1 is configured to generate a pulse signal Sp according to a feedback signal Vfb. The input rectification and filter 101 is operative to generate a first DC voltage from an AC input source. The main transformer 1〇2 and the output rectification and filter 1〇3 are used to convert the first DC voltage into a DC output voltage V〇. The feedback circuit 104 is configured to generate the feedback signal VFB according to the DC output voltage V〇. The NMOS transistor 105 is configured to control energy conversion of the main transformer 102 in accordance with the pulse signal sP. The pulse signal sP generated by the PWM controller 1 is subjected to periodic on/off switching of the NMOS transistor 105, and the input power source can be switched to the output via the main transformer 102. The principle of operation of the PWM controller 1 will be described with reference to FIG. 2 is a circuit diagram of a conventional device of the present invention, as shown in the following figure. The circuit includes at least a sawtooth signal generator 200, a trigger signal generator 201, and a latch 202. A reverse gate 203, a reverse gate 204, a reset generator 205 and an output stage 206. In the circuit, the sawtooth signal generator 200 is configured to generate a sawtooth signal vSAW according to an ICKB signal and an ICK signal, and has a current source 丨up, a switch SWUP, a capacitor CT, a switch SWDN, and A current source 丨 dn. When the switch SWUP is turned on, flowing into the capacitor (the current source 丨up causes the ore wave signal VSAW to rise linearly; when the switch SWDN is turned on, the current source 丨(10) flowing out of the capacitor CT causes the ore tooth_signal The trigger signal generator 201 is configured to generate a pair of trigger signals according to the comparison of the sawtooth wave signal vSAW with a high level VH and a low level VL, respectively, to trigger the latch 202. The device 202 is configured to generate a CKB message and a CK j Lu number according to the pair of trigger signals, wherein the CKB signal is complementary to the CK signal. The reverse gate 203 is configured to generate an ICKB signal according to the CKB signal; The gate 204 is configured to generate an ICK signal according to the CK signal. The _ s reset generator 205 is configured to generate a RESET signal according to a linear rising signal \/s and a V+ signal related to the feedback signal VFB. When the RESET signal is at a low logic potential, the pulse signal Sp of the output stage 206 is pulled low to a low logic potential to turn off the NMOS transistor 1〇5 (shown in Figure 1). The output stage 206 is used to Generating the pulse wave signal SP according to the CK signal and the RESET signal The timing relationship between the sawtooth wave signal VSAW, the CKB signal, the ▽+ signal, the linear rising signal Vs, and the pulse wave signal SP is as shown in Fig. 3. As shown in Fig. 3, the linear rising period and the linear falling period are both Fixed, so the period of the pulse signal SP is fixed. Thus, 6 201023520 the NMOS transistor 1〇5 (shown in Figure 1) i ; ϊ ΐ ΐ; load condition at a fixed frequency switching: ΐ: 'This 0 design Will waste a lot of power and deviate from the need of energy saving. Cap (10)? Need to provide a high-performance port controller, which can be adjusted [invention] - the purpose is to provide a high-performance power management mechanism ^器's can be used for light load or no load, reduce a power conversion (four) i send r another - the purpose of the step - provide - a high-performance pwm 'one two _ /, can be based on the mode selection signal and defend In the -the - mode or - shows a supply. The batch is made, the other is the purpose of providing a high-performance pwm, which has a -tooth wave signal generator, which can be produced in the first mode. Riding a signal or generating in the second mode - the second orthodontic letter 22 / The first sawtooth wave signal has a first linear rising period and a depressed linear falling period; the second mineral tooth wave signal has a second linear rising period and a second linear falling period. It can reduce the light load or no-load power consumption of the PWM controller related power conversion application based on the design of its sawtooth signal generator, that is, its novel sawtooth signal generator can generate a sawtooth signal in the first mode. Or generating a second sawtooth signal in the second mode, wherein the PWM controller related power conversion applications can be AC/DC, DC/DC, AC/AC or DC/AC. The present invention accordingly provides a high performance PWM controller for power management in such power conversion applications. The high performance {3*1^ controller can operate the first mode in 201023520, ☆ 丨 the second mode, the Lai, or operate in the |- linear descent period; the; upper: period and - liter period and - The second linear descent period includes a second linearity in the first-different ^^1, and the second-line falling period is also longer during the first line d-linear rising period plus the rising period plus the second line to =, It is longer than the corresponding period ff silk energy mode, the degree of decline _ longer than the first line ^ "two independent" and the second line and its =, step "the structure, features of the invention [embodiment]; better implementation The detailed description of the example is as follows. 10 In a switching circuit, the power consumption of the image is salty and At-$ state, which increases with the increase of _ frequency. The power consumption Pd of mm state can be expressed as Pd=CTH2, and the VDD of the power Ct is VDD. The largest dragon across the capacitor, the controller job: Switching jobs, will consume a lot: List each implementation details. Please refer to FIG. 5, which is a block diagram of a ρ^Μ controller according to a preferred embodiment of the present invention; as shown in FIG. 5, the PWM controller package & a sawtooth wave of the present invention is shown in FIG. A signal generator 500 and a pulse generator. The sawtooth signal generator 500 is configured to generate a corresponding sawtooth wave signal Vsaw according to a mode selection signal sMODE, comprising: a constant current source 501, a constant current source 502, a voltage to current converter 5〇3, A voltage to current converter 504, a switch 505, a switch 5〇6, a switch 507, a switch 508 and a capacitor 5〇9. The 疋 current source 501 is used to generate a certain current |up. The constant current source 502 is used to generate a certain current |DN. The voltage to current converter 503 is operative to generate a current 丨UPA based on a feedback signal vFB. The voltage to current converter 504 is operative to generate a current 丨DNA based on a feedback signal Vfb. The switch 505 is used to connect the constant current source 501 and the voltage to current converter 5〇4 with a dependent selection signal 3瞧. When Sm〇de indicates the normal mode 'the switch 505 is open; when S_ indicates the power save mode, the switch 505 is turned on. The switch 506 is used to connect the constant current source to the voltage to current converter 5Q3 in a dependent selection signal s_. When s_e indicates normal mode 'the switch 506 is open; when S_E indicates the power save mode, the switch 506 is turned on. The switch 507 is configured to connect the constant current source 501 and the capacitor 509 according to the 丨CKB signal. The switch 508 is configured to connect the constant current source 502 and the capacitor 509 according to the 丨CK signal. The capacitor 509 is used to establish the ore signal by current integration 201023520
Vs AW ° f脈波產生器510係用以依該鋸齒波信號Vsaw及該 回授信號VFB產生該脈波信號Sp。 π \/在圖5中，該電壓至電流轉換器503係根據該回授信 ，vFB之一第一函數產生該電流丨υρΑ，而該電壓至電流轉換 器50=則根據該回授信號Vfb之一第二函數產生該電流 Idna。該電流丨UPA小於該電流丨叫且該電流丨dna小於該電流 ιυΡ，而該第一函數及第二函數較佳者為該回授信號Vfb之 一次多項式。 ❹ 凊參照圖6 ’其繪示本案一較佳實施例之pwM控制 器，其鋸齒波信號產生器操作於該節能模式時之電路圖。 如圖6所示，本發明之鋸齒波信號產生器包括一 pM〇s電 晶體601、一 NMOS電晶體602、一 PMOS電晶體603、 一 NMOS電晶體604、一 NMOS電晶體605、一運算放 大器 OPA606、一電阻 607、一 PMOS 電晶體 608、一 NMOS電晶體609、一 PMOS電晶體610、一 NM〇S電 晶體611、一開關612、一開關613及一電容614。 其中，該PMOS電晶體601係用以將電流丨複製到其 翬他分支。 該NMOS電晶體602係用以產生電壓vx= VFB-VGS。 該PMOS電晶體603係用以複製流經該pM〇S電晶 體601之電流卜 該NMOS電晶體604係用以產生電壓vY= VA-VGS。 該NMOS電晶體605係用以提供該電流丨之電流路 徑。 該運算放大器0PA 606係用作一壹增益(unit-gain)緩 衝器。 201023520 該電阻607具有電阻值R，係用以產生該電流 I = (Vx-VY)/R ° 該PMOS電晶體608係用以複製流經該pm〇s雷晶 體601之電流卜 該NMOS電晶體609係用以將該電流丨複製到其他分 i ° 八 該PMOS電晶體610係用以依該電流丨產生該電流 ΙυΡΑ 0 該NMOS電晶體611係用以依該電流丨產生該電流 .Idna 〇 該開關612、開關613及電容614扮演之角色與圖5 中之該開關507、開關508及電容509相同，故不在此贅 述。 、 在以上所述之較佳實施例中，該第一函數及第二函數 可變化為其他形式，例如但不限於常數函數。在常數函數 之情況下，該節能模式切換週期既長於該正常模式切換週 期且其亦為一固定之週期。 、 ⑩ 另，在包含一變壓器之電源轉換應用中，當該節能模 式之線性上升期間過長時，該變壓器可能有館和的風險。 考里此狀況，本發明之一較佳實施例之PWM控制器可進 一步包括一脈波寬度限制機制。請參照圖7，其繪示一脈 波寬度限制器700之方塊圖。如圖7所示，該脈波寬度限 制器700包括一單擊脈波產生器7〇1和一及閘7〇2。 該單擊脈波產生器701係用以依該脈波信號sp產生 一具固定脈波寬度之單擊脈波SPL 〇 該及閘702係用以依該脈波信號sp及該單擊脈波Spi_ 產生一輸出信號S0UT。經由適當設定該固定脈波寬度，將 11 201023520 可確保該些電源轉換應用之變壓器免於飽和。 本案所揭示者，乃較佳實施例，舉凡局部之變更或修 飾而源於本案之技術思想而為熟習該項技藝之人所易於推 知者，倶不脫本案之專利權範嘴。 、表上所陳，本案無論就目的、手段與功效，在在顯示 其迥異於習知之技術特徵，且其首先創作合於實用，亦在 在符合新型之專利要件，懇請f審查委員明察，並祈早 曰賜予專利，俾嘉惠社會，實感德便。 【圖式簡單說明】The Vs AW ° f pulse generator 510 is configured to generate the pulse wave signal Sp according to the sawtooth wave signal Vsaw and the feedback signal VFB. π \ / In FIG. 5, the voltage to current converter 503 generates the current 丨υρΑ according to the feedback signal, one of the first functions of the vFB, and the voltage to current converter 50= according to the feedback signal Vfb A second function generates the current Idna. The current 丨UPA is less than the current squeak and the current 丨dna is less than the current ιυΡ, and the first function and the second function are preferably a polynomial of the feedback signal Vfb. Referring to FIG. 6 ′, a circuit diagram of the pwM controller of the preferred embodiment of the present invention, in which the sawtooth signal generator operates in the power saving mode, is illustrated. As shown in FIG. 6, the sawtooth signal generator of the present invention includes a pM〇s transistor 601, an NMOS transistor 602, a PMOS transistor 603, an NMOS transistor 604, an NMOS transistor 605, and an operational amplifier. The OPA 606, a resistor 607, a PMOS transistor 608, an NMOS transistor 609, a PMOS transistor 610, an NM〇S transistor 611, a switch 612, a switch 613, and a capacitor 614. The PMOS transistor 601 is used to copy the current 丨 to its other branch. The NMOS transistor 602 is used to generate a voltage vx = VFB - VGS. The PMOS transistor 603 is used to replicate the current flowing through the pM〇S transistor 601 to generate a voltage vY=VA-VGS. The NMOS transistor 605 is used to provide a current path for the current 丨. The operational amplifier 0PA 606 is used as a unit-gain buffer. 201023520 The resistor 607 has a resistance value R for generating the current I = (Vx - VY) / R °. The PMOS transistor 608 is used to replicate the current flowing through the pm 〇 ray crystal 601. The 609 is used to copy the current 到 to the other sub-eighth. The PMOS transistor 610 is configured to generate the current according to the current ΙυΡΑ 0. The NMOS transistor 611 is configured to generate the current according to the current .. Idna 〇 The roles of the switch 612, the switch 613 and the capacitor 614 are the same as those of the switch 507, the switch 508 and the capacitor 509 in FIG. 5, and therefore will not be described here. In the preferred embodiment described above, the first function and the second function may be changed to other forms such as, but not limited to, a constant function. In the case of a constant function, the power save mode switching period is longer than the normal mode switching period and it is also a fixed period. 10 In addition, in a power conversion application including a transformer, when the linear rise period of the power saving mode is too long, the transformer may have a risk of being linked. In this case, the PWM controller of a preferred embodiment of the present invention may further include a pulse width limiting mechanism. Referring to Figure 7, a block diagram of a pulse width limiter 700 is shown. As shown in Fig. 7, the pulse width limiter 700 includes a click pulse generator 7〇1 and a gate 7〇2. The click pulse generator 701 is configured to generate a click pulse SPL having a fixed pulse width according to the pulse signal sp, and the gate 702 is configured to use the pulse signal sp and the click pulse Spi_ produces an output signal SOUT. By properly setting the fixed pulse width, 11 201023520 ensures that the transformers for these power conversion applications are not saturated. The disclosure of the present invention is a preferred embodiment. Any change or modification of the present invention originating from the technical idea of the present invention and being easily inferred by those skilled in the art can not deviate from the patent right of the case. On the table, the case, regardless of its purpose, means and efficacy, is showing its technical characteristics that are different from the conventional ones, and its first creation is practical, and it is also in compliance with the new patent requirements, so please review the members, and I prayed for the patent, and I was very happy with the society. [Simple description of the map]
應用之 圖1為示意圖，其繪示一PWM控制器之典型 架構圖。 ^ f知PWM控制器之電路圖。 號波^為不意圖’其繪示一習知PWMfe制器之主要信 及r S 其繪不本案—較佳實施例之正常模式 形圖’其各包括-線性上升期 制器’鱗示本案—較佳實施例之pwm控 制 罘圖盆64^^圖妹^會示本案一較佳實施例之PWM控 Λ ^軸模式時之電路圖。 限制器之一不本案—較佳實施例之脈波寬度 【主要元件符號說明】 PWM控制器1〇〇 輸入整流及滤波器1〇1 主變壓器102 12 201023520 輸出整流及濾波器103 回授電路104 NMOS電晶體105 鋸齒波信號產生器200、500 觸發信號產生器201 閂鎖器202 反閘 203、204 重置產生器205 輸出級206 ❿定電流源501、502 電壓至電流轉換器503、504 開關 505、506、507、508、612、613 電容 509、614 脈波產生器510 電阻607 PMOS 電晶體 601、603、608、610 NMOS 電晶體 602、604、605、609、611 運算放大器OPA606 ® 脈波寬度限制器700 單擊脈波產生器701 及閘702 13Application Figure 1 is a schematic diagram showing a typical architecture of a PWM controller. ^ f Know the circuit diagram of the PWM controller. The number wave ^ is not intended to 'show the main letter of a conventional PWMfe device and r S which is not the case - the normal mode diagram of the preferred embodiment' each includes a linear riser' scale - The pwm control panel of the preferred embodiment is shown in the circuit diagram of the PWM control mode in the preferred embodiment of the present invention. One of the limiters is not the case - the pulse width of the preferred embodiment [Description of main component symbols] PWM controller 1 〇〇 input rectification and filter 1 〇 1 main transformer 102 12 201023520 output rectification and filter 103 feedback circuit 104 NMOS transistor 105 sawtooth signal generator 200, 500 trigger signal generator 201 latch 202 reverse gate 203, 204 reset generator 205 output stage 206 set current source 501, 502 voltage to current converter 503, 504 switch 505, 506, 507, 508, 612, 613 Capacitance 509, 614 Pulse Generator 510 Resistor 607 PMOS Transistor 601, 603, 608, 610 NMOS Transistor 602, 604, 605, 609, 611 Operational Amplifier OPA606 ® Pulse Wave Width limiter 700 clicks pulse generator 701 and gate 702 13