JP5545857B2 - DC-DC converter control circuit and DC-DC converter - Google Patents

Description

  The present invention relates to a DC-DC converter control circuit and a DC-DC converter.

  As a control circuit for a DC-DC converter, a control circuit for current mode control as shown in FIG. 1 is known (see Non-Patent Document 1).

  In the control circuit shown in FIG. 1, one end of the inductor L is connected to the input terminal, a diode D is connected between the other end of the inductor L and the output terminal, and a node between the inductor L and the diode D is connected to the ground. Is a control circuit connected to a step-up DC-DC converter section to which a switching transistor M1 is connected.

The control operation of the control circuit shown in FIG. 1 will be described below.
The combined signal generation circuit 930 outputs a combined signal S930 of the detection signal S910 based on the current IM flowing through the switching transistor M1 and the ramp signal S920 output from the ramp signal generation unit 920 to the non-inverting input terminal of the comparator 950. . Here, the ramp signal S920 plays a role of slope compensation for preventing subharmonic oscillation in which the inductor current IL oscillates at a frequency of 1 / n of the fundamental wave when the on-duty is 50% or more.

  On the other hand, a voltage signal obtained by dividing the voltage of the output terminal by the resistors R1 and R2 is input to the inverting input terminal of the error amplifier 940 as a signal S911 based on the signal of the node between the input terminal and the output terminal, and a predetermined reference signal The difference is amplified by inputting S912 to the non-inverting input terminal of the error amplifier 940, and the control signal S940 is output to the inverting input terminal of the comparator 950. When the composite signal S930 becomes larger than the control signal S940, the comparator 950 outputs a HIGH output signal to the reset of the flip-flop 961, the flip-flop outputs a LOW drive signal S960, and the switching transistor M1 It becomes OFF. Then, the oscillator 962 that outputs a HIGH pulse to the set of flip-flops 961 with a constant clock outputs a HIGH drive signal S960 to the flip-flops, and the switching transistor M1 is turned ON again. By repeating these operations, control is performed so as to operate as a DC-DC converter.

“Transistor Technology”, CQ Publishing Co., Ltd., April 2004, P213-222

  As described above, in the current mode control control circuit as shown in FIG. 1, the duty ratio of the drive signal S960 is determined by the result of comparing the control signal S940 and the combined signal S930. Once the switching transistor M1 is turned on, the detection signal S910 increases and the combined signal S930 also increases. Then, when it becomes equal to the control signal S940, it is turned OFF, and it is turned OFF until the next switching cycle starts. Since the control signal itself limits the current IM flowing through the switching transistor M1, the current IL flowing through the inductor L can be indirectly limited without providing a separate current limiting circuit, and the load connected to the output terminal It becomes possible to control the current to.

  However, the control signal S940 changes according to the signal S911 based on the signal of the node between the input terminal and the output terminal, and may affect the load connected to the output terminal depending on the input / output state. A large current may flow through the inductor L. As a means for preventing such a large current from flowing through the inductor L, a method using a comparator 951 having a plurality of multi-input inverting input terminals as shown in FIG.

  In the control circuit of FIG. 2, the limit signal S940 is input to one inverting input terminal of the multi-input comparator 951 as before, and the constant limit signal S921 is input to the other inverting input terminal.

  FIG. 3 shows an operation when the limit signal S940 becomes larger than the constant limit signal S921. When the combined signal S930 obtained by combining the detection signal S910 based on the current IM flowing through the switching transistor M1 and the ramp signal S920 matches the constant limit signal S921, the multi-input comparator 951 outputs a HIGH signal to the flip-flop 961. The reset signal is output, the drive signal S960 becomes LOW, and the switching transistor M1 is turned OFF.

  According to the circuit of FIG. 2, it seems that the desired current limit is possible at first glance. However, when the input / output voltage changes and the duty ratio of the switching transistor M1 changes, what is the inductor current IL to be limited? There arises a problem that the switching transistor M1 is turned off by different inductor currents.

  FIG. 4 is a waveform diagram when the above problem occurs. 4 (a1) to FIG. 4 (a3) show a case where the on-duty is 20% due to the constant limit signal S921, and FIGS. 4 (b1) to 4 (b3) are based on the constant limit signal S921. It is a figure which shows the case where an on-duty becomes 60%. The on-duty ratio changes based on the input / output conditions. In the step-up DC-DC converter, for example, when the input voltage is close to the output voltage, the on-duty becomes low.

  FIG. 4 (a1) is a diagram showing that the combined signal S930 (a) is limited by a fixed limit signal S921. FIG. 4 (a2) is a diagram showing a signal obtained by decomposing the combined signal S930 (a) of FIG. 4 (a1) into a detection signal S910 (a) and a ramp signal S920 before combining. FIG. 4 (a3) is a diagram showing the inductor current IL (a) obtained from the detection signal S910 (a) and its peak current ILpk (a).

  FIG. 4B1 is a diagram illustrating that the combined signal S930 (b) is limited by a certain limit signal S921. FIG. 4B2 is a diagram illustrating a signal obtained by decomposing the combined signal S930 (b) of FIG. 4B1 into a detection signal S910 (b) and a ramp signal S920 before combining. FIG. 4 (b3) is a diagram showing the inductor current IL (b) obtained from the detection signal S910 (b) and its peak current ILpk (b).

  As is clear from the comparison between FIGS. 4A3 and 4B3, ILpk (a)> ILpk (b), and it can be seen that each is limited by a peak value of a different inductor current.

  That is, an object of the present invention is to provide a DC-DC converter control circuit and a DC-DC converter capable of limiting the inductor current IL to a desired value regardless of input / output conditions.

As a result of intensive studies to solve the above problems, the present inventors have found that the control circuit of the DC-DC converter according to claim 1 of the present invention is provided between any one of the input terminal, the output terminal, and the ground. A DC-DC converter control circuit for controlling a DC-DC converter unit including an inductor and a switching transistor connected to the inductor, wherein the control circuit outputs a detection signal corresponding to a current flowing through the switching transistor. Current detection means; first ramp signal generation means for generating a first ramp signal; and second ramp signal generation means for generating a second ramp signal obtained by shifting the first ramp signal upward. Generating a combined signal of the detection signal corresponding to the current flowing through the switching transistor and the first ramp signal And stage, the feedback voltage signal based on the voltage of the output terminal is input to the inverting input terminal, a predetermined reference signal is input to the non-inverting input terminal, an error amplifier for generating a control signal, the combined signal is a non-inverting input A comparator having the control signal input to the first inverting input terminal, the second ramp signal input to the second inverting input terminal, and a duty ratio based on the output signal of the comparator. It has been found that the above problem can be solved by generating a drive signal and driving circuit for driving the switching transistor, and the present invention has been completed.

Further, DC-DC converter control circuit according to claim 2, characterized in that on SL predetermined reference signal is a predetermined reference voltage.

  According to a third aspect of the present invention, the drive circuit includes a flip-flop circuit in which a pulse signal is input to the set at a predetermined cycle, and the output of the comparator is connected to the reset.

  In order to solve the above problem, a DC-DC converter according to claim 4 of the present invention is an inductor existing between any of an input terminal, an output terminal, and a ground, and a switching connected to the inductor. A transistor and a control circuit according to any one of claims 1 to 3 are provided.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the control circuit and DC-DC converter of a DC-DC converter which can restrict | limit an inductor electric current with a desired value.

It is a circuit diagram which shows the control circuit of the conventional step-up type DC-DC converter of a current mode limitation type. FIG. 3 is a circuit diagram showing a control circuit of a current mode limited step-up DC-DC converter in which a combined signal is controlled by a constant limit signal. It is a figure which shows the operation example of the control circuit of FIG. FIG. 3 is a diagram illustrating an example of current limitation at different on-duty in the control circuit of FIG. 2. It is a figure which shows the control circuit of the DC-DC converter by the 1st Embodiment of this invention. It is a circuit diagram of the control circuit of the DC-DC converter by the 2nd Embodiment of this invention, and is a figure which shows the example of the concrete circuit structure of the 1st and 2nd ramp signal production | generation means and a synthetic | combination means. It is a figure which shows the control circuit of the pressure | voltage rise type DC-DC converter by the 3rd Embodiment of this invention. It is a figure which shows the example of the electric current limitation by the control circuit of FIG. It is a figure which shows the example of a converter part.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 5 is a circuit diagram of a control circuit of the DC-DC converter according to the first embodiment of the present invention.

  In FIG. 5, the control circuit 1 according to the first embodiment of the present invention includes an inductor L between any one of the input terminal 3, the output terminal 4, and the ground 5, and a switching transistor M <b> 1 connected to the inductor L. The DC-DC converter unit 2 is controlled.

  The control circuit 1 includes a current detection unit 10 that outputs a detection signal S10 corresponding to a current flowing through the switching transistor M1, a first ramp signal generation unit 20 that generates a first ramp signal S20, and the first A second ramp signal generating means 21 that generates a second ramp signal S21 having the same period and slope as the ramp signal, and a combined signal S30 of the detection signal S10 and the first ramp signal S20 are generated. The signal S11 based on the combined signal generating means 30, and the signal of the node between the input terminal 3 and the output terminal 4, is input to the inverting input terminal, the predetermined reference signal S12 is input to the non-inverting input terminal, and the control signal S40 And the synthesized signal S30 are input to a non-inverting input terminal, the control signal S40 is input to a first inverting input terminal, and the second A comparator 51 to which an amplifier signal S21 is input to a second inverting input terminal, a drive circuit 60 for generating a drive signal S60 having a duty ratio based on the output signal S50 of the comparator 51, and driving the switching transistor M1, Is provided.

  Here, the DC-DC converter section 2 is not particularly limited as long as it converts an input voltage into a desired output voltage. For example, the DC-DC converter section 2 is a non-insulated chopper boost DC-type shown in FIG. 9B, a non-insulated chopper step-down DC-DC converter shown in FIG. 9B, a non-insulated chopper step-up / step-down DC-DC converter shown in FIG. 9C, and FIG. Insulation buck-boost type DC-DC converter shown in FIG. In the case of the non-insulated chopper step-up / step-down DC-DC converter shown in FIG. 9C, both the detection signal corresponding to the current flowing through the transistors M and M ′ are combined with the ramp signal S20 by the combined signal generating means. By synthesizing, a later-described current limiting operation is possible.

  Further, the non-insulated DC-DC converters of FIGS. 9A to 9C are elements in which the diode D is controlled in a complementary manner with the switching transistor M (for example, a p-type MOSFET if the transistor M is an n-type MOSFET). Alternatively, a synchronous rectification DC-DC converter may be used.

  The drive circuit 60 is not particularly limited as long as it generates the drive signal S60 having a duty ratio based on the output signal from the comparator 51, and is appropriately appropriate depending on the state of the DC-DC converter unit 2 to be controlled. Things can be adopted. As an example, there is a circuit having a flip-flop that is set or reset at a certain period and a driver that can amplify and / or phase-shift a signal from the flip-flop.

  FIG. 6 is a circuit diagram of the control circuit of the DC-DC converter according to the second embodiment of the present invention. The first ramp signal generating means 20, the second ramp signal generating means 21 used in the present invention, and 3 is an example of a specific circuit configuration of the combining unit 30. Note that the transistors M3 to M5 are all transistors of the same size.

  The first ramp signal generation means 20 includes an oscillator 201, an operational amplifier 202, transistors M3 and M4, and a resistor R1, and a current signal corresponding to the ramp signal output from the oscillator 201 is a first ramp signal S20. Generate as

  The second ramp signal generating means 21 includes a transistor M5, a constant current source 211, and a resistor R4. In the transistor M5, a current generated by mirroring the current signal of the first ramp signal S20 is generated, and this current and the current signal S211 output from the constant current source 211 are combined at the node N1 and flow to the resistor R4. . Therefore, the node N2 outputs the second ramp signal S21 in which the first ramp signal S20 is shifted upward by the current signal S211.

  The synthesizing means 30 is composed of resistors R2 and R3. The first ramp signal S20 flows through the node N4, and the detection signal S10 is input into the node N3. Therefore, the node N4 outputs a combined signal S30 of the first ramp signal S20 and the detection signal S10.

  FIG. 7 is a circuit diagram of a control circuit of the DC-DC converter according to the third embodiment of the present invention.

  In the control circuit 1 shown in FIG. 7, one end of the inductor L is connected to the input terminal 3, and a p-type MOSFET is connected as the switching transistor M <b> 2 between the other end of the inductor L and the output terminal 4. 2 is a control circuit for the step-up synchronous rectification DC-DC converter unit 2 of a non-insulated chopper type in which an n-type MOSFET is connected as a switching transistor M1 between a node between the first node and the ground 5. Although not shown in the figure, a driver that outputs two drive signals obtained by phase-shifting the output signal from the flip-flop 61 to each of the switching transistors M1 and M2 according to characteristics such as threshold voltages of the switching transistors M1 and M2 is provided in the flip-flop 61. And between the switching transistors.

  A clock signal having a fixed period output from the oscillator 62 is input to the set of the flip-flop 61, the drive signal S60 becomes a HIGH signal, the switching transistor M1 is turned on, the p-type MOSFET is turned off, and the current IM is supplied to the switching transistor M1. Flows.

  The combining unit 30 outputs a combined signal S30 of the signal S10 corresponding to the current IM flowing through the switching transistor M1 and the first ramp signal S20 to the non-inverting input terminal of the multi-input comparator 51.

  In the error amplifier 40, the voltage signal S11 obtained by dividing the voltage of the output terminal 4 by the resistors R1 and R2 is input to the inverting input terminal, and the reference voltage VREF is input to the non-inverting input terminal as the predetermined reference voltage S12. A control signal S40 obtained by amplifying the input difference is generated and output to one of the inverting input terminals of the multi-input comparator 51.

  The second ramp signal generation unit 21 generates a second ramp signal S21 obtained by shifting the first ramp signal upward, and outputs the second ramp signal S21 to the other inverting input terminal of the multi-input comparator 51.

  The multi-input comparator 51 resets the output signal S50 to the flip-flop 61 when the composite signal S30 input to the non-inverting input terminal matches either the control signal S40 input to the inverting input terminal or the second ramp signal S21. And the drive signal S60 becomes LOW, turning off the switching transistor M1, and turning on the p-type MOSFET.

  FIG. 8 is a diagram illustrating an example of current limiting by the control circuit of FIG.

  FIG. 8 shows operation waveforms when the control signal S40 is sufficiently higher than the second ramp signal S21 in the circuit of FIG.

  FIGS. 8 (a1) to 8 (a3) show a case where the on-duty is 20% by the second ramp signal S21, and FIGS. 8 (b1) to 8 (b3) show the second ramp signal. It is a figure which shows the case where an on-duty becomes 60% by S21.

  FIG. 8A1 is a diagram showing that the combined signal S30 (a) is limited by the second ramp signal S21. FIG. 8A2 is a diagram illustrating a signal obtained by decomposing the combined signal S30 (a) of FIG. 8A1 into a detection signal 10 (a) before combining and a first ramp signal S20. FIG. 8A3 shows the inductor current IL (a) obtained from the detection signal S10 (a) and its peak current ILpk (a).

  FIG. 8B1 is a diagram showing that the combined signal S30 (b) is limited by the second ramp signal S21. FIG. 8 (b2) is a diagram showing a signal obtained by decomposing the combined signal S30 (b) of FIG. 8 (b1) into a detection signal S10 (b) and a first ramp signal S20 before combining. FIG. 8 (b3) is a diagram showing the inductor current IL (b) obtained from the detection signal S10 (b) and its peak current ILpk (b).

  As is clear from comparing FIGS. 8A3 and 8B3, ILpk (a) = ILpk (b), and it can be seen that each is controlled by the same inductor current peak value.

  The present invention is suitable as a control circuit for a DC-DC converter.

DESCRIPTION OF SYMBOLS 1 Control circuit 2 DC-DC converter part 3 Input terminal 4 Output terminal 5 Ground 20 1st ramp signal generation means 21 2nd ramp signal generation means 920 Ramp signal generation means 30,930 Synthetic signal generation means 40,940 Error amplifier 950 Comparator 51, 951 Multi-input comparator 60 Drive circuit 61, 961 Flip-flop 62, 962 Oscillator S10, S910 Detection signal S11, S911 Signal based on signal of node between input terminal and output terminal S12, S912 Predetermined reference signal S20 first ramp signal S21 second ramp signal S920 ramp signal S30, S930 combined signal S40, S940 error amplifier output signal S50, S950 comparator output signal S60, S960 drive signal

Claims (4)

Between any of the input terminal, output terminal and ground,
A control circuit for a DC-DC converter for controlling a DC-DC converter unit including an inductor and a switching transistor connected to the inductor,
The control circuit includes:
Current detection means for outputting a detection signal corresponding to the current flowing through the switching transistor;
First ramp signal generating means for generating a first ramp signal;
Second ramp signal generating means for generating a second ramp signal obtained by shifting the first ramp signal upward;
Combined signal generating means for generating a combined signal of the detection signal corresponding to the current flowing through the switching transistor and the first ramp signal;
A feedback voltage signal based on the voltage of the output terminal is input to the inverting input terminal, a predetermined reference signal is input to the non-inverting input terminal, and an error amplifier that generates a control signal;
A comparator in which the composite signal is input to a non-inverting input terminal, the control signal is input to a first inverting input terminal, and the second ramp signal is input to a second inverting input terminal;
A drive circuit for generating a drive signal having a duty ratio based on the output signal of the comparator and driving the switching transistor;
A control circuit for a DC-DC converter, comprising: DC-DC converter control circuit according to claim 1 before Symbol predetermined reference signal is a predetermined reference voltage. The drive circuit is
3. The DC-DC converter control circuit according to claim 1, further comprising a flip-flop circuit in which a pulse signal is input to the set at a predetermined cycle, and an output of the comparator is connected to a reset. An inductor existing between any of the input terminal, the output terminal, and the ground, and a switching transistor connected to the inductor;
A control circuit according to any one of claims 1 to 3,
DC-DC converter provided with.

Images