TW201021154A - Electrostatic chuck containing buffer layer for reducing thermal stress - Google Patents
Electrostatic chuck containing buffer layer for reducing thermal stress Download PDFInfo
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- TW201021154A TW201021154A TW098130090A TW98130090A TW201021154A TW 201021154 A TW201021154 A TW 201021154A TW 098130090 A TW098130090 A TW 098130090A TW 98130090 A TW98130090 A TW 98130090A TW 201021154 A TW201021154 A TW 201021154A
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- terminal
- buffer layer
- electrostatic chuck
- base plate
- insulating member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
- H02N13/00—Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Jigs For Machine Tools (AREA)
Abstract
Description
201021154 1W5632FA ^ 六、發明說明： 【發明所屬之技術領域】 本發明之是有關於一種位於處理腔室中之靜電夾 頭，且特別是有關一種以緩衝層覆蓋之靜電夾頭，用以在 執行使用靜電夾頭之製程時降低熱應力，並使由於熱應力 所導致之靜電夾頭之龜裂最小化。 【先前技術】 一般而言，半導體裝置與例如液晶顯示器（LCD)裝置 之平面板裝置之製程，係包含例如化學氣相沈積（CVD)之 沈積製程以及例如反應性離子蝕刻製程之蝕刻製程。於上 述沈積製程與蝕刻製程中，需要將例如矽晶圓與玻璃面板 之基板固定至處理腔室中之電極板，俾能改善製程可靠 度。靜電夾頭（ESC)通常用來將基板固定至處理腔室中之 電極板。 第1圖係為顯示在處理腔室中之習知靜電夾頭之剖 面圖。 參見第1圖，習知之靜電夾頭100包含：一本體101， 其包含鋁；一基底平板102,於其上固定地安置有一基板； 一電極103,裝設於基底平板102之内部中並產生靜電力； 一端子104,用以施加高電壓至前述電極；以及一絕緣構 件105，其包圍端子104。 高電壓係經由端子104而從外部電源被施加至電極 201021154201021154 1W5632FA ^ VI. Description of the Invention: [Technical Field] The present invention relates to an electrostatic chuck located in a processing chamber, and more particularly to an electrostatic chuck covered with a buffer layer for execution The use of an electrostatic chuck reduces the thermal stress and minimizes cracking of the electrostatic chuck due to thermal stress. [Prior Art] In general, a process of a semiconductor device and a planar panel device such as a liquid crystal display (LCD) device includes a deposition process such as chemical vapor deposition (CVD) and an etching process such as a reactive ion etching process. In the above deposition process and etching process, it is necessary to fix a substrate such as a germanium wafer and a glass panel to an electrode plate in a processing chamber, which can improve process reliability. Electrostatic chucks (ESC) are commonly used to secure substrates to electrode plates in processing chambers. Figure 1 is a cross-sectional view of a conventional electrostatic chuck shown in a processing chamber. Referring to FIG. 1 , a conventional electrostatic chuck 100 includes a body 101 including aluminum, a substrate plate 102 on which a substrate is fixedly disposed, and an electrode 103 disposed in the interior of the substrate plate 102 and produced. An electrostatic force; a terminal 104 for applying a high voltage to the electrode; and an insulating member 105 surrounding the terminal 104. The high voltage is applied to the electrode from the external power source via the terminal 104 201021154
• ι woo^zrA 103，而靜電力可能產生於電極103。然後，基底平板102 上之基板係藉由靜電力而被取出朝向基底平板102，並被 固定至靜電夾頭100。 於習知之沈積製程或蝕刻製程中，基底平板1〇2係由 處理腔室中之電漿所加熱，而靜電夾頭1〇〇之基底平板1〇2 通常由於處理腔室中之電漿之高溫而處在大熱應力之 下。更明確而言，熱係從基底平板102被傳送至鋁本體 101 ’從而使本體101朝所有方向呈現熱膨脹。因為本體 101、基底平板102與絕緣構件1〇5之熱係數通常彼此不 同’所以熱應力係被施加至本體1〇1、基底平板1〇2及絕 緣構件105。在習知之靜電夾頭100中，讓本體1〇1、基 底平板102與絕緣構件1〇5彼此接觸之邊界區域之上端部 A之熱應力達到最大化。 因為基底平板102具有遠小於本體1〇1與絕緣構件 105的強度’所以在邊界區域之上端部A之熱應力對於基 ❹底平板1〇2比對於本體101與絕緣構件1〇5具有來得更多 的影響，從而於靠近邊界區域之上部A之基底平板1〇2之 下部產生龜裂。當靜電失頭1〇〇重複操作時，龜裂係• ι woo^zrA 103, and an electrostatic force may be generated from the electrode 103. Then, the substrate on the substrate flat plate 102 is taken out toward the base flat plate 102 by electrostatic force, and is fixed to the electrostatic chuck 100. In the conventional deposition process or etching process, the substrate plate 1〇2 is heated by the plasma in the processing chamber, and the substrate plate 1〇2 of the electrostatic chuck 1 is usually due to the plasma in the processing chamber. High temperature and under great thermal stress. More specifically, the thermal system is transferred from the substrate plate 102 to the aluminum body 101' such that the body 101 exhibits thermal expansion in all directions. Since the thermal coefficients of the body 101, the base plate 102, and the insulating member 1〇5 are generally different from each other, thermal stress is applied to the body 1〇1, the base plate 1〇2, and the insulating member 105. In the conventional electrostatic chuck 100, the thermal stress of the upper end portion A of the boundary region where the body 1〇1, the base plate 102 and the insulating member 1〇5 are in contact with each other is maximized. Since the base plate 102 has a strength much smaller than that of the body 1〇1 and the insulating member 105, the thermal stress at the end portion A above the boundary region is greater for the base plate 1〇2 than for the body 101 and the insulating member 1〇5. The influence is large, so that cracks are generated in the lower portion of the base plate 1〇2 near the upper portion A of the boundary region. When the static electricity is lost, the crack system is repeated.
^底平板102之上部以及整體的基底平板102，而最後 基底平板102由於龜裂而損壞。 X 因此，對於能將由於熱應力所導致之龜裂最小化，藉 =免靜電爽頭之故障之改良之靜電失頭，存在有強烈! 201021154The upper portion of the bottom plate 102 and the integral base plate 102, and finally the base plate 102 is damaged by cracking. X Therefore, there is a strong static head loss that can minimize the crack caused by thermal stress, and the failure of the static electricity-free head is improved! 201021154
TW5632FA » 【發明内容】 實施示範例提供一種供ESC用之端子單元，其包含一 緩衝層’用以在操作使用ESC之一製程時吸收熱應力；實 施示範例亦提供端子單元之形成方法。 實施示範例亦提供具有上述端子單元之ESC以及ESC 之製造方法。 依據某些實施示範例，提供一種靜電夾頭（ESC)，其 包含··一本體’具有一穿孔；一基底平板，配置於本體上， 其中一基板係藉由一靜電力而固定至基底平板，該基底平 板具有對應至本體之穿孔之一插入部以及安置於基底平 板之内部並經由插入部而局部露出之一電極；一端子單 元’具有經由本體之穿孔以及基底平板之插入部而與電極 接觸之一端子；以及一緩衝層，配置於端子與本體和基底 平板之至少一者之間之一邊界區域，並吸收本體之熱應 力。 於一實施示範例中，本體包含一導電材料，而端子單 元包含介設於本體與穿孔中之端子之間之一絕緣構件，俾 能使緩衝層被配置於本體與絕緣構件之間之一邊界區 域。緩衝層係更進一步被配置於絕緣構件與基底平板之間 之一邊界區域。 於一實施示範例中，基底平板與緩衝層包含基於陶瓷 材料之材料。緩衝層之孔隙率係等於或高於基底平板之孔 隙率。緩衝層之孔隙率係在大約2%至大約1〇%之範圍内。 緩衝層之厚度係在大約ΙΟΟμιη至大約25〇μπι之範圍内。緩 201021154 • 1 w^o^zr/\ 曰依摅面報糙度係在大約〇· 1μΠ1至大約2μΐΠ之範圍内。 子單元，某些實施示範例，提供一種供一靜電夾頭用之端 至一電極其包含一端子，電連接至一電源並施加一電力 子，俾能藉^產生—靜電力；—絕緣構件，局部包圍端 以及一緩〜由絕緣構件而使端子能與外界環境電氣絕緣； +从衝層，配置於端子與絕緣構件之至少一者上，並 吸收由外界環_施加之熱Μ。 並TW5632FA » SUMMARY OF THE INVENTION Embodiments provide a terminal unit for ESC that includes a buffer layer </ RTI> for absorbing thermal stress during operation of one of the ESC processes; and an exemplary embodiment also provides a method of forming a terminal unit. The embodiment also provides a method of manufacturing the ESC and the ESC having the above terminal unit. According to some embodiments, an electrostatic chuck (ESC) is provided, comprising: a body having a perforation; a substrate plate disposed on the body, wherein a substrate is fixed to the substrate plate by an electrostatic force The base plate has an insertion portion corresponding to the perforation of the body and disposed inside the base plate and partially exposing one of the electrodes via the insertion portion; a terminal unit having the insertion portion through the body and the insertion portion of the base plate and the electrode Contacting one of the terminals; and a buffer layer disposed at a boundary region between the terminal and at least one of the body and the base plate, and absorbing thermal stress of the body. In an exemplary embodiment, the body includes a conductive material, and the terminal unit includes an insulating member interposed between the body and the terminal in the through hole, and the buffer layer is disposed at a boundary between the body and the insulating member. region. The buffer layer is further disposed in a boundary region between the insulating member and the base plate. In an embodiment, the substrate plate and the buffer layer comprise a material based on a ceramic material. The porosity of the buffer layer is equal to or higher than the porosity of the substrate plate. The porosity of the buffer layer is in the range of from about 2% to about 1%. The thickness of the buffer layer is in the range of from about ιμηη to about 25 〇μπι. Slowness 201021154 • 1 w^o^zr/\ The roughness of the surface is in the range of approximately 〇·1μΠ1 to approximately 2μΐΠ. Subunit, some embodiments, provide a terminal for an electrostatic chuck to an electrode, which comprises a terminal, is electrically connected to a power source and applies a power source, and can generate an electrostatic force; The partial surrounding end and the slowing end are electrically insulated from the external environment by the insulating member; + the secondary layer is disposed on at least one of the terminal and the insulating member, and absorbs the heat applied by the external ring. and
、、； 某些實施示範例，提供一種靜電夾頭之製造方 法#準備具有一穿孔之一本體，並提供對應至穿孔之一端 子單元。端子具有—緩衝層，用以吸收本體之表面上之熱 應力。本體與端子單元可能彼此結合，以使端子單元貫穿 一下基底平板係形成於本 此穿孔並凸出本體之一上表面。 體上，以使端子之一上表面露出，而一電極係形成於下基 底平板上’以使電極與露出之端子單元接觸。一上基底平 板係形成於下基底平板與電極上。 依據某些實施示範例，提供一種形成供一靜電夾頭用 之一端子單元之方法。利用端子貫穿靜電夾頭之一本體並 電連接至一外部電源之這樣的方式來準備一端子。此端子 係被插入至一絕緣體，以使端子之一末端部分露出。一緩 衝層係形成於端子之露出表面上，緩衝層吸收由外界環境 所施加之熱應力。 於一實施示範例中，緩衝層之形成方式如下：將絕緣 髏移離端子，藉以露出端子之末端部分；以及將缓衝層塗 佈於露出之端子上。緩衝層可能藉由大氣所導致的電漿喷 7 201021154 灑塗佈製程而塗佈於端子上。在形成緩衝層之後，可更進 一步在緩衝層上執行倒角製程，藉以將緩衝層之一邊緣部 分形成為圓形。 依據某些實施示範例’ ESC之熱應力可能被吸收至 ESC中之緩衝層，從而可能充分減少由熱應力所導致的龜 裂，藉以增加ESC之耐久性壽命。 為讓本發明之上述内容能更明顯易懂，下文特舉一較 佳實施例’並配合所附圖式，作詳細說明如下： 【實施方式】 以下將參考附圖更完全地說明各種實施示範例，於 附圖中顯示本發明之數個實施示範例。然而，本發明可能 以許多不同的形式被具體化，且不應被解釋成受限於於此 所提出之實施示範例。反之，這些實施示範例之提供是為 為清楚起見，可 了能使這個揭露書呈現徹底且完整的，且將完全傳達本發 明之範疇給熟習本項技藝者。在附圖中 能誇大數個層與數個區域之尺寸與相對尺寸 •之上 吾人將理解到當一元件或層被稱為係「在〜丄、 「連接至」或「耦接至」另一個元件或層時，其可=《1」亩 接在其之上、連接或耦接至另一個元件或層或者 一 件或層可能存在。相較之下，當一元件被稱為係= 之上」、「直接連接至」或「直接耦接至」另一個元件或層 時，則沒有中介元件或層存在。遍及全文，相同的參考數 字表不相同的兀件。如於此所使用的，專門用語「及/戋 201021154 包含一個或多個相關的列出項目之任 ❹ 參 吾人將理解到雖然專門用語第_:d 於此被使用以說明各種元件、組件、區域、層及/或部犯 但這些元件、組件、區域、層及/或部不應受限於這二專 門用語。這些專門用語只用以區別一個元件、組件、區域、 層或部與另一個區域、層或部。因此，在不背離本發明之 教導之下，以下所討論之一第一元件、組件、區域、層或 部可稱為一第二元件、組件、區域、層或部。 於此可能使用空間相對的專門用語，例如「在底下」、 「在下方」、「低於」、「在上方」、「高於」等等，以便簡化 說明顯示於圖中之-個元件或特徵部與另—元件或特徵 部之間的關係。吾人將理解到空間相對的專門用語係意圖 使用中或操作中之除了描♦於圖中之方位以外的不 同方位之裳置。舉例而言，如果翻轉圖中之裝置，「位在 其他元件料徵部町或底下」之元狀綠會被改變成 「位在其他7〇件或特徵部以上」。因此，例示的專門用語 定包含上方或下方之方位。此裝置可能會被重新 度或位於其他方值），且使用於此之空間 相對的敘述元因此得到解釋。 例，之專門用語係只用以說明特定實施示範 ===:本r之限制。如於此所使用的，除 式。吾人將I則早數形式係意圖也包含複數形 有」，當於太切:步理解到專門用語「包含」及/或「含 ;§明書中所使用時，指定出規^特徵、整數、 9 201021154Some embodiments show a method of manufacturing an electrostatic chuck. A body having a perforation is prepared and a terminal unit corresponding to one of the perforations is provided. The terminal has a buffer layer for absorbing thermal stress on the surface of the body. The body and the terminal unit may be coupled to each other such that the terminal unit is formed through the base plate to be perforated and protrudes from an upper surface of the body. The upper surface of one of the terminals is exposed, and an electrode is formed on the lower base plate to bring the electrode into contact with the exposed terminal unit. An upper substrate is formed on the lower substrate plate and the electrodes. According to certain embodiments, a method of forming a terminal unit for an electrostatic chuck is provided. A terminal is prepared in such a manner that the terminal penetrates one of the bodies of the electrostatic chuck and is electrically connected to an external power source. This terminal is inserted into an insulator to expose one end portion of the terminal. A buffer layer is formed on the exposed surface of the terminal, and the buffer layer absorbs thermal stress applied by the external environment. In an exemplary embodiment, the buffer layer is formed by moving the insulating raft away from the terminal to expose the end portion of the terminal; and applying a buffer layer to the exposed terminal. The buffer layer may be applied to the terminals by a plasma spray process caused by the atmosphere. After the buffer layer is formed, the chamfering process can be further performed on the buffer layer, whereby one edge portion of the buffer layer is formed into a circular shape. According to certain embodiments, the thermal stress of the ESC may be absorbed into the buffer layer in the ESC, so that the crack caused by the thermal stress may be sufficiently reduced, thereby increasing the durability life of the ESC. In order to make the above description of the present invention more comprehensible, the following detailed description of the preferred embodiments of the present invention will be described in detail below. For example, several embodiments of the invention are shown in the drawings. However, the invention may be embodied in many different forms and should not be construed as being limited to the implementation examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The size and relative dimensions of several layers and several regions can be exaggerated in the drawings. Above, we will understand that when a component or layer is referred to as "in", "connected" or "coupled to" another In the case of an element or layer, it may be that "1" is attached to it, connected or coupled to another element or layer or a layer or layer may be present. In contrast, when an element is referred to as being "above", "directly connected" or "directly coupled" to another element or layer, no intervening element or layer exists. Throughout the full text, the same reference number table is not the same. As used herein, the term "and /戋201021154 contains one or more related listed items. The occupant will understand that although the term _:d is used here to describe the various components, components, The elements, components, regions, layers and/or parts are not limited to these two terms. These terms are only used to distinguish one element, component, region, layer or part from another. A first element, component, region, layer or section may be referred to as a second element, component, region, layer or section, without departing from the teachings of the invention. This may use spatially specific terms such as "below", "below", "below", "above", "above", etc., in order to simplify the description of the components shown in the figure. Or the relationship between a feature and another component or feature. It will be understood that the space-specific terminology is intended to be used in a different orientation than the one described in the figure. For example, if the device in the figure is flipped, the meta-green of "located in the other component's material department or underneath" will be changed to "beyond the other 7 parts or features". Therefore, the exemplified terminology includes the orientation above or below. This device may be re-scaled or located at other values, and the spatially relative narration used herein is therefore explained. For example, the specific language is only used to illustrate the specific implementation of the demonstration ===: the limit of this r. As used herein, the formula. In the case of I, the number of the early forms is also included in the plural form. When it is too cut: the step is to understand the specific terms "including" and / or "including; when used in the book, specify the characteristics, integers , 9 201021154
i W^032PA 步驟、運作、元件，及/或組件之存在，但並未阻止一個 或多個其他特徵、整數、步驟、運作、元件、組件及/或 其群組之存在或添加。 於此參考剖面圖例（其係為理想化實施示範例（與中 間構造）之示意圖）來說明實施示範例。如此，從譬如由製 造技術及/或公差之結果所造成之圖例之形狀之變化是可 預期的。因此，實施示範例不應被解釋成受限於於此所顯 示之區域之特定形狀，但係用以包含譬如由製造引起的形 狀之偏差。舉例而言’顯示為矩形之植入區，一般是具有 圓形或曲線特徵及/或於其邊緣處之植入濃度梯度而非從 植入區到非植入區之二元改變（binary change)e同樣地， 藉由植入而形成之埋入區可能導致在埋入區以及經由其 發生植入之表面之間的區域中之某些植入。因此，顯示於 圖中之區域本質上係為概要的，而它們的形狀並非意圖顯 示裝置之區域之實際形狀，且並非意圖限制本發明之範 除非另有定義，否則於此所使用之所有專門用語（包 含技術與科學用語）具有與本發明所屬之其中一個熟習本 項技藝者所通常理解相同的意思。吾人將更進一步理解到 例如定義在常用字典中之那些專門用語應被解釋成具有 下述意思’其係與相關技術之上下文中的它們的意思相符 且將不會以一種理想化或過度形式的意識被解釋，除非於 此特別如此定義。 以下’將參考附圖而詳細說明實施示範例。 201021154 .i yy j〇pz.r/\ 第2圖係為顯示依據本發明的概念之實施示範例之 靜電夾頭之剖面圖。 參見第2圖，依據本發明的概念之實施示範例之靜電 夾頭（ESC)200可包含：一本體2〇1 ; —基底平板202，安 裝於本體201上並包含一電極2〇3於其中；一端子單元， 包含一端子204與一絕緣構件205，端子204用以從一外 部電源（未顯示）施加一高電壓至電極2〇3’而絕緣構件205 包圍端子204 ·’以及一緩衝層206，用以吸收本體201之 ❹熱應力。於處理腔室中可將待被處理之基板（未顯示）固定 地安置於基底平板202上，並可將緩衝層206安置於本體 201與基底平板202之邊界區域之至少一部分。 於一實施示範例中，本體201可包含例如鋁之導電材 料’並發揮ESC 200之基礎支撐之功能。可於本體2〇1之 中央部分製備一穿孔207，並可將具有端子2〇4與絕緣構 件205之端子單元插入至穿孔207，從而可貫通本體201。 ❿ 於一實施示範例中’基底平板202可包含一介電材 料，並可能藉由大氣所致的電漿喷灑（APS)塗佈製程而塗 佈於本體201上。基底平板202可包含具有介電材料之陶 瓷材料。陶瓷材料之例子可包含氧化鋁（A1203)、氧化釔 (Y203)、氧化鋁（A1203)與氧化釔（Y203)之複合物、二氧 化鍅（Zr02)、碳化鋁（A1C)、氮化鈦（錫）、氮化鋁（A1N)、 碳化鈦（TiC)、氧化錢（MgO)、氧化#§(CaO)、氧化鈽 (Ce02)、氧化鈦（Ti02)、碳化蝴（BxCy)、氮化鄉（BN)、二 氧化石夕（Si02)，碳化碎（SiC)、紀銘石權石（YAG， 11 201021154 ·♦ » Y3A15012)、富鋁紅柱石（鋁矽酸鹽，3A12〇3.2Si〇3)、氟 化铭（A1F3)等。這些可被單獨使用或組合使用。 藉由靜電力’可將基板固定至基底平板202，並固定 地定位基板’而靜電力可能藉由被施加至裝設於基底平板 202之内部中之電極203之電力而產生。基底平板202之 上表面可能是平的’從而使基板可能水平地安置於基底平 板202上。於本實施示範例中，可將電極203裝設成實質 上平行於基底平板202之上表面。 可將一插入部208設置於基底平板202之一中央部 ❿ 分’並可將與端子204插入至插入部208。端子204可經 由基底平板202之插入部208而與電極203接觸。因此， 可經由穿孔207而將端子204插入至本體201，並可經由 基底千板2 0 2之插入部2 0 8而將端子2 0 4延伸至電極2 0 3。 亦即’可經由本體201之穿孔207與基底平板202之插入 部208而將端子204連接至電極203。 如上所述’可將電極203裝設於基底平板202中，並 可經由端子204而將高電壓施加至電極203。因此，可將 ⑩ 靜電力施加至基底平板202上之基板，並可將基板固定至 基底平板202。亦即，可藉由靜電力而將基板固定地定位 於基底平板202上。 舉例而言，電極203可包含例如鎳（Ni)之導電材料。 在本實施示範例中，藉由連續的大氣所致的電漿喷灑 (APS)製程，可將電極203形成於基底平板202中。首先， 可藉由一第一 APS塗佈製程而將一下基底平板202a形成 12 201021154 於本體201上，並可藉由一 APS塗佈製程或一網印製程來 將一電極層（未顯示）形成於下基底平板2〇2a上。藉由圖 案化製程’電極層可能於下基底平板2〇2a上被製作成電 極203。然後，可藉由一第二ApS塗佈製程而在下基底平 板202a上形成一上基底平板202b達到足夠厚度以覆蓋電 極 203 〇 舉例而言，可使下基底平板202a形成達到大約4〇〇μιη 至大約6〇〇μηι之厚度，而電極203可具有大約5μιη至大 約65μΓη之厚度。又，上基底平板2〇2b可能形成達到大約 400μιη至大約750μιη之厚度。 端子204可經由穿孔207與插入部2〇8而連接至電極 203，並可從一外部電源（未顯示）經由端子2〇4而將高電 壓施加至電極203。端子204可包含例如鎢（w)、鉬^) 與鈦（Ti)之導電金屬材料。 於一實施示範例中，絕緣構件2〇5可能介設於本體 參201與端子204之間，從而使本體2〇1與端子2〇4可彼此 電氣絕緣。舉例而言，絕緣構件2〇5可包含一種燒結之陶 瓷材料，因為燒結之陶瓷材料中具有非常少的孔隙率，從 而使在本體201與端子204之間之電氣絕緣得以最大化。 舉例而言，絕緣構件205可具有大約2, 〇〇〇μηι之厚 度，並具有大約0· Ιμιη至大約2μιη之表面粗糙度，俾能使 表面電阻最小化，並避免電弧。於本例子中，絕緣構件2〇5 可具有大約Ιμιη或更少之表面粗糙度。 於一實施示範例中，可將緩衝層2〇6安置於本體2〇1 13 201021154 與絕緣構件205之一第一邊界區域之一部分，於基底平板 202與絕緣構件205之一第二邊界區域，以及於基底平板 202與端子204之一第三邊界區域。舉例而言，緩衝層2〇6 可包含一陶瓷材料。陶瓷材料之例子可包含氧化鋁 (A1203)、氧化釔（Y203)、氧化鋁（A1203)與氧化釔（γ2〇3) 之複合物、二氧化锆（Zr〇2)、碳化鋁（A1C)、氮化鈦（錫）、 氮化鋁（A1N)、碳化鈦（TiC)、氧化鎂（Mg0)、氧化鈣（Ca〇)、 氧化鈽（Ce02)、氧化鈦（Ti02)、碳化硼（BxCy)、氮化硼 (BN)、氧化石夕（Si02)、碳化石夕（SiC)、纪銘石權石（yag， Y3A15012)、富鋁紅柱石（鋁矽酸鹽，3A12〇3.2Si〇3)、氟 化鋁（A1F3)等。這些可被單獨使用或組合使用。緩衝層206 可能藉由APS塗佈製程而形成於第一、第二及第三邊界區 域。 舉例而言，緩衝層206可具有大約ι〇〇μιη至大約 250μιη之厚度’更好是大約15〇μιη至大約2〇〇μιη之厚度。 當緩衝層206可具有大於大約250μιη之厚度時，孔隙很可 能良好地產生於缓衝層206中’其將導致在緩衝層2〇6中 之龜裂，雖然其小於大約ΙΟΟμιη，但是緩衝層206將傾向 於如此薄’以致於緩衝層206可能難以吸收本體2〇1之熱 應力。 … 此外’類似於絕緣構件205 ’緩衝層2〇6可具有大約 〇· Ιμιη至大約2μιη之表面粗糙度，俾能使表面電阻最小化 並避免電弧。於本例中’緩衝層206可具有大約ιμιη或更 少之表面粗糙度。 201021154 緩衝層206可吸收靜電夾頭200之熱應力，其可能由 在一電漿沈積製程或一電漿蝕刻製程期間之溫升所導 致。雖然習知之ESC鋁本體可能由於習知ESC在電漿製程 中之高溫而熱膨脹，且各種熱應力可能被施加至習知之 ESC，但是在同一電漿製程中之本發明之ESC之本體之熱 膨脹可能會被吸收進入緩衝層206中。因此，無法將ESC 之本體之熱應力施加至絕緣構件。更明確而言，可藉由緩 衝層206來充分避免到達ESC之一邊緣點（對應至第1圖 ® 之部分A)之應力濃度，從而避免在ESC之本體201與絕緣 構件205之間之邊界區域之龜裂，藉以增加ESC之耐久性 壽命。 於本實施示範例中，緩衝層206之孔隙率可能等於 或高於基底平板202之孔隙率，藉以使熱應力之吸收最大 化，並使ESC之龜裂最小化。亦即，缓衝層206之孔隙率 可能等於或高於下基底平板202a或上基底平板202b之孔 鲁隙率。舉例而言’緩衝層206可具有大約2%至大約10%之 孔隙率，更好是大約2%至大約7%之孔隙率。當緩衝層206 之孔隙率可能超過大約10%時，在緩衝層中之孔隙率傾向 於過度，這會減少缓衝層206之強度，且最後會使緩衝層 206與絕緣構件205和基底平板202分離。當孔隙率低於 大約2%時，容易與急速地產生龜裂，以致於可能使緩衝層 206難以吸收熱應力。 又，缓衝層206之邊緣部分可能被形成為圓形或被倒 角，從而將尖銳部分移離緩衝層206。當緩衝層包含尖銳 15 201021154 邊緣部分時，熱應力可能集中於尖銳部分，而龜裂可能從 緩衝層206之尖銳邊緣部分急速成長。 再請參照第2圖，由於在ESC 2〇〇之中央部分之本 ，201之傾斜部S，使得下基底平板202a之中央厚度A可 能大於下基底平板2〇2a之周邊厚度B。因此，下基底平板 202a在ESC 200之中央部分之密度可能小於在Esc 2〇〇之 周邊部分之密度。然而，由於下基底平板2〇%之較大厚 度，可充分減少經由位於ESC 2〇〇之中央部分之下基底平 板202a之孔隙之電流洩漏，藉以避免在本體2〇1與電極❹ 203之間形成弧狀（arcing)。 此外，因為下基底平板2〇2a於ESC 200之中央部分 可具有較大厚度，所以可充分避免龜裂產生於本體2〇1與 絕緣構件205之第一邊界區域，藉以避免在本體2〇1與電 極203之間形成弧狀（arcing)。 一黏著層（未顯示）可能介設於本體201與下基底平 板202a之間’藉以堅穩地固定本體2〇1與下基底平板202a 至彼此。黏著層之熱係數可能在本體之熱係數與下基底平❹ 板202a之熱係數之間改變，從而使本體2〇1之熱應力可 能被吸收至黏著層’且無法整體被施加至下基底平板 202a。黏著層可包含例如錄-銘合金之金屬合金。 請再參見第2圖，下基底平板202a可能以下述配置 而形成於本體201、端子204與絕緣構件205上：下基底 平板202a之一上表面可能高於位在ESC 200之周邊部分 之端子204之上表面。因此’上基底平板202b在ESC之 201021154i W^032PA The existence of steps, operations, components, and/or components, but does not prevent the presence or addition of one or more other features, integers, steps, operations, components, components, and/or groups thereof. Embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized implementation examples (and intermediate structures). Thus, variations in the shape of the legend resulting from, for example, manufacturing techniques and/or tolerances are contemplated. Therefore, the examples are not to be construed as limited to the specific shapes of the regions shown herein. For example, an implanted area that is shown as a rectangle, typically having a circular or curved feature and/or an implant concentration gradient at its edges rather than a binary change from the implanted to the non-implanted region (binary change) Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which implantation occurs. Therefore, the regions shown in the figures are generally in the nature and their shapes are not intended to represent the actual shape of the region of the device, and are not intended to limit the scope of the invention unless otherwise defined. The terms (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. We will further understand that, for example, those specific terms defined in commonly used dictionaries should be interpreted as having the following meanings 'these are consistent with their meaning in the context of the related art and will not be in an idealized or excessive form. Consciousness is explained unless it is specifically defined as such. The following description will be described in detail with reference to the accompanying drawings. 201021154 .i yy j〇pz.r/\ Fig. 2 is a cross-sectional view showing an electrostatic chuck according to an exemplary embodiment of the concept of the present invention. Referring to FIG. 2, an electrostatic chuck (ESC) 200 according to an exemplary embodiment of the inventive concept may include: a body 2〇1; a substrate plate 202 mounted on the body 201 and including an electrode 2〇3 therein A terminal unit includes a terminal 204 and an insulating member 205 for applying a high voltage from an external power source (not shown) to the electrode 2〇3' and the insulating member 205 surrounding the terminal 204·' and a buffer layer 206, for absorbing the thermal stress of the body 201. A substrate (not shown) to be processed may be fixedly disposed on the substrate plate 202 in the processing chamber, and the buffer layer 206 may be disposed on at least a portion of a boundary region between the body 201 and the substrate plate 202. In an exemplary embodiment, the body 201 may comprise a conductive material such as aluminum' and function as a base support for the ESC 200. A through hole 207 can be formed in the central portion of the body 2〇1, and the terminal unit having the terminal 2〇4 and the insulating member 205 can be inserted into the through hole 207 so as to penetrate the body 201. In an exemplary embodiment, the substrate plate 202 may comprise a dielectric material and may be applied to the body 201 by an atmospheric plasma spray (APS) coating process. The substrate plate 202 can comprise a ceramic material having a dielectric material. Examples of the ceramic material may include alumina (A1203), yttrium oxide (Y203), a composite of alumina (A1203) and yttrium oxide (Y203), cerium oxide (ZrO2), aluminum carbide (A1C), titanium nitride ( Tin), aluminum nitride (A1N), titanium carbide (TiC), oxidized money (MgO), oxidation #§(CaO), cerium oxide (Ce02), titanium oxide (Ti02), carbonized butterfly (BxCy), nitriding township (BN), SiO2 (Si02), carbonized ash (SiC), Jiming Shiquanshi (YAG, 11 201021154 ·♦ » Y3A15012), mullite (aluminum silicate, 3A12〇3.2Si〇3), Fluoride Ming (A1F3) and so on. These can be used alone or in combination. The substrate can be fixed to the substrate flat plate 202 by electrostatic force, and the substrate can be fixedly positioned, and electrostatic force can be generated by electric power applied to the electrode 203 installed in the interior of the base plate 202. The upper surface of the substrate plate 202 may be flat so that the substrate may be placed horizontally on the substrate plate 202. In the present embodiment, the electrode 203 may be disposed substantially parallel to the upper surface of the substrate plate 202. An insertion portion 208 can be disposed at a central portion of the base plate 202 and can be inserted into the insertion portion 208 with the terminal 204. Terminal 204 is in contact with electrode 203 via insertion portion 208 of substrate plate 202. Therefore, the terminal 204 can be inserted into the body 201 via the through hole 207, and the terminal 2 0 4 can be extended to the electrode 2 0 3 via the insertion portion 2 0 8 of the base plate 2 0 2 . That is, the terminal 204 can be connected to the electrode 203 via the through hole 207 of the body 201 and the insertion portion 208 of the base plate 202. The electrode 203 can be mounted in the base plate 202 as described above, and a high voltage can be applied to the electrode 203 via the terminal 204. Therefore, 10 electrostatic forces can be applied to the substrate on the substrate plate 202, and the substrate can be fixed to the substrate plate 202. That is, the substrate can be fixedly positioned on the substrate plate 202 by electrostatic force. For example, the electrode 203 may comprise a conductive material such as nickel (Ni). In the present embodiment, the electrode 203 can be formed in the substrate plate 202 by a plasma spray (APS) process by continuous atmosphere. First, the lower substrate plate 202a can be formed on the body 201 by a first APS coating process, and an electrode layer (not shown) can be formed by an APS coating process or a screen printing process. On the lower substrate plate 2〇2a. The electrode layer may be formed as an electrode 203 on the lower substrate plate 2〇2a by the patterning process. Then, an upper substrate plate 202b can be formed on the lower substrate plate 202a to a sufficient thickness to cover the electrode 203 by a second ApS coating process. For example, the lower substrate plate 202a can be formed up to about 4 μm to The thickness of about 6 μm may be, and the electrode 203 may have a thickness of about 5 μm to about 65 μm. Further, the upper substrate plate 2 2b may form a thickness of up to about 400 μm to about 750 μm. The terminal 204 can be connected to the electrode 203 via the through hole 207 and the insertion portion 2〇8, and can apply a high voltage to the electrode 203 via an external power source (not shown) via the terminal 2〇4. The terminal 204 may comprise a conductive metal material such as tungsten (w), molybdenum (), and titanium (Ti). In an exemplary embodiment, the insulating member 2〇5 may be interposed between the body 201 and the terminal 204 such that the body 2〇1 and the terminal 2〇4 are electrically insulated from each other. For example, the insulating member 2〇5 may comprise a sintered ceramic material because of the very low porosity in the sintered ceramic material, thereby maximizing the electrical insulation between the body 201 and the terminal 204. For example, the insulating member 205 may have a thickness of about 2, 〇〇〇μηι, and have a surface roughness of from about 0 μm to about 2 μm, which minimizes surface resistance and avoids arcing. In the present example, the insulating member 2〇5 may have a surface roughness of about Ιμη or less. In an exemplary embodiment, the buffer layer 2〇6 may be disposed on a portion of the first boundary region of the body 2〇1 13 201021154 and the insulating member 205 in a second boundary region between the substrate plate 202 and the insulating member 205. And a third boundary region between the substrate plate 202 and the terminal 204. For example, the buffer layer 2〇6 may comprise a ceramic material. Examples of the ceramic material may include alumina (A1203), yttrium oxide (Y203), a composite of alumina (A1203) and yttrium oxide (γ2〇3), zirconium dioxide (Zr〇2), aluminum carbide (A1C), Titanium nitride (tin), aluminum nitride (A1N), titanium carbide (TiC), magnesium oxide (Mg0), calcium oxide (Ca〇), cerium oxide (Ce02), titanium oxide (Ti02), boron carbide (BxCy) Boron nitride (BN), oxidized stone Xi (Si02), carbonized stone (SiC), Jiming stone (yag, Y3A15012), mullite (aluminum silicate, 3A12〇3.2Si〇3), fluorine Aluminum (A1F3) and the like. These can be used alone or in combination. The buffer layer 206 may be formed in the first, second, and third boundary regions by an APS coating process. For example, the buffer layer 206 may have a thickness of from about 1 μm to about 250 μm, more preferably from about 15 μm to about 2 μm. When the buffer layer 206 can have a thickness greater than about 250 μm, the voids are likely to be well produced in the buffer layer 206 'which will cause cracking in the buffer layer 2〇6, although it is less than about ΙΟΟμιη, but the buffer layer 206 It will tend to be so thin that the buffer layer 206 may be difficult to absorb the thermal stress of the body 2〇1. Further, similar to the insulating member 205', the buffer layer 2〇6 may have a surface roughness of about 〇·Ιμηη to about 2 μm, which minimizes surface resistance and avoids arcing. In this example, the buffer layer 206 may have a surface roughness of about ιηη or less. The 201021154 buffer layer 206 can absorb the thermal stress of the electrostatic chuck 200, which may be caused by a temperature rise during a plasma deposition process or a plasma etching process. Although the conventional ESC aluminum body may thermally expand due to the high temperature of the conventional ESC in the plasma process, and various thermal stresses may be applied to the conventional ESC, the thermal expansion of the body of the ESC of the present invention in the same plasma process may be Will be absorbed into the buffer layer 206. Therefore, the thermal stress of the body of the ESC cannot be applied to the insulating member. More specifically, the stress concentration of one of the edge points of the ESC (corresponding to part A of FIG. 1) can be sufficiently avoided by the buffer layer 206, thereby avoiding the boundary between the body 201 of the ESC and the insulating member 205. The crack in the area is used to increase the durability life of the ESC. In this embodiment, the porosity of the buffer layer 206 may be equal to or higher than the porosity of the substrate plate 202, thereby maximizing the absorption of thermal stress and minimizing cracking of the ESC. That is, the porosity of the buffer layer 206 may be equal to or higher than the porosity of the lower substrate plate 202a or the upper substrate plate 202b. For example, the buffer layer 206 can have a porosity of from about 2% to about 10%, more preferably from about 2% to about 7%. When the porosity of the buffer layer 206 may exceed about 10%, the porosity in the buffer layer tends to be excessive, which reduces the strength of the buffer layer 206, and finally separates the buffer layer 206 from the insulating member 205 and the substrate plate 202. . When the porosity is less than about 2%, cracks are easily and rapidly generated, so that it is possible to make the buffer layer 206 difficult to absorb thermal stress. Also, the edge portion of the buffer layer 206 may be formed to be circular or chamfered to move the sharp portion away from the buffer layer 206. When the buffer layer contains the sharp 15 201021154 edge portion, thermal stress may concentrate on the sharp portion, and the crack may rapidly grow from the sharp edge portion of the buffer layer 206. Referring again to Fig. 2, the center thickness A of the lower base plate 202a may be larger than the peripheral thickness B of the lower base plate 2〇2a due to the inclined portion S of the center portion of the ESC 2〇〇. Therefore, the density of the lower substrate plate 202a in the central portion of the ESC 200 may be smaller than the density at the peripheral portion of the Esc 2 inch. However, due to the large thickness of the lower base plate 2%, the current leakage through the aperture of the base plate 202a under the central portion of the ESC 2〇〇 can be sufficiently reduced to avoid between the body 2〇1 and the electrode 203203. Form an arcing. In addition, since the lower base plate 2〇2a can have a large thickness in the central portion of the ESC 200, it is possible to sufficiently prevent the crack from being generated in the first boundary region between the body 2〇1 and the insulating member 205, thereby avoiding the body 2〇1. An arcing is formed with the electrode 203. An adhesive layer (not shown) may be interposed between the body 201 and the lower substrate plate 202' by which the body 2〇1 and the lower substrate plate 202a are firmly fixed to each other. The thermal coefficient of the adhesive layer may vary between the thermal coefficient of the body and the thermal coefficient of the lower substrate flat plate 202a, so that the thermal stress of the body 2〇1 may be absorbed to the adhesive layer' and cannot be applied to the lower substrate flat as a whole. 202a. The adhesive layer may comprise a metal alloy such as a recording alloy. Referring to FIG. 2 again, the lower substrate plate 202a may be formed on the body 201, the terminal 204 and the insulating member 205 in a configuration in which the upper surface of one of the lower substrate plates 202a may be higher than the terminal 204 located at the peripheral portion of the ESC 200. Above the surface. Therefore, the upper substrate plate 202b is at ESC 201021154
.1W5632FA 中央部分之中央厚度C可能大於在ESC 200之周邊部分之 -周邊厚度D。因此，當可能經由端子2Q4而將高電壓施 加至電極簡時’可充分避免在電極203與安置於上基底 平板202b上之基板之間之電弧。 以下，可詳細說明顯示於第2圖之ESC 200之製造方 法。.1W5632FA The central thickness C of the central portion may be greater than the peripheral thickness D of the peripheral portion of the ESC 200. Therefore, an arc between the electrode 203 and the substrate disposed on the upper substrate plate 202b can be sufficiently avoided when it is possible to apply a high voltage to the electrode via the terminal 2Q4. Hereinafter, the manufacturing method of the ESC 200 shown in Fig. 2 can be explained in detail.
首先，可將端子單元裝設至本體2〇1。端子單元可包 含端子204、絕緣構件2〇5與緩衝層2〇6。在操作esc 2〇〇 時，端子204可電連接至一外部電源。絕緣構件可包 圍端子204，從而可使本體201與端子2〇4達到彼此電氣 絕緣。緩衝層206可能形成於絕緣構件205之一部分上， 並可吸收在ESC 200中之熱應力，藉以減少由於熱:力所 導致之ESC 200之龜裂。 … 具有一預先決定的尺寸與形狀之一絕緣體（未顯示） 可被處理，且端子204可個別被製備。然後，可將端子2〇4 插入至並穿過被處理之絕緣體，從而使端子2〇4與絕緣體 之組合可利用端子可能局部地被絕緣體封閉之這樣的配 置而設置。包圍端子204之絕緣體可發揮絕緣構件2〇5之 功能。然後，可將緩衝層206形成於端子2〇4之一部分上。 舉例而言，可將絕緣體移離端子2〇4之末端部分，^藉"7以於 端子204形成緩衝區域。於端子2〇4之末端部分，可將緩 衝層206形成於緩衝區域上。 、 此外，端子204與絕緣構件205之邊緣部分可能形成 為圓形或被倒角。然'後，可藉由—平坦化製輕而將缓衝層 17 201021154First, the terminal unit can be mounted to the body 2〇1. The terminal unit may include a terminal 204, an insulating member 2〇5, and a buffer layer 2〇6. Terminal 204 can be electrically connected to an external power source when esc 2〇〇 is operated. The insulating member may surround the terminal 204 so that the body 201 and the terminal 2〇4 are electrically insulated from each other. The buffer layer 206 may be formed on a portion of the insulating member 205 and may absorb thermal stress in the ESC 200 to reduce cracking of the ESC 200 due to heat: force. An insulator (not shown) having a predetermined size and shape can be processed, and the terminals 204 can be separately prepared. Terminal 2〇4 can then be inserted into and through the insulator being treated so that the combination of terminal 2〇4 and insulator can be provided in such a configuration that the terminal may be partially enclosed by an insulator. The insulator surrounding the terminal 204 functions as the insulating member 2〇5. Then, a buffer layer 206 may be formed on a portion of the terminal 2〇4. For example, the insulator can be moved away from the end portion of the terminal 2〇4, and the terminal 204 can form a buffer region. At the end portion of the terminal 2〇4, the buffer layer 206 can be formed on the buffer region. Further, the terminal portion 204 and the edge portion of the insulating member 205 may be formed in a circular shape or chamfered. After that, the buffer layer can be made by flattening the light 17 201021154
1W5632FA 206平坦化，藉以縮小表面粗糙度。包含端子2〇4、絕緣 構件205與緩衝層206之端子單元可能貫穿本體2〇1之穿 孔207，藉以結合端子單元與本體201。 然後’基底平板202可能依據以下配置而形成於本體 201上：使電極203可能裝設於基底平板202之内部中。 亦即’下基底平板202a係首先形成於本體201上，而電 極層（未顯示）可能形成於下基底平板202a上。電極層可 能被圖案化成為於下基底平板202a上之電極203。然後， 上基底平板202b形成在下基底平板202a上，以達到足夠 的厚度來覆蓋電極203。 更明確而言，可分別於下基底平板202a之表面上， 於電極層之表面上，以及於上基底平板202b之表面上執 行平坦化製程’藉以充分縮小表面粗糙度及增加表面平滑 度0 於本實施示範例中’下基底平板202a可能依據以下 配置而形成於本體201上：使貫穿本體201之端子204之 一上表面無法被下基底平板202a覆蓋。舉例而言，在形 成下基底平板202a之前，可提早形成一遮罩層（未顯示） 於端子204之上表面上，並可在形成下基底平板2〇2a以 後，將遮罩層移離端子204。否則，一預備下基底平板（未 顯示）可能形成於本體201上，且預備下基底平板之一中 央部分可能局部被移離本體201，藉以形成一開口（未顯 示），使端子204之上表面經由此開口露出。 依據某些實施示範例，ESC之熱應力可能被吸收至 201021154 ESC ^之緩衝層’從而可能充分減少由熱應力所導致的龜 裂，藉以增加Esc之耐久性壽命。 參 甘^，迷内各係用以說明實施示範例，且並非被解釋成對 , 特別限制。雖然已說明一些實施示範例，但是熟習 ㈣者將輕易地明白到，在實質上不背離本發明之嶄 =教導與優_情況τ，仍可崎實施示_作出各種變 ^。因此，所有的這些變形例係意圖被涵蓋在在申請專 中範，中所界定的本發明之範脅之内。在_請專利範圍 加魏子句_涵蓋朗於此之構造，如執行引 :之功能’以及*但是構造料效設計 造。因此，吾人應理_上心 且對於所揭露之實施示_歸㈣之特疋實施不範例’ 示範例係意圖被涵蓋細下的^=形例以及其他實施 的申清專利範圍之範疇之内。 【圖式簡單說明】 第1圖係為顯示在處理腔室中之習知之靜電央頭之 剖面圖。 第2圖係為顯示依據本發明的概念之實施示範例之 靜電夾頭之剖面圖。 【主要元件符號說明】 A ·上端部/上部/中央厚度 B.周邊厚度The 1W5632FA 206 is flattened to reduce surface roughness. The terminal unit including the terminal 2〇4, the insulating member 205 and the buffer layer 206 may penetrate the through hole 207 of the body 2〇1, thereby bonding the terminal unit and the body 201. The substrate plate 202 may then be formed on the body 201 in accordance with the configuration that the electrode 203 may be mounted in the interior of the substrate plate 202. That is, the lower substrate plate 202a is first formed on the body 201, and an electrode layer (not shown) may be formed on the lower substrate plate 202a. The electrode layer may be patterned into the electrode 203 on the lower substrate plate 202a. Then, the upper substrate plate 202b is formed on the lower substrate plate 202a to have a sufficient thickness to cover the electrode 203. More specifically, the planarization process can be performed on the surface of the lower substrate plate 202a, on the surface of the electrode layer, and on the surface of the upper substrate plate 202b to sufficiently reduce the surface roughness and increase the surface smoothness. In the present exemplary embodiment, the lower substrate plate 202a may be formed on the body 201 according to the following configuration: the upper surface of one of the terminals 204 penetrating the body 201 cannot be covered by the lower substrate plate 202a. For example, a mask layer (not shown) may be formed on the upper surface of the terminal 204 before the lower substrate plate 202a is formed, and the mask layer may be removed from the terminal after forming the lower substrate plate 2〇2a. 204. Otherwise, a preparatory lower substrate plate (not shown) may be formed on the body 201, and a central portion of the preliminary lower substrate plate may be partially removed from the body 201, thereby forming an opening (not shown) for the upper surface of the terminal 204. It is exposed through this opening. According to certain embodiments, the thermal stress of the ESC may be absorbed into the buffer layer of 201021154 ESC^, thereby possibly reducing the crack caused by thermal stress, thereby increasing the durability life of the Esc. References are made to illustrate the implementation of the examples and are not to be construed as being limiting, particularly limited. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that various changes can be made without departing from the invention. Accordingly, all such variations are intended to be included within the scope of the present invention as defined in the application. In the scope of the _ patent, the addition of the Wei clause _ covers the structure of this, such as the implementation of the function: and * but the construction efficiency design. Therefore, we should take care of it and make a demonstration of the implementation of the disclosure. The example is intended to be covered by the finest ^= shape and other implementation scope of the patent scope. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional electrostatic head shown in a processing chamber. Figure 2 is a cross-sectional view showing an electrostatic chuck according to an exemplary embodiment of the concept of the present invention. [Description of main component symbols] A · Upper end / upper / center thickness B. Peripheral thickness
201021154 TW5632FA C :中央厚度 D :周邊厚度 S :傾斜部 100 :靜電夾頭 101 :本體 102 :基底平板 103 :電極 104 :端子 105 :絕緣構件 200 :靜電夾頭 201 :本體 202 :基底平板 202a :下基底平板 202b :上基底平板 203 :電極 204 :端子 205 :絕緣構件 206 :緩衝層 207 :穿孔 208 :插入部201021154 TW5632FA C : central thickness D : peripheral thickness S : inclined portion 100 : electrostatic chuck 101 : body 102 : base plate 103 : electrode 104 : terminal 105 : insulating member 200 : electrostatic chuck 201 : body 202 : base plate 202a : Lower substrate plate 202b: upper substrate plate 203: electrode 204: terminal 205: insulating member 206: buffer layer 207: perforation 208: insertion portion
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080088972A KR100995250B1 (en) | 2008-09-09 | 2008-09-09 | Electrostatic chuck containing buffer layer for reducing thermal stress |
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| Publication Number | Publication Date |
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| TW201021154A true TW201021154A (en) | 2010-06-01 |
| TWI401768B TWI401768B (en) | 2013-07-11 |
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| KR (1) | KR100995250B1 (en) |
| CN (2) | CN103227138A (en) |
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| WO (1) | WO2010030102A2 (en) |
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| KR101974386B1 (en) * | 2012-03-21 | 2019-05-03 | 주식회사 미코 | Electrode static chuck |
| KR102119867B1 (en) * | 2013-10-21 | 2020-06-09 | 주식회사 미코세라믹스 | Electrostatic chuck |
| US11420278B2 (en) * | 2018-06-28 | 2022-08-23 | Spirit Aerosystems, Inc. | System and method employing active thermal buffer element for improved joule heating |
| JP7162500B2 (en) * | 2018-11-09 | 2022-10-28 | 株式会社Kelk | Temperature controller |
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| EP0899986B1 (en) * | 1996-05-05 | 2004-11-24 | Tateho Chemical Industries Co., Ltd. | Electric heating element and electrostatic chuck using the same |
| JP4173212B2 (en) * | 1997-10-08 | 2008-10-29 | 東京エレクトロン株式会社 | Holding device and processing apparatus equipped with holding device |
| JP3771722B2 (en) * | 1998-07-31 | 2006-04-26 | 京セラ株式会社 | Wafer support member |
| CN1207939C (en) * | 1999-09-29 | 2005-06-22 | 东京电子株式会社 | Multi-zone resistance heater |
| JP3859914B2 (en) * | 1999-10-08 | 2006-12-20 | 東芝セラミックス株式会社 | Ceramic-metal composite part having metal terminal and method for manufacturing the same |
| JP2001287130A (en) * | 2000-04-07 | 2001-10-16 | Taiheiyo Cement Corp | Electrostatic chuck device and its manufacturing method |
| JP2001313331A (en) * | 2000-04-28 | 2001-11-09 | Sumitomo Osaka Cement Co Ltd | Electrostatic attraction device |
| JP4753460B2 (en) * | 2000-08-16 | 2011-08-24 | 株式会社クリエイティブ テクノロジー | Electrostatic chuck and manufacturing method thereof |
| US7161121B1 (en) * | 2001-04-30 | 2007-01-09 | Lam Research Corporation | Electrostatic chuck having radial temperature control capability |
| KR20030044499A (en) * | 2001-11-30 | 2003-06-09 | 삼성전자주식회사 | Electro static chuck and Method of Manufacturing Thereof |
| JP4510745B2 (en) * | 2005-10-28 | 2010-07-28 | 日本碍子株式会社 | Bonding structure of ceramic substrate and power supply connector |
| KR101066798B1 (en) * | 2006-03-14 | 2011-09-23 | 엘아이지에이디피 주식회사 | Esc, support table, chamber and the manufacture methods thereof |
| US7701693B2 (en) * | 2006-09-13 | 2010-04-20 | Ngk Insulators, Ltd. | Electrostatic chuck with heater and manufacturing method thereof |
| WO2008035395A1 (en) * | 2006-09-19 | 2008-03-27 | Creative Technology Corporation | Feeding structure of electrostatic chuck, method for producing the same, and method for regenerating feeding structure of electrostatic chuck |
-
2008
- 2008-09-09 KR KR1020080088972A patent/KR100995250B1/en active IP Right Grant
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- 2009-09-07 TW TW098130090A patent/TWI401768B/en active
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| KR100995250B1 (en) | 2010-11-18 |
| CN102150233B (en) | 2014-10-15 |
| WO2010030102A3 (en) | 2010-07-01 |
| TWI401768B (en) | 2013-07-11 |
| CN103227138A (en) | 2013-07-31 |
| WO2010030102A2 (en) | 2010-03-18 |
| CN102150233A (en) | 2011-08-10 |
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