TW201017421A - Cache memory, memory system and control method therefor - Google Patents

Cache memory, memory system and control method therefor Download PDF

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Publication number
TW201017421A
TW201017421A TW098130538A TW98130538A TW201017421A TW 201017421 A TW201017421 A TW 201017421A TW 098130538 A TW098130538 A TW 098130538A TW 98130538 A TW98130538 A TW 98130538A TW 201017421 A TW201017421 A TW 201017421A
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TW
Taiwan
Prior art keywords
memory
command
cache
data
write
Prior art date
Application number
TW098130538A
Other languages
English (en)
Chinese (zh)
Inventor
Takanori Isono
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of TW201017421A publication Critical patent/TW201017421A/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW098130538A 2008-09-24 2009-09-10 Cache memory, memory system and control method therefor TW201017421A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008244963 2008-09-24

Publications (1)

Publication Number Publication Date
TW201017421A true TW201017421A (en) 2010-05-01

Family

ID=42059438

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098130538A TW201017421A (en) 2008-09-24 2009-09-10 Cache memory, memory system and control method therefor

Country Status (5)

Country Link
US (1) US20110173393A1 (ja)
JP (1) JPWO2010035425A1 (ja)
CN (1) CN102165424A (ja)
TW (1) TW201017421A (ja)
WO (1) WO2010035425A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9075725B2 (en) 2010-06-09 2015-07-07 Micron Technology, Inc. Persistent memory for processor main memory
US9317450B2 (en) 2010-09-30 2016-04-19 Micron Technology, Inc. Security protection for memory content of processor main memory
US9448938B2 (en) 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories

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US8719506B2 (en) 2011-11-21 2014-05-06 Apple Inc. Push mechanism for quality of service (QoS) support in coherency port
CN103138912B (zh) * 2011-12-05 2016-08-03 阿里巴巴集团控股有限公司 数据同步方法及系统
US9053058B2 (en) 2012-12-20 2015-06-09 Apple Inc. QoS inband upgrade
KR102149222B1 (ko) * 2013-09-26 2020-10-14 삼성전자주식회사 캐시를 이용한 데이터 복사 방법 및 그 장치
CN105630698A (zh) * 2014-10-28 2016-06-01 华为技术有限公司 配置扩展缓存的方法、装置及扩展缓存
EP3224729A1 (en) * 2014-11-25 2017-10-04 Lantiq Beteiligungs-GmbH & Co. KG Memory management device
CN106856663B (zh) * 2015-10-01 2022-01-07 瑞萨电子株式会社 半导体装置
KR20170075396A (ko) * 2015-12-23 2017-07-03 고려대학교 산학협력단 메모리 시스템
CN107145337B (zh) * 2016-03-01 2021-06-29 中兴通讯股份有限公司 一种数据流处理芯片的表项访问方法及装置
CN109101439B (zh) * 2017-06-21 2024-01-09 深圳市中兴微电子技术有限公司 一种报文处理的方法及装置
JP7000748B2 (ja) 2017-09-04 2022-01-19 富士フイルムビジネスイノベーション株式会社 画像処理装置、半導体装置及びプログラム
JP6946168B2 (ja) * 2017-12-22 2021-10-06 ルネサスエレクトロニクス株式会社 半導体装置
CN110058783B (zh) * 2018-01-17 2022-04-12 瑞昱半导体股份有限公司 暂存存储器处理方法、暂存存储器程序与存储装置
US11080211B2 (en) * 2018-12-12 2021-08-03 Arm Limited Storing data from low latency storage

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US4603380A (en) * 1983-07-01 1986-07-29 International Business Machines Corporation DASD cache block staging
JPH05257805A (ja) * 1992-01-14 1993-10-08 Hitachi Ltd キャッシュメモリ制御方式
JPH0797352B2 (ja) * 1992-07-02 1995-10-18 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システム及び入出力コントローラ
US6868472B1 (en) * 1999-10-01 2005-03-15 Fujitsu Limited Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory
KR100798020B1 (ko) * 2000-04-12 2008-01-24 엔엑스피 비 브이 데이터 처리 회로, 데이터 처리 회로를 포함하는 장치, 그리고 장치를 위한 컴퓨터 독출 가능 저장 매체
JP4822598B2 (ja) * 2001-03-21 2011-11-24 ルネサスエレクトロニクス株式会社 キャッシュメモリ装置およびそれを含むデータ処理装置
JP4114915B2 (ja) * 2002-05-24 2008-07-09 株式会社ルネサステクノロジ データ処理装置及びデータ処理システム
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EP1698978A4 (en) * 2003-12-22 2008-11-05 Matsushita Electric Ind Co Ltd CACHE MEMORY AND CONTROL PROCEDURE THEREFOR
US7490117B2 (en) * 2003-12-31 2009-02-10 Intel Corporation Dynamic performance monitoring-based approach to memory management
US7260688B1 (en) * 2004-04-15 2007-08-21 Xilinx, Inc. Method and apparatus for controlling access to memory circuitry
US20060112226A1 (en) * 2004-11-19 2006-05-25 Hady Frank T Heterogeneous processors sharing a common cache
DE102005037219A1 (de) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9075725B2 (en) 2010-06-09 2015-07-07 Micron Technology, Inc. Persistent memory for processor main memory
US9384134B2 (en) 2010-06-09 2016-07-05 Micron Technology, Inc. Persistent memory for processor main memory
US9448938B2 (en) 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories
US9317450B2 (en) 2010-09-30 2016-04-19 Micron Technology, Inc. Security protection for memory content of processor main memory

Also Published As

Publication number Publication date
JPWO2010035425A1 (ja) 2012-02-16
CN102165424A (zh) 2011-08-24
WO2010035425A1 (ja) 2010-04-01
US20110173393A1 (en) 2011-07-14

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