TW201015763A - Dielectric mesh isolated phase change structure for phase change memory - Google Patents

Abstract

A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Description

201015763 >9twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a chalcogenide materials type memory device and a method of manufacturing the same. [Prior Art] A phase change type memory material such as a chalcogen material and the like may apply an electric current at a level suitable for implementation in an integrated circuit to cause an amorphous state ( Phase change between amorphous state and crystalline state. The generally amorphous state is characterized by a higher electrical resistance than the general crystalline state, which is easy to sense and thus can indicate data. These features have generated interest in the use of programmable resistive materials to form non-volatile memory circuits that are read and written in a random access manner.

Changing from an amorphous state to a crystalline state is generally a lower current operation. The operation referred to herein as resetting (prison t) from a crystalline state to an amorphous state is generally a higher current operation, including (10) high current density pulses to dissolve or dissolve the crystalline structure 'read to rapidly cool the phase transition (4) to Fire, variable process and allow at least a portion of the phase change material to be stabilized in an amorphous state by reducing the size of the phase change material element of the memory cell and the magnitude of the current between the decides and the phase change material. A higher current density is achieved by the phase change material. · Piece (10) small absolute current ^i.doc/n 201015763 However, due to the fault caused by the small contact surface, it is too much because of the paint sore because of the misrecording (Ge_S1>Te, GST). The crystalline state of human mosquitoes regulates the two crystalline states and causes stress on non-crusted and in gadolinium (GST) materials. The size of the flowable phase change material is doped. The temperature of the memory element (memoryelem) of the sulphur material of the scorpion 2, and the melting temperature and other Characteristics: Representative impurities used to hold the chalcogenide materials include H Oxygen, Oxidation Chop, Nitride Xi, Copper, Silver, Gold, Ming, Oxidation, Group, Oxidation, Nitriding, Titanium, and Emulsified Titanium. For example, the participating patents No. 6, _, 504 (metal doping) and U.S. Patent Application No. 2, 295 〇 2 (nitrogen doping).

U.S. Patent No. 6, 〇 87, 674 to Ovshinsky et al., and its patent parent, U.S. Patent No. 5,825, G46, describes how to form a composite memory material in which a phase change material and a southerly-concentrated dielectric are formed. The material is mixed to control the electrical resistance of the composite memory material. The nature of the composite memory materials described in these patents is not clear, as the composite materials are not only layered but also hybrid structures. The dielectric materials described in these patents contain a very wide range. Some researchers have studied how to use yttrium oxide to do so in a chalcogenide material in order to reduce the reset current required to operate a memory device. See Ryu et al., 2006, Electrochemical and Solid-State Letters ’ 9 (8) G259-G261, “Si〇2 Incorporation Effects in 201015763 w. (9twf.doc/n

"Separate domain formation in Ge2Sb2Te5 - SiOx mixed layer" by Lee et al. "Current Reduction in Ovonic Memory Devices" by E*PCOS06; and Noh

Et al., 2006, Mater. Res. Soc. Symp. Proc. 888, "Modification of Ge2Sb2Te5 by the Addition of SiOx for Improved Operation of Phase Change Random Access

Memory". These references indicate that doping a lower concentration of cerium oxide to a eucalyptus cement (Gejt^Te5) results in a substantial increase in electrical resistance and a corresponding reduction in reset current. The paper by Czubatyj et al. indicates that the resistance of the yttria-doped yttrium (GST) alloy improves the saturation point at about 丨〇 volume percent vol (vol° / 〇) (6.7 atomic percent (at 〇 / 0)), and It indicates that up to 30% by volume of yttrium oxide has been tested, but no details are provided. Le et al.'s article describes a phenomenon in which a higher doping concentration occurs at about 8.4 atomic percent, in which after the high temperature annealing, the oxidized stone j exhibits a separation from strontium (GST), thus forming a major The composition is the 锗锑碲 (GST) region surrounded by the boundary of the oxidation reserve. Related research has progressed to obtain a device operating at a low reset current by adjusting the structure of the phase change material to provide a very small size. The problem with the extremely small size of the phase change device is that the resistance is ', the amorphous is unstable to the crystalline state, and the memory of the phase change material is made doc/n 201015763 (11^111〇7〇^13) May be malfunctioning. For example, a memory cell in which the active area (: _1 > 〇 11) has been reset to a generally amorphous state may form a crystallization zone in the active area over a period of time. If these crystallization regions are joined to form a low resistance path across the active region, a lower resistance state will be detected when reading the memory cells, resulting in data errors. See Gleixner's "Phase Change Memory Reliability" in tutorial. 22nd NVSMW in 2007. SUMMARY OF THE INVENTION Accordingly, the present invention is intended to provide a memory cell having a small reset current and to solve the above problem of negative material storage while solving the problem of reliability of a small contact surface between the above electrode and the phase change material. SUMMARY OF THE INVENTION A method for manufacturing a memory device, in which the chalcogenide material of the doped oxide oxide is mixed with (4) money cells. The above method includes forming a first electrode having a contact surface; forming a phase change memory material body having a polycrystalline state in which the portion is in contact with the contact surface of the first electrode; and forming a second electrode in contact with the material body. The phase change memory material includes a chalcogenide material that pushes the dielectric material. The above process includes the formation of a dielectric material in the body of the phase change material that is not outside the active area. The grid has a region 'but the Na... demonstration, where the upper work == to the good = hundred devices The material of the electric material is characterized by the result of the formation of the ==201015763 "Jtwf.doc/n ring, the reduced grain size of the polycrystalline state, and the formation of at least one of the plurality of crystals corresponding to the polycrystalline state. . For the chalcogenide used, it is characterized by a plurality of solid crystalline phases, such as GexSbyTez, where x = 2, y = 2, and z = 5, these phases include face-centered cubic 'FCC solid state crystalline phases And the hexagonal close-packed (HCP) solid crystalline phase, at its concentration

It is avoided that a dielectric material of at least one of the above-described solid crystalline phases (e.g., hexagonal closest packed (HCP) solid crystalline phase) is formed in the body of material outside the active region to dope the chalcogenide material. Therefore, the chalcogenide material used in the phase change memory material is characterized by having a first volume of the first solid crystal = (eg, hexagonal closest packing (HCP)) and having a second volume when the dielectric is not doped. The second solid crystalline phase (eg, face centered cubic (FCC)), the volume of the amorphous phase phase change memory material is closer to the second volume than the first volume, where the concentration of the 'I dielectric material in the chalcogenide material Sufficient to promote the formation of a second solid crystalline phase. Borrow = the formation of the most densely packed (HCP) phase of the six parties, so that the setting (four) (four) she)

Or substantially only the face-centered cubic (FCC) phase, thus, the amount of volume change caused by the conversion of the 曰 phase, the 曰 phase into the crystalline phase, and the reliability of = good =. And, when limited to only or substantially only. The square (FCC) phase setting operation will occur faster. The phase-change material of the size and the twin crystal state is a small crystal grain plus a series of cells to write data, and by applying a series of settings and resetting pulses to the memory cell 7 *..doc/n 201015763 in memory The above melting and cooling cycles are carried out in the active zone of the cell. A phase change memory device according to the present invention, including

Phase change memory in which St and the second electrodes are in contact ί This phase change memory material includes a chalcogenide material doped with oxidized hair (or other smear material). The phase change material body has - an active region of the second electrode (this active region contains a mesh having at least "two:: = t: material") and has a phase change Zie in the net-free bear cub outside the active region The above-described features and advantages of the present invention can be more clearly understood from the above-described features and advantages of the present invention. The following embodiments are described in detail with reference to the accompanying drawings. [Embodiment] The following description of the present invention will refer to specific embodiments and methods. It is to be understood that the invention is not intended to be limited to the specific embodiments, and the invention may be practiced otherwise. The example of the invention is the invention of Xian Qianming, and the scope of the rights of the present invention is defined by the scope of the patent rights. Anything in the technical field has the usual knowledge (4) The following descriptions may exist = equivalent and change. Each component that implements the _ will be represented by the same reference number. In phase change memory, it is stored (4) by switching the phase change material between amorphous and dicrystalline phases. Figure i is a graph of memory cells with two states (data stored in 疋), including a low resistance set (stylized) state 100 and a high resistance reset (erase) state 1 〇 2, where Each of the 201015763 99twf.doc/n states has a non-overlapping range of resistance. The difference between the highest resistance R1 of the low resistance setting state 100 and the lowest resistance R2 of the high resistance reset state 102 is defined to distinguish the memory cell in the set state 100 from the read margin of the memory cell in the reset state 1〇2. (readmargin) lOl. The data stored in the memory cell can be determined by measuring whether the resistance of the memory cell corresponds to the low resistance setting state 100 or the high resistance reset state 1 〇 2 'for example, by measuring whether the resistance of the memory cell is higher or lower than the margin of § Threshold resistance ❹ vahie RSA 103 in 101. In order to reliably distinguish between the reset state 102 and the set state 100, it is important to maintain a large read margin 101. However, it has been observed that some phase change memory cells in the sense of resetting 102 may experience an erratic "tailing bit" effect, which is a reduction in the resistance of the memory cell over a period of time. The critical resistance value Rsa 1〇3 causes those memory cells to generate data preservation problems and bit errors. - Figures 2A through 2C are schematic diagrams of three conventional phase change memory cells, wherein the mother species have a phase change material memory element 220 (represented by a variable resistor in the figure) and with, for example, a transistor or a diode (diode) The selection device is coupled. 2A is a schematic diagram of a conventional memory cell 20 (four) including a field effect transistor (field) (FET) 210 as a selection device. = word line extending in the first direction ~ 〇 1^ line) 24 () is coupled to the gate of the field effect transistor (ET) 210, and the memory element 22 〇 _ _ 汲 与 与 与 与 与 与Bit detail (9 -i.doc/n 201015763 Figure 2B is a schematic diagram of a memory cell 202 similar to the memory cell of Figure 2A except that the access device is a bipolar junetion transistor (BJT) 212 2C is a schematic diagram similar to the memory cell 204 of the memory cell of FIG. 2A except that the access device is a diode 214. By applying a suitable voltage to the word line 240 and the bit line 23〇 Reading or writing can be achieved by causing current to flow through the memory element 220. The level and duration of the applied voltage depends on the operation being performed, such as a read operation or a write operation. ', in memory with memory element 220 The reset (or erase) operation of the cell will apply a reset pulse of appropriate amplitude and duration to word line 240 and bit line 230 to cause sufficient conversion of the active region of the phase change material to amorphous. Phase current to set the phase change material to a resistance related to the reset state The resistance in the range. The reset pulse is a higher energy pulse sufficient to at least increase the temperature of the active region of the memory member 220 to be higher than the conversion (crystallization) temperature of the phase change material and higher than the melting temperature, thus at least the active region The liquid repulsion is then placed. The reset pulse is then quickly terminated to obtain a faster quenching time, and the active region is rapidly cooled to below the switching temperature to stabilize at least the active region in the amorphous phase. In the setting (or stylization) operation of the memory cell, a program having a suitable amplitude and duration is applied to the word line 240 and the bit line 230 to cause a temperature sufficient to raise at least a portion of the active region to be higher than the switching temperature. The current causes at least a portion of the active region to be converted from a non-crystalline phase to a crystalline phase, which reduces the resistance of the memory element 10 201015763 99twf.doc/n and sets the memory cell to a desired state. In the read (or sense) operation of the cell, a read pulse having a suitable amplitude and duration is applied to the word line 240 and the bit line 230 to induce The current flowing through the memory cell is not caused by the memory element 220. The current through the memory cell depends on the resistance of the memory element 22 and thus on the data value stored by the memory cell. As described above, some of the arrays are in high resistance. The memory cells in the state may experience a trailing bit effect, in which those memory cells will experience a decrease in resistance over a period of time, resulting in data retention problems and bit errors. Figures 3 and 4 show the memory cells in the reset state. The possible early-fail model of the trailing bit effect. Because the initial reset resistance value of the memory cell experiencing the trailing bit effect is high, small or other defective active regions are not considered Is the possible reason. The randomly distributed crystallization regions in the normally amorphous active regions in the early models shown in Figures 3 and 4 will instead grow for a period of time. For memory cells undergoing a trailing bit effect, the randomly arranged crystalline regions result in very small growth in the formation of a low resistance path across the active region. 3A illustrates a conventional "mushroom type" memory cell 300' including a first electrode 314 extending through a dielectric 315, a memory element 220 including a phase change material, and a second memory element 220. Electrode 312. For example, the first electrode 314 can be interfaced with a terminal of an access device such as a diode or a transistor, while the second electrode 312 can be associated with a bit. The width 316 of the first electrode 314 is smaller than the width of the second electrode 312 and the memory cell 220. Because of this difference in width, the region adjacent to the electrode 314 in operation has the largest current density, so that the active region 310 has a meander shape as shown. Preferably, the width of the first electrode 314 (in some examples, the diameter) is minimized to achieve a higher current density using a small absolute current value across the memory element 220. However, attempts to reduce the width of the first electrode 314 may cause electrical and mechanical reliability problems with the interface between the first electrode 314 and the memory element 220 due to the small contact surface therebetween. In the reset state, memory element 220 has a generally amorphous active region 310 and a randomly distributed crystalline region 320 within active region 310. As shown in FIG. 3B, the crystallization zone 320 in the active zone 310 will undergo growth during a period of time but will not form a completely low resistance path through the active zone 310. Therefore, although the memory cells shown in Figs. 3A and 3B may experience a decrease in resistance, they do not experience a trailing bit effect. 4A and 4B illustrate a memory cell 400' having a randomly distributed crystalline region 420 within the active region 410. Thus, a low resistance path 450 is formed across the active region 410 as shown in FIG. 4B over a period of time, resulting in FIG. 4A and FIG. 4B's § memory has experienced a trailing bit effect. 5A and 5B are cross-sectional views of the memory cell 5〇〇, the active region 51〇 including the field containing; phase change domains 511 'in the dielectric-rich mesh 512'. The memory cell 500 solves the above-mentioned problem of smearing and reliability, and obtains improved information bribes, error reductions, and faster operations. The memory cell 500 includes a first electrode 52〇 extending through the dielectric 53〇 to contact the bottom surface of the memory cell 516, and a phase transition from the doped dielectric 201015763—

A second electrode 540 on the memory element 516 formed by the body of material. The first electrode 520 and the second electrode 540 may include, for example, titanium nitride (TiN) or tantalum nitride (TaN). On the other hand, the first electrode 520 and the second electrode 540 may each be tungsten (W), tungsten nitride (WN), titanium nitride (TiAIN) or aluminum nitride tantalum (TaAIN), or in another Examples include doped-Si, bismuth (Si), carbon (C), germanium (Ge), chromium (Cr), titanium (Ti), tungsten (W), molybdenum (Mo), Aluminum (A1), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni), nitrogen (N), oxygen (Ο), ruthenium (Ru), and One or more components selected from the group consisting of the combinations. In the illustrated embodiment, the dielectric 530 includes tantalum nitride (SiN). On the other hand, other dielectric materials can be used. In this example, the phase change material of memory element 516 comprises a germanium alloy (Ge2Sb2Te5) material doped with 1 to 20 atomic percent yttrium oxide. Other chalcogenide materials and dielectric materials characterized by a grid can also be used. It can be seen that the width 522 (in some embodiments, the diameter) of the first electrode 52A is less than the width of the memory element 516 and the top electrode 54A, so current will concentrate on the memory element 516 adjacent the first electrode 52〇. The part that leads to the active area 510 is not shown. The memory element 516 also includes an inactive regi〇n 5 i 3 of the active region 51. The inactive region 5 i 3 is a polycrystalline state of small crystal size and does not form a dielectric mesh. The active region 510 includes a phase change region of the grid 512 富含 rich in dielectric f 的 矽 矽 矽 矽 浓度 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The sulfur species has a concentration of chalcogen in the inactive zone 513. Vi.doc/n 201015763 FIG. 5A illustrates the memory cell 500 in a high resistance reset state. In the reset operation of the memory cell 500, a bias circuit is connected to the first electrode 52A and the second electrode 54A (for example, referring to the bias circuit voltage and current source 1736 of the figure together with the controller (c〇 The ntr〇ller) 1734) causes a current to flow between the first electrode 52A and the second electrode 54A via the memory element 516, which causes a mutual resistance of the normally amorphous phase in the phase change region 511 of the active region 510. In order to establish a high resistance reset state in the memory cell 5〇〇. In the inactive region 513 outside the active region, the body of the chalcogen-doped dielectric material maintains a polycrystalline state of small grain size. Fig. 5B shows the memory cell 5 which is not in the low resistance setting state. In the setting operation of the memory cell 500, a bias circuit coupled to the first electrode 52A and the second electrode 54A causes current to flow between the first electrode 520 and the second electrode 54A via the memory element 516. The current is sufficient to cause a low resistance of the generally crystalline phase in the phase change region 主动 of the active region to establish a low resistance set state in the cell 500. The area in the low resistance state can be different in size from the high resistance state as shown in FIGS. 5A and 5B. However, this has not been clearly demonstrated by experiments. ..., FIG. 6 is a memory cell 5 in the reset state of FIG. 5A. This figure provides an improved endurance for describing the memory cell: the power grid 512 is surrounded and the phase change region 511 is isolated. Therefore, the crystallization region in the phase change region 511 of the crystallization is via some regions ==路=〇〇' memory cell _ ΐ Ξ Ξ 质 质 质 质 质 质 质 质 质 质 质 质 段 段 段 段 段 段 段 段 段 段 段 段 段 段 段 段 段 段 段 段 段Training low resistance 201015763 9twf.doc/n into. Therefore, the bit position error and the reduced bit error are significantly reduced. Information on the improvement of the memory and the improvement of the memory Figure 7 is a data storage of the improved memory cell in accordance with the present invention. Fig. = Medium = Inference of the measurement data of the memory cell, the phase change region within the main material. , Active & include • Dielectric-containing grid

_Picture: 710 ′ This line indicates the inference of the measurement data of the δ-resonance cell containing the undoped GST material. As can be seen from Fig. 7, a significant improvement in the failure time is achieved for a memory cell having an active region including a dielectric-rich intra-grid region.

Figure 8A and Figure 8B show the X-ray diffraction (x_my output, XRD) spectral data of the 5) phase change material according to the undoped niobium alloy. GST-based memory materials typically include two crystalline phases, a face_centered cubic (FCC) phase with a lower switching temperature and a hexagonal closest packing with a higher switching temperature (hexag〇nal closed-packed). , HCP) phase, the density of the hexagonal closest packed (HCP) phase is higher than the density of the face centered cubic (FCC) phase. In general, it is best not to convert from the face-centered cubic (FCC) phase to the hexagonal closest packed (HCP) phase, as the result is a reduction in the volume of the memory material in the memory material and between the electrode and the memory material. Stress is generated at the interface. Also, the face centered cubic (FCC) phase material undergoes a small change in volume from the amorphous phase to the crystalline phase' and thus the transition will occur at a higher rate. 8A and 8B show that 15 Λ-doc/n 201015763 3 _2Sb2Te5) occurring at an annealing temperature lower than 400 ° C is converted from a face-centered cubic phase to a two-sided stacked (HCP) phase. Because it contains undoped erbium alloys, it is possible to experience the shed during the set operation. c or more == =, in the most densely packed state of the hexagonal conversion (HC ^ ^ 〇 ^ Figure 8A and 8B also shows the misplaced hoof alloy of the modified (four) sub-percentage oxidized stone in accordance with the present invention ( Ge2Sb2Te5) material (tX2 is pure in spectrum, and the structure of the blended material is corrected at the annealing temperature of six _C, the simple face center, the cubic (FCC) shape 20 and the stone eight is h in Fig. 8A and Fig. 8A The doping of 10 atomic percent in 8B and the diffraction peak of the recorded bismuth alloy __ = the so-called mis-recorded hoof alloy you talk about (4) the grain size of the undoped bismuth alloy (Ge2Sb2Te5) grains Size = fruit, compared with the alloy containing undoped bismuth (9) said Ke; the temperature of the second === _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Mechanical stress, and has a large switching speed of SW (SW off (four) _). The second package of the component _ material to modify the memory /, L miscellaneous atomic percentage atmosphere of the combination of 201015763 - gold (= e2Sb2Te5) material The Xenon Diffraction (xRD) data. Figure 9 illustrates the misplaced hoof alloy (2Sb2Tes) 彳 面 face centered cubic (FCC) of the push rabbit that has an annealing temperature below 40 °C. The state is converted into a hexagonal closest packed (HCP) m Jt eye compared to a nitrogen-containing niobium alloy § 忆 胞 cell domain. The present invention contains a 10 to 2 G atomic percent oxidized stone 锗 锗 碎 合金 alloy The memory cell you tear the material will experience less mechanical stress and have greater reliability and higher speed. Figure 1 is a flow chart of a process according to the present invention, and Figure ❹ to ® is in accordance with this Hair-to-draw process of a memory cell containing a 1G to 2 atomic atomic ratio of a oxidized stone alloy (Ge2Sb2Te5) material. This memory cell has a dielectric-rich grid. The active region of the phase change region. At step 1000, a first electrode 52G having a width or diameter 522 and extending through the dielectric 53〇 is formed, thereby obtaining a structure as shown in the cross-sectional view of Fig. 11A. In the illustrated embodiment, the first electrode 52A includes titanium nitride (TiN), and the dielectric 53A includes tantalum nitride (SiN). In some embodiments, the first electrode 52 has a sub-lithography Sublitliographic width or diameter 522. The first electrode 520 extends through the dielectric 53〇 to Surface access circuitry (not shown). The following access circuitry can be formed by standard processes well known in the art, and the configuration of the components of the access circuitry depends on the array of memory cells in accordance with the present invention. Configuration. Typically, the access circuitry may include access devices such as transistors and diodes, word and source lines, conductive plugs, and semiconductor substrates (4) to return to Gigalog 201015763 ---- Doped region within -.- tdoc/n substrate). For example, you can apply on June 18, 2007 and name it "Method f0r Manufacturing a Mind Change M_ry

The first electrode 520 and the dielectric layer 530 are formed by the method, material, and process disclosed in U.S. Patent Application Serial No. 11/764,678, the disclosure of which is incorporated herein. reference. For example, a layer of electrode material can be formed on the top surface of the access circuit (not shown), and then a layer of photoresist is formed on the electrode layer using standard photolithography techniques (ph〇 The pattern is patterned to form a mask that covers the photoresist of the position of the first electrode 52A. Thereafter, the photoresist mask is trimmed using, for example, an oxygen plasma to form a sub-lithographic-sized mask structure covering the position of the first electrode 520. The electrode material layer is then etched using a trimmed photoresist mask to form a first electrode 520 having a human lithography diameter 522. Thereafter, the dielectric material 530 is formed and planarized, thereby obtaining the structure shown in Fig. HA. "In another case, you can use the application called "Phase Change Memory Cell in Via Array with" on September 14, 2007.

The method, material, and process disclosed in U.S. Patent Application Serial No. 1/855,979, the entire disclosure of which is incorporated herein by reference. The content of the application will be incorporated into this case for reference. For example, a dielectric 53 can be formed on the top surface of the access circuit, and then an insulating layer and a sacrificial layer are sequentially formed. Then, a mask having a minimum feature size whose opening is close to or equal to the process for creating the mask is formed on the sacrificial layer, 18 201015763 ^9twf.doc/n This opening is located above the position of the first electrode 52〇. Then, the mask is used to selectively form the insulating layer and the sacrificial layer, thereby forming via holes (vm) in the insulating layer and the sacrificial layer and exposing the top surface of the dielectric layer 53A. After the mask is removed, a selective undercut is performed on the through hole (Xian Ru (10) imitation beer coffee h) so that the surname is engraved and the sacrificial layer and the dielectric layer are intact. A fill material is then formed in the vias. The self-aligned voids (self_aligned v〇id) of the fill material are formed in the vias due to the selective undercutting process. After that, an anisotropic etching process is performed on the i-filled material to open the cavity and layer the area below the cavity, thereby forming the package two-way: the side of the filling material Wallwaier (sidewaii spacer). The sidewall spacers have substantially π dimensions depending on the size of the void and may therefore be less than the minimum feature size of the lithography process. Then, the dielectric layer 530' is etched by using the sidewall spacer as an etching mask to form an opening having a diameter smaller than the minimum feature size in the dielectric f layer 53(). Next, an electrode layer is formed in the opening of the dielectric layer 53A and then subjected to a planarization process such as chemical mechanical ❹p〇hshing (CMP) to remove the insulating layer and the sacrificial layer and form the first electrode 520. Thus, the structure shown in Fig. 11A is obtained. In step 1010, a phase change material layer containing a bismuth alloy (Gejb^Te5) material doped with 10 to 20 atomic percent of yttrium oxide is deposited on the first electrode 52A and the dielectric 53A of FIG. 11A. Thus, the structure shown in Fig. ΐβ is obtained. Co-sputtering (<: 〇 叩 叩 11 沉 111 111 & ) ) 叩 灶 灶 & & & & & & ) ) G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G 10 watts (Watts) of direct current (DC) power in a gas environment and a radioactive (RF) power of 1 to 115 19 201015763 ry / ^ ^ wfdoc / n Watts (Watts) of the dioxide (Si02) dry material. Then, in step 1 () 2, annealing is performed to crystallize the phase change material. In the case of the Example A, the thermal annealing step was carried out in a nitrogen atmosphere for 100 seconds. On the other hand, since the subsequent back-end-〇f-iine (BE〇L) process of the finished device may include high temperature cycling and/or thermal annealing steps depending on the manufacturing techniques used to complete the device, Annealing of step 1020 can be accomplished in the examples by the following process, and no separate annealing step is added to the line. Next, at step 1030, the second electrode 540 is formed, thereby obtaining the structure of Fig. 11C. In the illustrated embodiment, the second electrode 540 comprises titanium nitride (TiN). Then, at step 1040, a post-stage (BE0L) process is performed to complete the semiconductor process steps of the wafer. The post-stage (BE0L) process can be a standard process well known in the art, and the process is performed in accordance with the configuration of the wafer on which the memory cell is implemented. Typically, the structure formed by the back-end (BE0L) process can include contact windows for interconnects, interlayer dielectrics, and various metal layers on the wafer including the circuitry that couples the memory cells to the peripheral circuitry. These back-end (BEOL) processes may include deposition of dielectric materials at high temperatures, such as tantalum nitride (SiN) deposition under 々^^ 或 or high density plasma at 500 ° C or higher (high density). Plasma, HDP) Oxygen deposition. The result of these processes is the formation of the control circuit and bias circuit shown in Figure 17 on the device. Thereafter, at step 1050, a current is applied to the memory cells of the array to melt the active region, and cooling is allowed to form a dielectric mesh, such as by a control circuit and a bias circuit on the memory cell 500 by a reset cycle (or Set 20 201015763 : 99twf.doc/n 201015763 :99twf.doc/n ❹

St solves and cools the active zone at least once or enough times to shape F? ,. The number of cycles required to form the active region 510 including the phase change in the dielectric-rich grid 512 can be, for example, shown in Figure UD. This cycle involves applying an appropriate current from the "one electrode 520 and the second electrode 540 to the memory element, and the subsequent program has no current or a small current to allow active area cooling." Applying one or more reset pulses or a series of setting and reset pulses sufficient for the active area, the set/reset circuit on the settling can be used to implement the secret/cooling cycle. The normal set/reset cycle used during device operation is different = voltage level and pulse length, and the (4) circuit and bias circuit can be implemented to perform the mesh formation mode. In another embodiment, the wafer is connected during fabrication. Line equipment (such as test equipment) can perform a melting/cooling cycle to set the voltage magnitude and pulse height.

12 to 14 also illustrate a memory cell comprising a bismuth alloy (Gejl^Te5) material doped with 1 〇 to 2 〇 atomic percent yttrium oxide, the active region of which includes a phase in a dielectric-rich grid. Variable area. The materials described above with reference to the elements of Figures 5A and 5B can be implemented in the memory cells of Figures 12 through 14, and thus a detailed description of these materials will not be repeated. 12 is a cross-sectional view of a second memory cell 1200 having an active region ι 210 including a phase change region 1211 within a dielectric-rich grid 1212. The memory cell 1200 includes a dielectric spacer 1215 that isolates the first electrode 1220 from the second electrode 1240. The memory element 1216 extends across the dielectric spacer 1215 to contact the first electrode 1220 and the second electrode 21 i.aoc/n 201015763 1240, thereby defining a current path between the electrodes of the first electrode 122 〇 and the second electrode i24 〇 This path has a path length defined by the width 12 of the dielectric spacer 1215. In operation, when current flows between the first electrode 122A and the second electrode 1240 and passes through the memory element 1216, the active region 1210 heats up faster than the remaining portion 1213 of the memory element 1216. 13 is a cross-sectional view of a third memory cell 1300 having an active region i3i〇 including a phase change region 311 in a dielectric-rich mesh 1312. The memory cell 1300 includes a piUar memory element 1316 that contacts the first electrode 1320 and the second electrode 1340 at the top 1322 and the bottom surface 1324, respectively. The width 1317 of the memory element 1316 is substantially the same as the width of the first electrode 132x and the second electrode 1340 to define a multilayer pillar surrounded by a dielectric (not shown). As used herein, the term "substantially" includes "manufacturing tolerance." In operation, when the home current circulates between the first electrode 1320 and the second electrode 1340 and passes through the two-memory element 1316, the active region 1310 heats up faster than the remaining portion 13& of the memory element. 14 is a cross-sectional view of a fourth memory cell 1400 having an active region 141A including a phase change region 14ι within a dielectric-rich grid 1412. The memory cell 1400 includes a pore-type memory element 1416 surrounded by a dielectric (not shown) that contacts the first electrode 1420 and the second electrode 1440 at the top and bottom surfaces, respectively. The width of the memory element is less than the width of the first and second electrodes, and operatively, when current flows between the first electrode and the second electrode and passes through the memory element, the main area heats up faster than the remainder of the memory element. °° 22 201015763 ,, 9twf.doc/n, it should be noted that the present invention is not limited to the memory cell structure described herein* and includes a memory cell having an active region including a rich network. The phase change region within the grid. 15A and 15B are respectively a type of memory cell containing a phase change material doped with oxidized oxidized stone according to the present invention in a reset and set state after 1 cycle, respectively. Although a_issi〇n - such as please (10) ah 'Ding chat image ^ said and the figure of the memory cell formation as described above with reference to Figure 1G and Figure u, so including ❹ ❹ 10 to 20 atomic percent oxidized stone The erbium-doped alloy (Ge2sb2Te5) material' has an active region comprising a phase change region within the dielectric-rich grid. The phase change region of the active region in the reset and set states can be seen from Figs. 15A and 15B. In photograph t, the doped phase change material presents an intermediate gray horizontal bar in the center, a dark gray top electrode ' on top of the phase change material and a blurred visible bottom electrode column extending through the black bars below the phase change material. A dome-shaped active region having a radius just smaller than the thickness of the film layer can be seen to have an arrangement of materials different from the material body outside the active region. The body of the phase change material exhibits a very uniform boundary characterized by a polycrystalline structure of small grain size. 16A to 16C are other transmission electron microscope (TEM) images of the memory cells of Figs. 15A and 15B in a reset state. Figure 16A is an expanded image of the active area of the memory element (located inside the rectangle) showing the boundary between the phase change regions. In Figure 16A, the area within the dielectric grid is visible. 16B and 16C are images of electron energy loss spectroscopy (EELS) of 矽(Si) and oxygen (〇), respectively. Figures 16B and 16C show a clear correlation of the position of bismuth (Si) with oxygen (9) and show 矽(si) and oxygen (Ο) between the boundaries of the phase change regions visible in Figure 16A. Also, the phase change region exhibits no bismuth (Si) and oxygen (〇). 17 is a simplified block diagram of an integrated circuit 1710 including a memory array 1712 implemented using memory cells in accordance with the present invention. The memory cell has a phase within a dielectric including a dielectric rich matrix. The active area of the variable area. A word line decoder 1714 having read, set, and reset modes is consuming and electrically communicating with a plurality of sub-elements 1716 along the column arrangement of the memory array 1712 (eiectricai communication). Bit line (row) decoder 1718 is in electrical communication with a plurality of bit lines 1720 arranged along the rows of array 1712 for reading, setting, and resetting phase change memory cells (not shown) of array 1712. Bus 1722 provides addresses to the word line decoder and driver 丨7丨4 and bit line decoder (1^1丨1^&(^〇(161*)1718. Contains read The sensing circuits (sensing amplifiers) and data-in structures of the voltage and/or current source block 1724 of the fetch, set, and reset modes are via the data bus 1726 and the bit line decoder 1718. The handle is connected to the input/output of the integrated circuit pH or other internal or external data source of the integrated circuit 1710 via the data input line 1728 to the data input structure of block 1724. Other circuits 1730 may be included in the integrated body. The circuit 1710, for example, a general purpose processor or a special purpose circuit, or a combination of modules providing a system-on-a-chip function supported by the array 1712. The sense amplifier is supplied to the input/output port of the integrated circuit 1710 or the data integrated circuit 171 via the data wheel output line 1732. The σρ or the external data target (data destinati〇ns) in this example. The implemented controller Π 34 utilizes a bias arrangement The application of the earth control bias voltage and current source 1736 is applied to the package 3 »selling, erasing, erasing verification and stylizing the voltage and/or current of the word line and bit line Bias arrangement. In addition, the bias arrangement of the dissolution/cooling cycle can be implemented in the manner described above. The controller m ^ 34 ° can be implemented using special purpose logic circuits well known in the art, in other embodiments, the controller The device 34 includes a general purpose processor that can be implemented on the same "circuit to execute a computer program to control the operation of the device. In other embodiments, the controller 1734 can be implemented using a combination of special purpose logic circuits and a general purpose processor. As shown in FIG. ,, each of the memory cells of the array 1712 includes an access memory: 曰, (or other access device, such as a diode), and a memory device having an active region including a rich medium. The phase change region within the grid of electrical mass, in Fig. 18, shows four memory cells 1830, 1832, 1834, and 1836 having memory elements 1840, 1842, 1844, and 1846, respectively, which may include a cell block of an array of millions of memory cells. The sources of each of the access cells 1830, 1832, 1834, and 1836 are connected to a source line (source), source line 1854, and In the source line termination circuit 1855, such as a ground terminal. In other examples, the source line of the access device is not electrically connected, but can be independently controlled. In some embodiments, the source line terminal Circuitry 1855 can include, for example, a bias circuit of source and current sources and a decoding circuit that applies a bias field other than ground to source line 1854. 25 201015763 t.doc/n A plurality of word lines including word lines 1856, 1858 extend in parallel along the first side. Word lines 1856, 1858 are in electrical communication with word line decoder 1714. The memory cell and the access terminal of the cell 1834 are connected to the word το line 1856' and the gate of the memory cell of the memory cell 1836 is commonly connected to the word line 1858. A plurality of bit lines including bit lines 1860, 1862 extend in a second direction and are in electrical communication with bit line decoder 1718. In the illustrated embodiment, each memory element is arranged between the drain of the corresponding access device and the corresponding bit line. Alternatively, the memory element can be located at the source terminal of the opposite access device. ... ❹ Note that the memory array 1712 is not limited to the array configuration shown in Figure 18, and other array configurations can be used. Moreover, in some embodiments, a bipolar transistor or a diode may be used in place of a metal oxide semiconductor (MOS) transistor as an access device. In operation, each of the memory cells of array 1712 stores data based on the resistance of the corresponding memory element. The above data values can be determined, for example, by the sense amplifier of sense circuit 1724 to compare the selected memory cell line current with a suitable reference current. The current with the reference current set to the predetermined ❹ range corresponds to the logic "〇", while the current of the different range corresponds to the logic "1". Thus, the memory cells of the array 1712 can be read or written by applying a suitable voltage to one of the word lines 1858, 1856 and coupling one of the bit lines I860, 1862 to the voltage source for current Flow through the selected memory cells. For example, a current path 〇88〇 is established to traverse the selected memory cell (in this case, memory cell 26 201015763 > 9twf.doc/n 1830 and corresponding memory component 184A) in such a manner that the voltage is applied in place. The line 186G, the word line 1856, and the source line 1854 are sufficient to turn on the access transistor of the 183 cell, and cause a current flow from the bit line to the source line 1854 in the path 188 ,, and vice versa. Of course. The level and duration of the applied voltage depends on the operation being performed, such as reading 4 or writing. In the reset (or erase) operation of the NMOS cell 1830, the word line decoder 1714 causes the appropriate voltage pulse to be applied to the word line to turn on the access transistor of the memory cell 1830. The bit line decoder 1718 causes the supply of the amplitude and duration of the voltage pulse to the bit line 1860 to cause the current to flow through the memory element 184, which increases the temperature of the active region of the memory element 184 to above the phase. The transition temperature of the variable material is higher than the melting temperature in order to place the active region-variable material in the liquid towel. The current is then terminated (e.g., by terminating the voltage pulses on bit line 1860 and word line 1856) to obtain a more quenching time in which the active region is cooled to the amorphous phase of the normal zeta resistance in the phase change region of the active region. Establish a high resistance reset _ state in the memory cell. The reset operation can also include more than one pulse, such as using a pair of pulses. __ In the set (or stylized) operation of the selected delta cell 1830, the word line decoder 1714 causes the appropriate voltage pulse to be supplied to the word line a% to turn on the access transistor of the memory cell 1830. The bit line decoder 1718 causes the supply of a voltage pulse of a suitable amplitude and duration to the bit line' to pick up the current flowing through the memory element brain. This current pulse is sufficient to raise the temperature of the active region above the switching temperature and to cause the active region The phase change region is converted from a crystallized state of 27 201015763 to a crystalline state of generally low resistance, recalling the resistance of the component side, and the memory cell 1530 to a low resistance state.

The read (or sense) operation of the data value stored in the cell deletes the code 'code H Π 14 to cause the appropriate voltage pulse to be supplied to the word line 1856 to turn on the memory cell. The bit line decoder (4) causes the supply of a suitable amplitude and __ voltage pure element line to cause current to flow through the memory element 184, which does not cause the memory element to generate a power P and change state. The current touched by the bit line and the current through the memory cell 183 = = depends on the resistance of the memory cell, depending on the state of the data associated with the memory cell. Therefore, the data state of the memory cell can be determined by detecting whether the resistance of the memory cell 183 对应 corresponds to a high resistance sad or low resistance state, for example, by comparing the bit line 186 by the sense amplifier of the sensing circuit 1724. The current is with a suitable reference current. Materials used in accordance with embodiments of the present invention comprise yttria and yttrium-niobium alloys (GeJbzTe5). Other chalcogenide materials can also be used. Chalcogen

Chalcogens include any of four elements (a part of a group VIA element forming a periodic table) of oxygen (〇), sulfur (S), lithus (Se), and Te (Te). Chalcogenic materials include compounds having more positively charged elements or radical chalcogen elements. Chalcogenide alloys include combinations of chalcogenide materials with other materials such as transition metals. Chalcogenide alloys typically contain one or more elements of Group IVA elements of the Periodic Table of the Elements, such as germanium (Ge) and tin (Sn). Chalcogenide alloys typically include a combination of one or more of bismuth (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change-based 28 201015763 9twf.doc/n memory materials have been described in the scientific literature, including the following alloys: gallium (Ga) / antimony (Sb), indium (In) / antimony (Sb), indium ( In)/Nitrate (Se), Sb/S (Te), Ge (Ge)/Te (Te), Ge (Ge)/锑(Sb)/碲(Te), Indium(In)/锑( Sb)/碲(Te), gallium (Ga)/砸(Se)/碲(Te), tin(Sn)/锑(Sb)/碲(Te), indium(In)/锑(Sb)/锗( Ge), Silver (Ag) / Indium (In) / Sb (Sb) / 碲 (Te), 锗 (Ge) / Tin (Sn) / 锑 (Sb) / 碲 (Te), 锗 (Ge) / 锑 ( Sb) / 砸 (Se) / 碲 (Te) and 碲 (Te) / 锗 (Ge) / 锑 (Sb) / 琉 (S). In the group of bismuth (Ge)/recorded (Sb)/tellurium (Te) alloys, a wide range of alloy combinations can be used. The characteristics of this combination can be expressed as TeaGebSb100(a+b). One researcher has indicated that the most useful alloy is that the average concentration of cerium (Te) in the deposited material is preferably less than 70%, usually less than about 60% 'and generally ranges from as low as about 23% to Up to about 58% of cerium (Te), and preferably about 48% to 58% of cerium (Te). The average concentration of germanium (Ge) in the material is above about 5%, and ranges from as low as about 8% to as high as about 30%. The remaining elements are typically less than 50%. The concentration of germanium (Ge) preferably ranges from about 8% to about 40%. The main constituent element of the remaining ❹ in this combination is 锑(Sb). These percentages are atomic percentages of a total of 1% by atom of the constituent elements (the first to the uth of the 5th, 687, 112th patent proposed by 〇vshinsky). Other alloys evaluated by other researchers include the following niobium alloys: Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7 (see Noboru Yamada, 1997, SPIE, Vol. 3109, pp. 28-37, "Potential of Ge-Sb-Te"

Phase-Change Optical Disks for High-Data-Rate Recording"). More commonly, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), 29 doc/n 201015763 铌 (Nb), palladium fRd), platinum (Pt) can be combined to form a binary sign. Phase change alloy. Possible useful notes P. The examples are hereby incorporated by reference.至13订' Although the present invention has been disclosed by way of example, 鈇1 ❿ ^ is a phase change memory cell of the memory state of the resistance division = map to Figure 2C is a variety of memory transposition _ variable memory 3A and 3B are conventionally known that the active region (10) has a memory cell, and the pop region is usually a crystalline block. FIG. 4A and FIG. 4B are conventionally known as a contact and a cell, and the active region is usually There is also a non-crystalline phase that forms a scorpion-like memory. The crystal blocks j 5A and FIG. 5B which are caused by the growth failure mode are respectively the memory cells having the active region according to the inventors of the present invention in the set and reset state, and the active region contains eight phases. A dielectric mesh of the variable material region. 6 is a schematic diagram of an active region of a memory cell in a reset state in accordance with an embodiment of the present invention, the active region having a thin layer of dielectric material 30 201015763 ^twf.doc/i to avoid FIG. 4A and Fault Domain 0 as depicted in Figure 4B Figure 7 is an improved data preservation by an embodiment in accordance with the present invention. Fig. 8A and Fig. 8B are diagrams of x-my dif-' XRD spectral data according to the present invention.

The hexagonal closest packing of doped oxidized (tetra) ytterbium (GST) = = there is a kind of X-ray diffraction that is used to compare the doping of nitrogen with X-rays (X 戦 ,, where ^ ^ 任 ) 12 is a bridge type memory cell structure using a phase change material having a dielectric mesh in an active region in accordance with an embodiment of the present invention.

The mode phase change material region diagram H) is a simplified flow diagram according to the present invention-implementation-difficulty process. 11ASW 11DS is a memory having a dielectric grid formed in the active region according to an embodiment of the present invention. The steps of the process of the cell. Figure 13 is a diagram showing an "active in via" type of memory cell using a phase change material having a dielectric grid in an active region in accordance with an embodiment of the present invention. Figure 14 is a perspective view of a memory cell structure using a phase change material having a dielectric grid in an active region in accordance with an embodiment of the present invention. 15A and 15B are respectively a transmission electron microscope of a cross section of a 记忆-type memory cell containing yttrium oxide (GST) doped with yttrium oxide according to an embodiment of the present invention in a reset and set state. (TEM) image. 201015763d/ ..... /i.doc/n

16A to 16C are transmission electron microscope (TEM) images of the memory cells of FIGS. i5a and i5B in a reset state, wherein FIG. 16A is an expanded image of the active region (located inside the rectangle) of the memory element, and FIG. 16B and Figure 16C are images of the electron energy loss spectrometer (EELS) of helium and oxygen, respectively. Figure 17 is a simplified block diagram of an integrated circuit memory device including phase change memory cells in accordance with one embodiment of the present invention. Figure 18 is a simplified circuit diagram of a memory array including phase change memory cells in accordance with an embodiment of the present invention. [Description of main component symbols] 1〇〇: setting state 101. Reading margin 102: reset state 103, RSA: critical resistance values 200, 202, 204, 300, 400, 500, 1200, 1300, 1400, 1830, 1832 , 1834, 1836: memory cell 210: field effect transistor 212: bipolar junction transistor 214: diode 220, 516, 1216, 1316, 1416, 1840, 1842, 1844, 1846: memory elements 230, 1720 , 1860, 1862: bit lines 240, 1716, 1856, 1858: word lines 310, 410, 510, 1210, 1310, 1410: active area 32 201015763; 99twf.doc / n 312, 540, 1240, 1340, 1440 : second electrodes 314, 520, 1220, 1320, 1420: first electrodes 315, 530: dielectrics 316, 522, 1217, 1317: widths 320, 420: crystallization regions 450, 600: low resistance paths 511, 1211, 13H, 1411: phase change region

512, 1212, 1312, 1412: dielectric-rich grid 513: inactive regions 700, 710: lines 1000, 1010, 1020, 1030, 1040, 1050: step 1100: phase change material layers 1213, 1313: remaining section

1215 Dielectric spacer 1322 Top surface 1324 Substrate 1710 Integrated circuit 1712 Memory array 1714 Word line decoder 1718 Bit line decoder 1722 Bus line 1724 Sensing circuit 1726 Data bus 1728 Data input line 33 201015763 - 1730 : Other circuit 1732: Data output line 1734: Controller 1736: Bias circuit voltage and current source 1854: Source line 1855: Source line termination circuit 1880: Current path R1: High resistance R2 of low resistance setting state: Minimum resistance of high resistance reset state

Claims (1)

201015763 99twf.doc/n VII. Patent application scope: 1. A method for manufacturing a memory device, comprising: forming a first electrode and a second electrode; forming a main body body between the first electrode and the second electrode a memory material shape, a chaotic dielectric material of the chalcogenide material, including a ruthenium-doped ruthenium body, in the grid-domain of the first electrode and the second electrode The grid of dielectric material outside the active region and without the region of the dielectric material. ^ 属 · · · · · · 之 之 之 之 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 ^ 记忆 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The memory material includes the chalcogenide material doped with the dielectric material; Recalling that the active region (10) of the body dissolves and solidifies the phase change "曰-time, but does not interfere with the dimorphism outside the active region, thus forming in the active region The mesh of the dielectric material in the region of at least one of the melon materials. The method of manufacturing the memory device according to claim 1, wherein the phase change memory material is The chalcogenide material used is characterized by having a first volume of a first solid state and a second volume of a second solid crystalline phase without the dielectric material, the phase change memory material having a non-junction 35 t.aoc/n 201015763 that is closer to the second volume than the first volume to i: the concentration of the dielectric material in the chalcogenide material is sufficient to promote the shape f Solid state crystalline phase. Method, description: The manufacturing method of the memory device, the second solid state, the second = the closest packed phase, and the manufacturing method of the memory device described in the first paragraph of the soil patent scope (2) The chalcogenide material is characterized by a plurality of solid crystalline phases in the case of a non-ferrous material, wherein the dielectric material in the material is sufficient (10) preventing formation of at least one of the solid crystalline phases in the active region. And the characteristics of the chalcogenide material used in the phase-recall material described in the manufacture of the memory device described in the first aspect of the patent device of claim 1 are not doped with the dielectric material. And a plurality of (four) crystalline phases, wherein the concentration of the dielectric material in the chalcogenide material is sufficient to form at least one of the solid crystalline phases outside the active region. 7. The method of manufacturing a memory device according to claim 1, wherein the dielectric material in the chalcogenide material is oxidized stone, and the concentration of the dielectric material is 丨〇2 Within the range of 〇 atomic percentages. 8. The method of manufacturing a memory device according to claim 2, further comprising forming a circuit on the memory device to write a set pulse and a reset pulse across the first electrode and the second electrode. The data is entered, and the melting and the curing are performed by applying a reset pulse across the first electrode and the second electrode. 9. The method of manufacturing a memory device according to claim 2, wherein the method further comprises forming a circuit on the memory device to span the first electrode and the first electrode. The set pulse and the reset pulse are applied to write data, and the melting and the curing are performed by applying a set pulse and a reset pulse across the first electrode and the second electrode. 1. The chalcogenide material used in the phase change memory material described in the eighth aspect of the invention of the memory device of the first aspect of the invention is GexSbyTez. The U.S. chalcogenide material used in the phase change memory material as described in the manufacturer of the memory device described in the second paragraph of the patent application includes ex yTez, wherein χ=2, y== 2 and z=5, and wherein the dielectric material is an oxidative dream, the dielectric material "in the range of 10 to 20 atomic percent. 12. A phase change memory device comprising: a first electrode and a Two electrodes; The memory material forms a second=two-excited memory material located at the first electrode and the material, including the active body, and a grid between the first electrode and the second electrode : the region and the region of the dielectric material of the dielectric material of the dielectric material (the sulphur material is turned over in the 12th item of the phase change memory used in the phase change memory material The eighth dielectric material is characterized by a first volume having a '4:;: 37 201015763 and a second solid crystalline phase having a second volume, the phase change memory material having a closer a second volume other than the first volume of the amorphous phase volume, wherein the concentration of the dielectric material in the chalcogenide material is sufficient to form the second solid crystalline phase. From 14. In the phase change memory device of item 12, the first solid state crystalline phase is a hexagonal closest packed phase ' and the two solid crystalline phase is a face centered cubic phase. 15. The phase change memory described in the phase change memory device of claim 12, wherein the sulfur riding material used in (10) is characterized by a plurality of types when the dielectric material is not broadcasted. a crystalline phase, wherein the concentration of the dielectric material in the material is sufficient to avoid formation of at least one of the solid crystalline phases in the active region. 16. The phase change memory device according to claim 12, wherein the chalcogenide material according to (4) is characterized in that the chalcogenide material is characterized by a plurality of crystal phases. Wherein the concentration of the dielectric (4) in the sulfur is sufficient to form at least one of the solid crystalline phases in the main. The dielectric material in the device of the reference device is oxidized stone, and the wave length of the material is in the range of 1 G to 2 G atomic percent. 18. The phase change memory device of claim 12, wherein the circuit is applied to the phase change memory device, and the circuit applies a set pulse across the stroke/poleless electrode. And resetting the pulse to write /Bei' and finely applying across the first electrode and the second electrode; 38 201015763 99twf.doc / n One less reset pulse to melt and solidify the active region. The phase change memory device of claim 12, comprising a circuit on the phase change memory device, the circuit applying a set pulse and resetting across the first electrode and the second electrode Pulse writing = grazing, and melting and solidifying the active region by applying at least one set pulse and at least one reset pulse across the first electrode and the second electrode. 20. The phase change memory device of claim 12, wherein The chalcogenide material used in the phase change memory material described herein includes GexSbyTez. 21. The phase change memory device of claim 12, wherein the phase of the phase change s memory material comprises: exSbyH, wherein x=2, y=2, and z =: 5, and wherein the dielectric material is oxygen cut 'the concentration of the dielectric f material is in the range of 'Μ% atomic percent. The phase change memory device of the above-mentioned item 12, wherein the dopants have a polycrystalline state outside the main surface.