201011759 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種多次可程式化快閃記憶體，特別是關 於-種應用在多次可程式化快閃記憶體中能加快讀取速度 的列解碼器。 【先前技術】 ffl 1顯示習知的快閃記憶體10，其中列解碼器12及行 解碼器16分別根據輸入信號Inl & In2驅動記憶體陣列 14，進而執行程式化、抹除、修正或讀取等操作。快閃記憶 體10的讀取速度主要受到字元線延遲㈣響，而字元線延 遲則與列解碼器12有關。W 2顯示圖丄中的列解碼器12， 其中字元驅動器18根據信號χτ、ΧΤΒ及BUB驅動宇元線 WL1或WL2 ’在咼壓模式時，高壓準位平移器2〇根據輸入信 號Ini及咼壓HV產生信號χτ、xtb及BLKB給字元驅動器 ❹ 18以執行程式化、抹除或修正等操作，其中高壓hv大於電 源電壓VDD或小於接地電位GND，在讀取模式時，高壓準位 平移器20根據輸入信號Ini及電源電壓vdd產生信號XT、 ΧΤΒ及BLKB給字元驅動器18以執行讀取操作。 圖3顯示高壓準位平移器2〇的部分電路，其中邏輯電 路22根據輸入信號lnl產生信號sl，pM〇s電晶體24及NM〇s 電晶體26串聯在電壓HV或VDD及接地端GND之間，PMOS 電晶體28及NMOS電晶體30串聯在電壓HV或VDD及接地端 GND之間，電晶體24、26、28及30以及反相器32組成一 201011759 準位平移電路（level shift circuit)用以平移信號S1的準 位，進而產生信號S2以決定信鍊χτ、XTB或BLKB。在實作 上’冋壓準位平移H 20可能包含多層的準位平移電路。由 於在高壓模式時，需要使用高壓Hv，因此電晶體24、26、 28及30均為高壓元件’換言之，電晶體24、26、28及3〇 具有較尚的門檻電壓（Vth)。然而，在讀取模式時是使用電源 電壓VDD，一般就0.5UH1製程，電壓VDD的範圍在18V〜5V 之間，當電壓VDD<3V時，將需要較長的時間來打開（turn〇n) 電晶體24、26、28及30 ’故反應較慢，也就是說，在電壓 VDD較低的情形下，讀取速度下降。再者，為了使正負高壓 應用皆正常’設計PMOS電晶體24及28與陬03電晶體26 及30的尺寸比例時，故意較為懸殊，然而這將造成信號傳 輸緩慢，使得讀取速度進一步下降。 為了解決在讀取模式時因電壓VDD太低而使讀取速度 下降的問題，Kwon在美國專利第6,865,118號提出一種在 φ 半導體記憶裝置中的升壓電路，用以在讀取模式時將電壓 VDD拉高至5V以加快讀取速度，然而，此種方法將使得功 率消耗增加。 因此，一種無需增加功率消耗而能增加快閃記憶體讀取 速度的裝置，乃為所冀。 【發明内容】 本發明的目的，在於提出一種新式多次可程式化快閃記 憶體的列解碼器，其可以加快該快閃記憶體的讀取速度。 201011759 瑪器=ί發明’ 一種新式多次可程式化快閃記憶體的列解 =中:線驅動器、切換電路、高壓準位平移器及= :號及高準位平移器根據-字元線 第彳§號經該切換電路提供仏哕字亓 驅動器^時= 捷徑電路根_字元、嶋及1帽ΓΓ ί= ❿ 字元線。該_路係=元=該=:體的 式時字元線信號不用經過多層由高壓元===取模 移電路，因而能大幅減少字元線信號延遲時^^ =位平 式的讀取速度。 遲時間，增加讀取模 【實施方式】 圖4顯示多次可程式化快閃記 高麼模式時，例如執行程式化、抹除或修歹解瑪器40 ’在 位平移器46根據字元線信號Ιη及高^正操作時，高壓準 XTB_HV A BLKB_HV ^ ^ ^ t ^ 44 ^ ^ ^ ^ ^ 出傳送給字元_H 42。在讀取 千料46的輸 字元線信號In及電源電麗VDD產生4 ’捷控電路48根據 及腿_獅，切換電路44將捷。=XTL™_READ 元驅動器42。字元轉器42根據8的輸出傳送給字 號Π、XTB及BLKB驅動該快閃記憶體的電字路^所送出的信 圖5顯示圖4中捷徑電路_ = 路48是由-般邏輯元件 電路，其中捷徑電 路’捷徑電路48根據 201011759 字元線信號In產生兩個反相的信號χτ—READ及XTB_READ 至切換電路44，切換電路44根據信號RDEN及RDENB決定 是否根據捷徑電路48所輸出的信號XT_READ及XTB_READ 產生信號XT及XTB。201011759 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a multi-programmable flash memory, and in particular to an application that can speed up reading in a plurality of programmable flash memories. Speed column decoder. [Prior Art] ffl 1 shows a conventional flash memory 10 in which a column decoder 12 and a row decoder 16 drive a memory array 14 according to input signals In1 & In2, respectively, to perform stylization, erasing, correction, or Read and other operations. The read speed of the flash memory 10 is mainly delayed by the word line delay (four), and the word line delay is related to the column decoder 12. W 2 shows the column decoder 12 in the figure, wherein the word driver 18 drives the unitary line WL1 or WL2 according to the signals χτ, ΧΤΒ and BUB. In the pressing mode, the high-voltage level shifter 2 is based on the input signal Ini and The voltage HV generates signals χτ, xtb, and BLKB to the word driver ❹ 18 to perform operations such as stylization, erasing, or correction, wherein the high voltage hv is greater than the power supply voltage VDD or less than the ground potential GND, and in the read mode, the high voltage level The translator 20 generates signals XT, ΧΤΒ and BLKB to the word driver 18 in accordance with the input signal Ini and the power supply voltage vdd to perform a read operation. 3 shows a partial circuit of the high voltage level shifter 2〇, wherein the logic circuit 22 generates a signal sl according to the input signal ln1, and the pM〇s transistor 24 and the NM〇s transistor 26 are connected in series at the voltage HV or VDD and the ground GND. The PMOS transistor 28 and the NMOS transistor 30 are connected in series between the voltage HV or VDD and the ground GND. The transistors 24, 26, 28 and 30 and the inverter 32 form a 201011759 level shift circuit. The signal S1 is used to shift the level of the signal S1 to determine the signal chain χτ, XTB or BLKB. In practice, the compression level shift H 20 may comprise a multi-level level shifting circuit. Since the high voltage Hv is required in the high voltage mode, the transistors 24, 26, 28 and 30 are all high voltage elements. In other words, the transistors 24, 26, 28 and 3 have a higher threshold voltage (Vth). However, in the read mode, the power supply voltage VDD is used, which is generally 0.5UH1. The voltage VDD ranges from 18V to 5V. When the voltage is VDD<3V, it takes a long time to turn on (turn〇n). The transistors 24, 26, 28, and 30' are relatively slow to react, that is, in the case where the voltage VDD is low, the reading speed is lowered. Furthermore, in order to make the positive and negative high voltage applications all normal. When designing the size ratios of the PMOS transistors 24 and 28 and the 陬03 transistors 26 and 30, the intention is rather disparate, however, this will cause the signal transmission to be slow, and the reading speed is further lowered. In order to solve the problem that the reading speed is lowered due to the voltage VDD being too low in the read mode, a boost circuit in the φ semiconductor memory device is proposed by Kwon in U.S. Patent No. 6,865,118 for the voltage in the read mode. VDD is pulled up to 5V to speed up the reading speed, however, this method will increase the power consumption. Therefore, a device that can increase the reading speed of a flash memory without increasing power consumption is a problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide a new type of multi-programmable flash memory column decoder that can speed up the reading of the flash memory. 201011759 玛器=ί发明' A new type of multi-programmable flash memory column solution = medium: line driver, switching circuit, high-voltage level shifter and =: number and high-level shifter according to - word line The third § § is provided by the switching circuit 仏哕 亓 = = = shortcut circuit root _ character, 嶋 and 1 cap ΓΓ ί = 字 word line. The _ _ _ = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Take the speed. Late time, increase the read mode [Embodiment] Figure 4 shows the multiple programmable flash memory high mode, such as performing stylization, erasing or repairing the solver 40' in-position translator 46 according to the word line When the signal Ιη and the high ^ positive operation, the high voltage quasi-XTB_HV A BLKB_HV ^ ^ ^ t ^ 44 ^ ^ ^ ^ ^ is transmitted to the character _H 42. The switching circuit 44 will be switched on by reading the bit line signal In of the thousand material 46 and the power supply VDD generating 4'' the control circuit 48 according to the leg _ lion. =XTLTM_READ meta drive 42. The character converter 42 transmits the signal according to the output of 8 to the font number X, XTB and BLKB to drive the flash memory. The signal 5 is shown in Fig. 4. The shortcut circuit in Fig. 4 is the general logic component. The circuit, wherein the shortcut circuit 'short circuit 48 generates two inverted signals χτ_READ and XTB_READ according to the 201011759 word line signal In to the switching circuit 44, and the switching circuit 44 determines whether to output according to the shortcut circuit 48 according to the signals RDEN and RDENB. Signals XT_READ and XTB_READ generate signals XT and XTB.
❹ 圖6顯示圖4中捷徑電路48的部分電路，其中捷徑電 路48是由一般邏輯元件組成的邏輯電路，捷徑電路48根據 字元線信號In產生信號BLKB_READ至切換電路44，切換電 路44根據信號RDEN及RDENB決定是否根據捷徑電路48所 輸出的信號BLKB_READ產生信號BLKB。 在列解碼器40中，程式化、抹除及修正等操作使用由 尚壓元件組成的咼壓準位平移電路46，而讀取操作則使用 由一般邏輯元件所組成的捷徑，因此在讀取模式時不用再經 過多層的準位平移電路’故能大幅減少字元線錢化延遲 時間，同時也不再因準位平移電路的電晶體尺寸比例懸殊而 導致信號傳遞緩慢，因此能增加讀取速度，此外，由於列解 碼器40無需使用升壓電路來拉高電壓讎，因此沒有額 的劝座消拉，。 圖7顯示使用傳統列解碼器12及本發明列解碼器仙 的絲速度’在使用〇. 5um製程且電壓卿= 傳統列解碼器12的字开娩„、屈* 度/兄下’ ㈧舰ϋ 遲為23nS，而讀取操作頻率為 瑪器4°的字元線延遲為 快的讀=顯然’本發明_器40具有較 8 201011759 【圖式簡單說明】 圖1顯示習知的快閃記憶體； 圖2顯示圖1中的列解碼器； 圖3顯示高壓準位平移器的部分電路； 圖4顯示多次可程式化快閃記憶體的列解碼器； 圖5顯示圖4中捷徑電路的部分電路；以及 圖6顯不圖4中捷徑電路的部分電路。 ® 【主要元件符號說明】 10 快閃記憶體 12 列解碼器 14 記憶體陣列 16 行解碼器 18 字元線驅動器 20 高壓準位平移器 22 邏輯電路 24 PMOS電晶體 26 NMOS電晶體 28 PMOS電晶體 30 NMOS電晶體 32 反相器 40 列解碼器 42 字元線驅動器 44 切換電路 201011759 46 高壓準位平移器 48 捷徑電路6 shows a portion of the circuit of the shortcut circuit 48 of FIG. 4, wherein the shortcut circuit 48 is a logic circuit composed of general logic elements. The shortcut circuit 48 generates a signal BLKB_READ according to the word line signal In to the switching circuit 44, and the switching circuit 44 is based on the signal. RDEN and RDENB determine whether or not the signal BLKB is generated based on the signal BLKB_READ output from the shortcut circuit 48. In the column decoder 40, the operations of stylization, erasing, and correction use the squeezing level shifting circuit 46 composed of the squeezing elements, and the reading operation uses a shortcut composed of the general logic elements, so that the reading is performed. The mode does not need to go through the multi-level level shifting circuit', so the word line delay time can be greatly reduced, and the signal transmission is not slow due to the disproportion of the transistor size ratio of the level shifting circuit, so the reading can be increased. Speed, in addition, since the column decoder 40 does not need to use a boost circuit to pull up the voltage 雠, there is no amount of squeezing. Figure 7 shows the use of the conventional column decoder 12 and the column decoder of the present invention. The speed of the filament is 'in the process of using 〇. 5um and the voltage is = the word of the conventional column decoder 12 „, 屈 degree / brother's (eight) ship ϋ 23nS late, and the read operation frequency is 4° of the word line delay is fast reading = obviously 'the invention _ 40 has more than 8 201011759 [Simplified illustration] Figure 1 shows the conventional flash Figure 2 shows the column decoder of Figure 1; Figure 3 shows part of the circuit of the high-voltage level shifter; Figure 4 shows the column decoder for multiple programmable flash memory; Figure 5 shows the shortcut of Figure 4. Part of the circuit of the circuit; and Figure 6 shows part of the circuit of the shortcut circuit in Figure 4. ® [Key Symbol Description] 10 Flash Memory 12 Column Decoder 14 Memory Array 16 Row Decoder 18 Word Line Driver 20 High Voltage Level shifter 22 Logic circuit 24 PMOS transistor 26 NMOS transistor 28 PMOS transistor 30 NMOS transistor 32 inverter 40 column decoder 42 word line driver 44 switching circuit 201011759 46 high voltage level shifter 48 shortcut circuit