TWI393141B - A column decoder that can be used to speed up the read speed in a number of programmable flash memories - Google Patents

Description

Column decoder for faster read speeds in multiple programmable flash memories

The present invention relates to a multi-programmable flash memory, and more particularly to a column decoder that can be used to speed up reading in multiple programmable flash memories.

1 shows a conventional flash memory 10 in which a column decoder 12 and a row decoder 16 drive a memory array 14 in accordance with input signals In1 and In2, respectively, to perform operations such as stylization, erasing, correction, or reading. The read speed of the flash memory 10 is primarily affected by the word line delay, while the word line delay is associated with the column decoder 12. 2 shows the column decoder 12 of FIG. 1, in which the word driver 18 drives the unitary line WL1 or WL2 according to the signals XT, XTB and BLKB. In the high voltage mode, the high voltage level shifter 20 is based on the input signal In1 and the high voltage HV. The signals XT, XTB and BLKB are generated to the word driver 18 for performing operations such as stylization, erasing or correction, wherein the high voltage HV is greater than the power supply voltage VDD or less than the ground potential GND, and in the read mode, the high voltage level shifter 20 is The input signal In1 and the power supply voltage VDD generate signals XT, XTB, and BLKB to the word driver 18 to perform a read operation.

3 shows a part of the circuit of the high voltage level shifter 20, wherein the logic circuit 22 generates a signal S1 according to the input signal In1, and the PMOS transistor 24 and the NMOS transistor 26 are connected in series between the voltage HV or VDD and the ground GND, the PMOS transistor 28 and the NMOS transistor 30 are connected in series between the voltage HV or VDD and the ground GND, and the transistors 24, 26, 28 and 30 and the inverter 32 form a level shift circuit for translating the signal S1. The level, which in turn generates signal S2, determines the signal XT, XTB or BLKB. In practice, the high voltage level shifter 20 may include multiple levels of level shifting circuitry. Since the high voltage HV is required in the high voltage mode, the transistors 24, 26, 28 and 30 are all high voltage components, in other words, the transistors 24, 26, 28 and 30 have a higher threshold voltage ( _Vth ). However, in the read mode, the power supply voltage VDD is used, generally 0.5um process, and the voltage VDD ranges from 1.8V to 5V. When the voltage VDD<3V, it takes a long time to turn on. The transistors 24, 26, 28, and 30 are relatively slow to react, that is, in the case where the voltage VDD is low, the reading speed is lowered. Moreover, in order to make the positive and negative high voltage applications all normal, when designing the size ratios of the PMOS transistors 24 and 28 and the NMOS transistors 26 and 30, the intention is rather disparity, however, this will cause the signal transmission to be slow, and the reading speed is further lowered.

In order to solve the problem that the reading speed is lowered due to the voltage VDD being too low in the read mode, a boost circuit in a semiconductor memory device is proposed by Kwon in U.S. Patent No. 6,865,118 for the voltage VDD in the read mode. Pulling up to 5V to speed up the reading speed, however, this method will increase power consumption.

Therefore, a device that can increase the reading speed of a flash memory without increasing power consumption is a problem.

It is an object of the present invention to provide a new type of multi-programmable flash memory column decoder that can speed up the reading of the flash memory.

According to the present invention, a new type of multi-programmable flash memory column decoder includes a word line driver, a switching circuit, a high voltage level shifter, and a shortcut circuit, wherein in the high voltage mode, the high voltage level shifter is a word line signal and a high voltage generating a first signal are supplied to the character driver via the switching circuit to drive the word line of the flash memory. In the read mode, the shortcut circuit is based on the word line The signal and a power supply voltage generate a second signal that is supplied to the character driver via the switching circuit to drive the word line of the flash memory. The shortcut circuit is composed of general logic components, so the word line signal does not need to pass through multiple level shifting circuits composed of high voltage components in the read mode, thereby greatly reducing the word line signal delay time and increasing the read mode. Read speed.

4 shows a column decoder 40 for a plurality of programmable flash memories. In the high voltage mode, for example, when performing a program, erase or correction operation, the high voltage level shifter 46 is based on the word line signal In and the high voltage HV. The signals XT_HV, XTB_HV, and BLKB_HV are generated, and the switching circuit 44 transmits the output of the high voltage level shifter 46 to the word driver 42. In the read mode, the shortcut circuit 48 generates signals XT_READ, XTB_READ, and BLKB_READ based on the word line signal In and the power supply voltage VDD, and the switching circuit 44 transfers the output of the shortcut circuit 48 to the word driver 42. The character driver 42 drives the word lines of the flash memory based on the signals XT, XTB, and BLKB sent from the switching circuit 44.

5 shows a portion of the circuit of the shortcut circuit 48 of FIG. 4, wherein the shortcut circuit 48 is a logic circuit composed of general logic elements, and the shortcut circuit 48 is based on The word line signal In generates two inverted signals XT_READ and XTB_READ to the switching circuit 44, and the switching circuit 44 determines whether or not the signals XT and XTB are generated based on the signals XT_READ and XTB_READ output by the shortcut circuit 48 based on the signals RDEN and RDENB.

6 shows a portion of the circuit of the shortcut circuit 48 of FIG. 4, wherein the shortcut circuit 48 is a logic circuit composed of general logic elements. The shortcut circuit 48 generates a signal BLKB_READ to the switching circuit 44 according to the word line signal In, and the switching circuit 44 is based on the signal RDEN. And RDENB determines whether or not the signal BLKB is generated based on the signal BLKB_READ output from the shortcut circuit 48.

In the column decoder 40, the operations of stylization, erasing, and correction use a high voltage level shifting circuit 46 composed of high voltage elements, and the reading operation uses a shortcut composed of general logic elements, so in the read mode. There is no need to go through the multi-level level shifting circuit, so the delay time of the word line signal In can be greatly reduced, and the signal transmission is not slow due to the disproportion of the transistor size ratio of the level shifting circuit, so the reading speed can be increased. Furthermore, since the column decoder 40 does not need to use a boost circuit to pull up the voltage VDD, there is no additional power consumption.

7 shows the read speed using the conventional column decoder 12 and the column decoder 40 of the present invention. In the case where the 0.5 um process is used and the voltage VDD = 3 V, the word line delay of the conventional column decoder 12 is 23 ns, while reading Taking the operating frequency as 21.7 Mhz, the word line delay of the column decoder 40 of the present invention is 15 ns, and the read operation frequency is 33 Mhz. Obviously, the column decoder 40 of the present invention has a faster reading speed.

10‧‧‧Flash memory

12‧‧‧ column decoder

14‧‧‧Memory array

16‧‧‧ line decoder

18‧‧‧Word line driver

20‧‧‧High-pressure level shifter

22‧‧‧Logical Circuit

24‧‧‧ PMOS transistor

26‧‧‧NMOS transistor

28‧‧‧ PMOS transistor

30‧‧‧ NMOS transistor

32‧‧‧Inverter

40‧‧‧ column decoder

42‧‧‧Word line driver

44‧‧‧Switching circuit

46‧‧‧High-pressure level shifter

48‧‧‧ Shortcut Circuit

1 shows a conventional flash memory; FIG. 2 shows the column decoder of FIG. 1; FIG. 3 shows a part of the circuit of the high voltage level shifter; and FIG. 4 shows a column decoder of a plurality of programmable flash memories. FIG. 5 shows a portion of the circuit of the shortcut circuit of FIG. 4; FIG. 6 shows a portion of the circuit of the shortcut circuit of FIG. 4; and FIG. 7 shows the reading speed using the conventional column decoder and the column decoder of the present invention.

40‧‧‧ column decoder

42‧‧‧Word line driver

44‧‧‧Switching circuit

46‧‧‧High-pressure level shifter

48‧‧‧ Shortcut Circuit

Claims (4)

A column decoder for multi-programmable flash memory, the flash memory comprising a plurality of word lines, the column decoder comprising: a driver, driving the plurality of word lines according to a first signal; a high voltage level shifter, generating a second signal according to a first voltage and a word line signal; a shortcut circuit generating a third signal according to the word line signal and a second voltage; and a switching circuit In the high voltage mode, the second signal is selected as the first signal, and in the read mode, the third signal is selected as the first signal. A decoder according to claim 1, wherein the shortcut circuit comprises a logic circuit. The decoder of claim 1, wherein the first voltage is greater than the second voltage. A decoder as claimed in claim 1, wherein the first voltage is less than a ground potential.