CN101777382B

CN101777382B - Column decoder of multiple programmable flash memory

Info

Publication number: CN101777382B
Application number: CN2009100014569A
Authority: CN
Inventors: 吴伯豪; 冯信彰
Original assignee: Elan Microelectronics Corp
Current assignee: Elan Microelectronics Corp
Priority date: 2009-01-09
Filing date: 2009-01-09
Publication date: 2012-04-04
Anticipated expiration: 2029-01-09
Also published as: CN101777382A

Abstract

The invention provides a column decoder of a novel multiple programmable flash memory, which comprises a high-voltage quasi-level translation device and a shortcut circuit. When the column decoder executes operations, such as programming, erasing or editing, and the like, the high-voltage quasi-level translation device generates a first signal according to a character element line signal and a high voltage which is larger than a power source voltage or smaller than a grounding level so as to drive a character element line of the flash memory. When the column decoder executes reading operation, the shortcut circuit generates a second signal according to the power supply voltage and the character element line signal so as to drive the character element line of the flash memory, and the shortcut circuit comprises common logic elements so that the delay of the character element line signal can be shortened, and accordingly the reading speed is increased.

Description

The column decoder of multiple programmable flash memory

Technical field

The invention relates to a kind of multiple programmable flash memory, particularly about a kind of column decoder that to accelerate reading speed in the multiple programmable flash memory that is applied in.

Background technology

Fig. 1 shows known flash memory 10, and wherein column decoder 12 and row decoder 16 drive memory array 14 according to input signal In1 and In2 respectively, and then carries out and operation such as programme, erase, revise or read.The reading speed of flash memory 10 mainly receives the influence of character wire delay, and the character wire delay is then relevant with column decoder 12.Column decoder 12 in Fig. 2 displayed map 1; Wherein character driver 18 drives character line WL1 or WL2 according to signal XT, XTB and BLKB; When high pressure mode; The accurate position of high pressure translation device 20 produces signal XT, XTB and BLKB according to input signal In1 and high pressure HV and gives character driver 18 to carry out programming, to erase or operation such as correction; Its mesohigh HV is greater than supply voltage VDD or less than earthing potential GND, and when read mode, the accurate position of high pressure translation device 20 gives character driver 18 to carry out read operation according to input signal In1 and supply voltage VDD generation signal XT, XTB and BLKB.

Fig. 3 shows the partial circuit of the accurate position of high pressure translation device 20; Wherein logical circuit 22 produces signal S1 according to input signal In1; PMOS transistor 24 and nmos pass transistor 26 are connected between voltage HV or VDD and the earth terminal GND; PMOS transistor 28 and nmos pass transistor 30 are connected between voltage HV or VDD and the earth terminal GND;

Transistor

24,26,28 and 30 and phase inverter 32 form surely position translation circuit (level shift circuit) in order to the accurate position of translation signal S1, and then produce signal S2 with decision signal XT, XTB or BLKB.On real the work, the accurate position of high pressure translation device 20 possibly comprise the accurate position translation circuit of multilayer.Because when high pressure mode, need to use high pressure HV, so

transistor

24,26,28 and 30 is high voltage device, in other words,

transistor

24,26,28 and 30 has higher threshold voltage (V _Th).Yet, when read mode, be to use supply voltage VDD, generally with regard to 0.5um technology; The scope of voltage VDD is between 1.8V～5V, and when voltage VDD＜3V, the time that needs are long is opened (turn on)

transistor

24,26,28 and 30; So reaction is slower; That is to say that under the lower situation of voltage VDD, reading speed descends.Moreover all normal for positive or negative high voltage is used, design

PMOS transistor

24 and 28 is during with the dimension scale of

nmos pass transistor

26 and 30, intentional great disparity comparatively, however this will cause the signal transmission slow, make reading speed further descend.

In order to solve the problem that because of voltage VDD is too low reading speed is descended when the read mode; Kwon is at United States Patent (USP) the 6th; A kind of booster circuits in semiconductor storage are proposed for 865, No. 118, in order to when the read mode with voltage VDD draw high to 5V to accelerate reading speed; Yet this kind method will make power consumption increase.

Therefore, need a kind of device that need not to increase power consumption and can increase the flash memory reading speed.

Summary of the invention

The object of the invention is to propose a kind of column decoder of new-type multiple programmable flash memory, and it can accelerate the reading speed of this flash memory.

According to the present invention; A kind of column decoder of new-type multiple programmable flash memory comprises character line drive, commutation circuit, high pressure accurate position translation device and shortcut circuit; Wherein when high pressure mode; The accurate position of this high pressure translation device produces one first signal according to a character line signal and a high pressure and offers this character driver through this commutation circuit, to drive the character line of this flash memory, when read mode; This shortcut circuit produces a secondary signal according to this character line signal and a supply voltage and offers this character driver through this commutation circuit, to drive the character line of this flash memory.Therefore this shortcut circuit is made up of general logic element, and character line signal need not pass through the accurate position translation circuit that multilayer is made up of high voltage device when read mode, thereby can significantly reduce character line signal delay time, the reading speed of increase read mode.

Description of drawings

Fig. 1 shows known flash memory;

Column decoder in Fig. 2 displayed map 1;

Fig. 3 shows the partial circuit of the accurate position of high pressure translation device;

Fig. 4 shows the column decoder of multiple programmable flash memory;

The partial circuit of shortcut circuit in Fig. 5 displayed map 4;

The partial circuit of shortcut circuit in Fig. 6 displayed map 4; And

Fig. 7 shows the reading speed of using traditional column decoder and column decoder of the present invention.

Drawing reference numeral:

10 flash memories

12 column decoders

14 memory arrays

16 row decoders

18 character line drives

The accurate position of 20 high pressure translation device

22 logical circuits

24 PMOS transistors

26 nmos pass transistors

28 PMOS transistors

30 nmos pass transistors

32 phase inverters

40 column decoders

42 character line drives

44 commutation circuits

The accurate position of 46 high pressure translation device

48 shortcut circuit

Embodiment

Fig. 4 shows the column decoder 40 of multiple programmable flash memory; When high pressure mode; For example carry out programming, erase or during correction operations; The accurate position of high pressure translation device 46 produces signal XT_HV, XTB_HV and BLKB_HV according to character line signal In and high pressure HV, and commutation circuit 44 sends the output of the accurate position of high pressure translation device 46 to character line drive 42.When read mode, shortcut circuit 48 produces signal XT_READ, XTB_READ and BLKB_READ according to character line signal In and supply voltage VDD, and commutation circuit 44 sends the output of shortcut circuit 48 to character driver 42.The signal XT that character driver 42 is seen off according to commutation circuit 44, XTB and BLKB drive the character line of this flash memory.

The partial circuit of shortcut circuit 48 in Fig. 5 displayed map 4; The logical circuit formed by general logic element of shortcut circuit 48 wherein; Signal XT_READ and XTB_READ that shortcut circuit 48 produces two anti-phases according to character line signal In be to commutation circuit 44, and signal XT_READ and XTB_READ that whether commutation circuit 44 is exported according to shortcut circuit 48 according to signal RDEN and RDENB decision produce signal XT and XTB.

The partial circuit of shortcut circuit 48 in Fig. 6 displayed map 4; The logical circuit formed by general logic element of shortcut circuit 48 wherein; Shortcut circuit 48 produces signal BLKB_READ to commutation circuit 44 according to character line signal In, and commutation circuit 44 determines the signal BLKB_READ that whether is exported according to shortcut circuit 48 to produce signal BLKB according to signal RDEN and RDENB.

In column decoder 40; Programme, erase and correction etc. manipulated the accurate position translation of the high pressure circuit of being made up of high voltage device 46, and read operation then uses the shortcut of being made up of general logic element, therefore when read mode, need not pass through the standard position translation circuit of multilayer again; So can significantly reduce character line signal In time delay; While also no longer because of the transistor size ratio great disparity of accurate position translation circuit causes the signal transmission slow, therefore can increase reading speed, in addition; Because column decoder 40 need not to use booster circuit to draw high voltage VDD, therefore there is not extra power consumption.

Fig. 7 shows the reading speed of using traditional column decoder 12 and column decoder of the present invention 40; Under the situation of using 0.5um technology and voltage VDD=3V, the character wire delay of traditional column decoder 12 is 23ns, and the read operation frequency is 21.7Mhz; The character wire delay of column decoder 40 of the present invention is 15ns; And read to occupy operating frequency is 33Mhz, and obviously, column decoder 40 of the present invention has reading speed faster.

Claims

1. the column decoder of a multiple programmable flash memory, said flash memory comprises many character lines, it is characterized in that, and said column decoder comprises:

One driver drives said many character lines according to one first signal;

The accurate position of one high pressure translation device produces a secondary signal according to one first voltage and a character line signal;

One shortcut circuit produces one the 3rd signal according to said character line signal and one second voltage; And

One switches circuit, when high pressure mode, chooses said secondary signal as said first signal, when read mode, chooses said the 3rd signal as said first signal;

Wherein, said first voltage is high pressure HV, and said second voltage is supply voltage VDD, and said high pressure HV is greater than said supply voltage VDD or less than earthing potential GND.

2. column decoder as claimed in claim 1 is characterized in that, said shortcut circuit comprises a logical circuit.