TWI442402B - Control driver for non-volatile memory - Google Patents

Description

Control driver for non-volatile memory

The present invention relates to a column decoder for a memory, and more particularly to a column decoder and a method thereof for reducing memory stylization difficulty and layout area thereof.

Flash memory is a non-volatile memory commonly used in memory cards, flash devices, and handheld electronic devices for the storage and transfer of data. Flash memory can be written and deleted by power-on. The advantages of flash memory include fast access times and shock resistance. In addition, flash memory is also very resistant to stress and temperature changes.

Please refer to FIG. 1 , which is a schematic diagram of the previous column driving circuit 10 . In order to program the flash memory unit, the location of the memory unit must be decoded by the decoder selecting the block including the memory unit, and after the position of the memory unit is decoded, the word line of the memory unit can be determined. . The column driver circuit 10 is used to drive the memory cells in the memory block to read, write, and erase the data of the memory cells. The column driving circuit 10 includes eight inverse gates 100 for receiving the memory block selection signals XPA, XPB, XPC, eight level up shift circuits 121, eight level down shift circuits 122, and eight Pull-up transistor MP, eight pull-down transistors MN, and eight reset transistors M_RESET. The column driving circuit 10 outputs an octet word line selection signal ZWL<7:0> for selecting a word line of the memory unit to be accessed, and the reset signal ZXWV<7:0> is used to control resetting. Transistor M_RESET.

Please refer to FIG. 2, which is a schematic diagram of a level up shift circuit 121. Each of the level up shift circuits 121 includes a first N-type MOS transistor MN1, a first P-type MOS transistor MP1, a second N-type MOS transistor MN2, and a second P-type MOS half. The transistor MP2, and the inverter 200. The gate terminal of the first N-type MOS transistor MN1 receives the input voltage of the input level up shift circuit 121. At the same time, the input voltage is also reversed by the inverter 200, and the inverted input voltage is output to the gate terminal of the second N-type MOS transistor MN2. The first N-type MOS transistor MN1 and the first P-type MOS transistor M1 operate like an inverter and output a first reverse signal to the gate terminal of the second P-type MOS transistor MP2. Similarly, the second N-type MOS transistor MN2 and the second P-type MOS transistor MP2 operate similarly to the inverter, and output a second reverse signal to the first P-type MOS transistor MP1. The gate is extreme. Therefore, if the input signal is a logic high potential, the output voltage of the terminal up-shift circuit 121 at the 汲 terminal of the second N-type MOS transistor MN2 and the second P-type MOS transistor M2 will be a high voltage. VPP. Conversely, if the input signal is logic low, the output voltage will be a low voltage, such as a ground voltage.

Please refer to FIG. 3, which is a schematic diagram of a level shifting circuit 122. Each of the level downward transfer circuits 122 includes a first N-type MOS transistor MN1, a first P-type MOS transistor M1, a second N-type MOS transistor MN2, and a second P-type gold oxide. Semi-transistor MP2, and inverter 200. The gate terminal of the first P-type MOS transistor MP1 receives the input voltage of the input level down-transfer circuit 122. At the same time, the input voltage is also reversed by the inverter 200, and the inverted input voltage is output to the gate terminal of the second P-type MOS transistor MP2. The first N-type MOS transistor MN1 and the first P-type MOS transistor M1 operate like an inverter and output a first reverse signal to the gate terminal of the second N-type MOS transistor MN2. Similarly, the second N-type MOS transistor MN2 and the second P-type MOS transistor MP2 operate similarly to the inverter, and output a second reverse signal to the first N-type MOS transistor MN1. The gate is extreme. Therefore, if the input signal is logic low, the output voltage of the level-down shift circuit 122 at the 汲 terminal of the second N-type MOS transistor MN2 and the second P-type MOS transistor M2 will be low. Voltage VBB. If the input signal is logic high, the output voltage will be high voltage VDD. The high voltage VDD can be equal to or lower than the high voltage VPP.

There are two conditions for the input voltage of the level up shift circuit 121 and the level down shift circuit 122. If the input voltage is high, the level up shift circuit 121 will output a high voltage VPP to the pull up transistor MP, and the level down shift circuit 122 will output a high voltage VDD to the pull down transistor MN. If the input voltage is low, the level up shift circuit 121 will output a low voltage, such as a ground voltage, and the level down shift circuit 122 will output a low voltage VBB. Therefore, the word line select signal ZWL<7:0> will have 7 VPP outputs and one XWV output. For example, the word line select signal ZWL<1> has a voltage of the signal XWV<1>, and the word line select signal ZWL<7:2>, and the ZWL<0> has a high voltage VPP. Please refer to FIG. 4, which is a schematic diagram of a flash memory cell array driven by the driving circuit of the first row. As shown in FIG. 4, the word line selection signal ZWL can be used to enable the flash memory unit in the flash memory cell array to control the flash memory unit for reading and writing.

The column drive circuit 10 includes a level up shift circuit 121, a level down shift circuit 122, a pull up transistor MP, a pull down transistor MN, and a reset transistor M_RESET. Therefore, the architecture of the column driver circuit 10 is complex and can take up a lot of wafer area.

An embodiment of the present invention discloses a control driver for a non-volatile memory. The non-volatile memory control driver includes a first driving circuit, a first level up shift circuit, and a first selection circuit. . The first driving circuit includes a first pull-up transistor and a first pull-down transistor. The first pull-up transistor is configured to pull up a first control line selection signal according to a first pull-up signal, and the first pull-down transistor is configured to pull down the first control line according to the first pull-up signal Select the signal. The first pull-up transistor includes a first end, a second end, and a control end. The first end pulls the first control line to select a signal to the first control line voltage, the second end is configured to receive the first control line voltage, and the control end is configured to receive the first pull-up signal And when the voltage of the first pull-up signal is less than the voltage of the first control line, the control terminal is configured to turn on the first pull-up transistor. The first pull-down transistor includes a first end, a second end, and a control end. The first end is coupled to the first end of the first pull-up transistor for pulling down the first control line select signal to approximately a low power supply voltage, and the second end is configured to receive the low power supply voltage, And the control terminal is configured to receive the first pull-up signal, and when the voltage of the first pull-up signal is greater than the low power supply voltage, turn on the first pull-down transistor. The first level up shifting circuit has an output end coupled to the control end of the first pull-up transistor and the control end of the first pull-down transistor for outputting the first Pull up the signal. The first level up shifting circuit receives a first selection signal, and when the first selection signal is enabled, the first pull signal is outputted as a first voltage, but when the first selection signal is not When possible, the first pull-up signal is outputted as a second voltage. The first selection circuit is coupled to the first level up shift circuit for outputting the first selection signal. The first selection circuit receives a plurality of first decoded signals, and when the plurality of first decoded signals are enabled, enabling the first selected signal, but when the first decoded signals of the plurality of first decoded signals are not present, When enabled, the first selection signal is not enabled.

Please refer to FIG. 5, which is a schematic diagram of a control line architecture according to an embodiment of the present invention. The control line architecture includes a plurality of memory array segments 500a, ..., 500g. In each memory array segment, each block in the memory array can be selected by decoding signals PA<14:8>. The decoding signals PA<14:8> can be divided into control line decoding signals PA<11:8> and sector decoding signals PA<14:12>. The control line decode signal PA<11:8> can be used to generate the control line voltage ZCLV<15:0>.

Please refer to FIG. 6. FIG. 6 is a block diagram of a gate drive selection for an embodiment of the present invention. The memory array 620 includes a plurality of memory array segments 621[0], 621[1], 621[2], 621[3], and the blocks of the memory array segments can select signals through a plurality of control lines respectively. ZCL<127:0>, ZCL<128:255>, ZCL<256:383>, ZCL<384:511> to select. The control line selection signal ZCL<0:511> can be generated by the pre-decoder 600, and the pre-decoder 600 receives the decoded signal A<8:16>, and generates a memory block selection signal XPA<3:0>, XPB<3. :0>, XPC<3:0>, and generate control signals XCT<7:0> based on the decoded signals A<8:16>. The control signals XCT<7:0> can be rotated to generate a quasi-displacement control signal XT<7:0> and a reverse quasi-displacement control signal XTB<7:0>. Then, based on the memory block selection signals XPA<3:0>, XPB<3:0>, XPC<3:0>, the quasi-displacement control signal XT<7:0>, and the reverse quasi-displacement control signal XTB<7:0> to generate the control line selection signal ZCL<0:511>.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of a plurality of column driving circuits in a stylized mode according to an embodiment of the present invention. The "column" in the first column of driving circuits includes a first driving circuit A, a second driving circuit B, a first level up shift circuit 721, and a first selection circuit 711. The first level up shift circuit 721 is coupled to the first and second drive circuits A and B for outputting the first pull-up signal PU1, and the first selection circuit 711 is coupled to the first level up shift circuit 721. To output the first selection signal. The first selection circuit 711 can be a gate or a reverse gate. The "column" in the second column of driving circuits includes a third driving circuit C, a fourth driving circuit D, a second level up shift circuit 722, and a second selection circuit 712. The second level up shift circuit 722 is coupled to the third and fourth drive circuits C and D for outputting the second pull-up signal PU2, and the second selection circuit 712 is coupled to the second level up shift circuit 722. To output a second selection signal. The second selection circuit can be a gate or a reverse gate. The first driving circuit A includes a first pull-up transistor MP_A for pulling up the first control line selection signal ZCL<0> according to the first pull-up signal PU1. The first pull-up transistor MP_A is a P-type MOS transistor, which includes a first end, a second end, and a control end. a first end of the first pull-up transistor MP_A, such as a 汲 terminal, for outputting a first control line select signal ZCL<0> to a first control line voltage ZCLV<0>; a second end, such as a source terminal, Receiving a first control line voltage ZCLV<0>; a control terminal, such as a gate terminal, for receiving the first pull-up signal PU1 and when the voltage of the first pull-up signal PU1 is less than the first control line voltage ZCLV<0>, The first pull-up transistor MP_A is turned on. The first driving circuit A further includes a first pull-down transistor MN_A for pulling down the first control line selection signal ZCL<0> according to the first pull-up signal PU1. The first pull-down transistor MN_A is an N-type MOS transistor, including a first end, a second end, and a control end. The first end of the first pull-down transistor MN_A, for example, the 汲 terminal, is coupled to the first end of the first pull-up transistor MP_A for outputting the first control line selection signal ZCL<0> to a low power supply voltage VBC a second end, such as a source terminal, for receiving a low power supply voltage; a control terminal, such as a gate terminal, for receiving the first pull-up signal PU1 and when the voltage PU1 of the first pull-up signal is greater than the low power supply voltage VBC , the first pull-down transistor MN_A is turned on. The output of the first level up-shift circuit 721 is directly coupled to the gate of the first pull-up transistor MP_A of the first driving circuit A and the gate of the first pull-down transistor MN_A for outputting the first pull-up Signal PU1. The output of the first level up shift circuit 721 is also directly coupled to the gate of the second pull-up transistor MP_B of the second driver circuit B and the gate of the second pull-down transistor MN_B. The first level up shift circuit 721 receives the first select signal. When the first select signal is enabled, the first level up shift circuit 721 outputs the first pull up signal PU1 at the first voltage GND, for example, 0V. When the first selection signal is not enabled, the first level up shift circuit 721 outputs the first pull-up signal PU1 at the second voltage VP5, for example, 5.5V. The first selection circuit 711 is coupled to the first level up shift circuit 721 for outputting the first selection signal. The first selection circuit 711 receives a plurality of first decoded signals XPA, XPB, and XPC. When all of the first decoded signals XPA, XPB, and XPC are enabled, the first selection circuit 711 will enable the first selection signal, and when the first decoded signals XPA, XPB, and XPC have a first decoded signal XPA, XPB When the XPC is not enabled, the first selection circuit 711 will not enable the first selection signal. Regarding the "enable" of the first selection signal, if the first selection circuit 711 is a gate, "enable" represents the output logic high level signal, but if the first selection circuit 711 is a reverse gate, "enable" "Represents the output logic low level signal. The same applies to the second selection circuit 721 and the second selection signal.

Please refer to Figure 7, there are 128 control line selection signals ZCL<0:127> for this architecture, 16 control line voltages ZCLV<0:15> and 8 drive circuit "columns" can be used in an array The control line selection signal ZCL<0:127> is generated. For example, the second driving circuit B can be used to generate the second control line selection signal ZCL<15>, the third driving circuit C can be used to generate the third control line selection signal ZCL<112>, and the fourth driving circuit D can be used to generate the first The four control lines select the signal ZCL<127>. The first pull-up signal PU1 can be used to control the control line selection signal ZCL<0:15>, and the second pull-up signal PU2 can be used to control the control line selection signal ZCL<112:127>. Then, the pull-up signal for each driver circuit "column" can be selected by decoding signals XPA, XPB, and XPC. Each combination of the decoded signals XPA, XPB, and XPC is a binary signal that corresponds to each column in the "column" of the driver circuit. Therefore, in the stylized mode, Figure 7 is enabled by the drive circuit "column" and the control line voltage ZCLV<0:15>, one of which can generate the control line select signal to the control line voltage, and other drive circuits. A control line selection signal can be generated to the low power supply voltage VBC. For example, in FIG. 7, the first driving circuit can be selected by the decoding signals XPA, XPB, XPC and the first control line voltage ZCLV<0>, such that the first control line selection signal ZCL<0> will output the first control line voltage. ZCLV<0>, for example 5.5V. The second drive circuit B, the third drive circuit C, and the fourth drive circuit D all output a low power supply voltage, for example, 3.3V. Therefore, although the second driving circuit B receives the enabled first pull-up signal PU1, since the second control line voltage ZCLV<15> is not enabled, for example, 3.3V, the second driving circuit B outputs the second control. The line voltage ZCLV<15>, for example 3.3V. The third drive circuit C receives the enabled first control line voltage ZCLV<0>, for example 5.5V. However, since the second pull-up signal PU2 is not enabled, the pull-up transistor MP_C of the third driving circuit C is turned off, and the pull-down transistor MN_C of the third driving circuit C is turned on, so that the third control line selection signal ZCL<112> The low supply voltage VBC is output, for example 3.3V. In the above embodiment, the low power supply voltage VBC and the non-enable control line voltage ZCLV may be the same, for example, 3.3V, however, the low power supply voltage VBC and the non-enabled control line voltage ZCLV may also be different.

Figure 8 In the read mode, the low power supply voltage VBC can be as low as 0V, and the operation of the column drive circuit can be performed as follows. When reading data from the memory, the control line select signal ZCL<0:127> remains at the read voltage, for example 3.3V. Thus, the pull-up transistors MP_A, MP_B, MP_C, MP_D of the drive circuits A, B, C, D must be turned on and pull up the control line selection signal ZCL<0:127> to the read voltage. Therefore, the pull-up signals PU1, PU2 are maintained at the first voltage GND, for example 0V, for turning on the pull-up transistors MP_A, MP_B, MP_C, MP_D and turning off the pull-down transistors MN_A, MN_B, MN_C, MN_D.

Figure 9 In the erase mode, the low power supply voltage VBC can be as low as -6V, and the operation of the column drive circuit can be performed as follows. When the data is erased from the memory, the control line selection signal ZCL<0:127> is held at the erase voltage, for example -6V. Thus, the pull-down transistors MN_A, MN_B, MN_C, MN_D must be turned on and the pull-down control line selection signal ZCL<0:127> to the low power supply voltage VBC. In order to turn off the pull-up transistors MP_A, MP_B, MP_C, MP_D, the pull-up signals PU1, PU2 must be maintained at the first voltage GND, such as 0V, and the control line voltage ZCLV<0:15> is to be maintained at the second voltage, for example 0V. Since the source voltages of the pull-up transistors MP_A, MP_B, MP_C, and MP_D are not higher than the gate voltage, the pull-up transistors MP_A, MP_B, MP_C, and MP_D remain off.

In summary, the above embodiment of the control driver utilizes a single quasi-displacement circuit, such as a level up shift circuit, a pull up transistor, and a pull down transistor, to make the control driver simpler and reduce the wafer area.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Column drive circuit

100. . . Reverse or gate

121. . . Level up shift circuit

122. . . Level shifting circuit

200. . . Inverter

500a~500g, 621[0]~621[3]. . . Memory array section

600. . . Predecoder

620. . . Memory array

711. . . First selection circuit

712. . . Second selection circuit

721. . . First level up shift circuit

722. . . Second level up shift circuit

A. . . First drive circuit

B. . . Second drive circuit

C. . . Third drive circuit

D. . . Fourth drive circuit

MP, MP1, MP2, MP_A, MP_B, MP_C, MP_D. . . Pull-up transistor

MN, MN1, MN2, MN_A, MN_B, MN_C, MN_D. . . Pull down transistor

M_RESET. . . Reset transistor

PA, A<8:16>. . . Decoding signal

PU1. . . First pull signal

PU2. . . Second pull signal

VBB. . . low voltage

VBC. . . Low power supply voltage

VPP, VDD. . . high voltage

XPA<3:0>, XPB<3:0>, XPC<3:0>. . . Memory block selection signal

XPA, XPB, XPC. . . First decoding signal

XCT. . . Control signal

XT. . . Quasi-displacement control signal

XTB. . . Reverse quasi-displacement control signal

ZCLV. . . Control line voltage

ZCL. . . Control line selection signal

ZWL. . . Word line selection signal

ZXWL, ZXWV. . . Reset signal

Figure 1 is a schematic diagram of a prior column drive circuit.

Fig. 2 is a schematic diagram showing the level shifting circuit of the column driving circuit in Fig. 1.

Figure 3 is a schematic diagram of the level shifting circuit of the column driver circuit in Figure 1.

Figure 4 is a schematic diagram of a flash memory cell array driven by the driver circuit of Figure 1.

Figure 5 is a schematic diagram of a control line architecture in accordance with an embodiment of the present invention.

Figure 6 is a block diagram of a gate drive selection for an embodiment of the present invention.

Figure 7 is a schematic diagram of a plurality of control drivers in a stylized mode in accordance with an embodiment of the present invention.

Figure 8 is a schematic diagram of the plurality of control drivers in the read mode of Figure 7.

Figure 9 is a schematic diagram of a plurality of control drivers in the erase mode in Figure 7.

500a~500g‧‧‧ memory array segment

PA<11:8>‧‧‧Control line decoding signal

ZCLV‧‧‧ control line voltage

Claims (10)

A control driver for a non-volatile memory, the control driver comprising: a first driving circuit comprising: a first pull-up transistor for pulling up a first control line to select a signal according to a first pull-up signal, The first pull-up crystal includes: a first end, wherein the first control line is used to select a signal to approximately a first control line voltage; a second end is configured to receive the first control line voltage; and a control The terminal is configured to receive the first pull-up signal, and when the voltage of the first pull-up signal is less than the first control line voltage, turn on the first pull-up transistor; and a first pull-down transistor, The first pull-down transistor is configured to pull down the first control line according to the first pull-up signal, and the first pull-down transistor includes: a first end coupled to the first end of the first pull-up transistor for pulling down the The first control line selects a signal to a low power supply voltage, wherein when the non-volatile memory operating mode is in a stylized mode, the low power supply voltage is a voltage between the first control line voltage and the ground voltage Non-volatile record When the operation mode of the body is a read mode, the low power supply voltage is a ground voltage; and in the non-volatile memory operation mode is an erase mode, the low power supply voltage is a negative voltage lower than one of the ground voltage; a second end for receiving the low power supply voltage; a control terminal for receiving the first pull-up signal, and when the voltage of the first pull-up signal is greater than the low power supply voltage, turning on the first pull-down transistor; a first level up shift circuit An output end directly coupled to the control end of the first pull-up transistor and the control end of the first pull-down transistor for outputting the first pull-up signal, the first level is upward The shifting circuit receives a first selection signal. When the first selection signal is enabled, the first pull-up signal is outputted by a first voltage, and when the first selection signal is disabled, the first The pull-up signal is outputted by a second voltage; and a first selection circuit coupled to the first level up shift circuit for outputting the first selection signal, the first selection circuit receiving the plurality of first decoding a signal, when the plurality of first decoded signals are enabled, enabling the first selection signal, and when the first decoded signal of the plurality of first decoded signals is not enabled, the first A selection signal. The control driver of claim 1, wherein the first pull-up transistor is a P-type MOS transistor, and the first pull-down transistor is an N-type MOS transistor. The control driver of claim 1, wherein the first selection circuit is a reverse gate and the first voltage is lower than the second voltage. The control driver of claim 1, further comprising: a second driving circuit coupled to the first level up shift circuit, the second driver The circuit includes: a second pull-up transistor for pulling up a second control line selection signal according to the first pull-up signal, the second pull-up transistor includes: a first end for outputting the first a second control line selection signal, the second control line selection signal is at a second control line voltage; a second end is for receiving the second control line voltage; and a control terminal is directly coupled to the The output terminal of the first level up shift circuit is configured to receive the first pull-up signal, and when the voltage of the first pull-up signal is less than the voltage of the second control line, the control end is used to enable the a second pull-up transistor; and a second pull-down transistor for pulling down the second control line selection signal according to the first pull-up signal, the second pull-down transistor includes: a first end coupled to the The first end of the second pull-up transistor is configured to output the second control line selection signal, the second control line selection signal is at a level of the low power supply voltage; and a second end is configured to receive the second control line Low power supply voltage, and a control terminal, direct coupling The output terminal of the first level up shift circuit is configured to receive the first pull-up signal, and when the voltage of the first pull-up signal is greater than the low power supply voltage, the control end is used to enable the first Two pull down the transistor. The control driver of claim 4, wherein the first selection circuit is a reverse gate and the first voltage is lower than the second voltage. The control driver of claim 4, further comprising: a third driving circuit, comprising: a third pull-up transistor for pulling up a third control line selection signal according to a second pull-up signal, The third pull-up transistor includes: a first end for outputting the third control line selection signal, the first control line selection signal is at a level of the first control line voltage; and a second end receives the a first control line voltage; and a control terminal for receiving the second pull-up signal, and when the voltage of the second pull-up signal is less than the first control line voltage, the control terminal is configured to enable the third pull-up And a third pull-down transistor for pulling down the third control line selection signal according to the second pull-up signal, the third pull-down transistor includes: a first end coupled to the third pull-up The first end of the crystal is configured to output the third control line selection signal, the third control line selection signal is at a level of the low power supply voltage; and a second end is configured to receive the low power supply voltage; And a control terminal for receiving the second Pulling up the signal, and when the voltage of the second pull-up signal is greater than the low power supply voltage, the control end is used to turn on the third pull-down transistor; and the second level is up-shifting circuit, having an output end, The output end is directly coupled to the control end of the third pull-up transistor and the control end of the third pull-down transistor for outputting the second pull-up signal, and the second level is shifted upward Receiving a second selection signal, when the second selection signal is enabled, the second pull-up signal is outputted by the first voltage, and when the second selection signal is disabled, the second The second selection circuit is coupled to the second level up shift circuit for outputting the second selection signal, and the second selection circuit receives the plurality of second decoded signals. When the plurality of second decoded signals are enabled, the second selection signal is enabled, and when the second decoded signal of the plurality of second decoded signals is not enabled, the second selection is not enabled. Signal. The control driver of claim 6, wherein the first selection circuit is a reverse gate, the second selection circuit is a reverse gate, and the first voltage is lower than the second voltage. The control driver of claim 1, further comprising: a third driving circuit, comprising: a third pull-up transistor for pulling up a third control line to select a signal according to a second pull-up signal, the The three-up pull-up transistor includes: a first end for outputting the third control line selection signal, the third control line selecting the signal level to be at a first control line voltage; and a second end for receiving The first control line voltage; and a control terminal for receiving the second pull-up signal, and when the voltage of the second pull-up signal is less than the first control line voltage, the control end is used to open the third pull-up a transistor; and a third pull-down transistor for pulling down the third according to the second pull-up signal a control line selection signal, the third pull-down transistor includes: a first end coupled to the first end of the third pull-up transistor for outputting the third control line selection signal, the third control line The level of the selection signal is about the low power supply voltage; a second end is for receiving the low power supply voltage, and a control terminal is for receiving the second pull-up signal, and when the second pull-up signal When the voltage is greater than the low power supply voltage, the control terminal is used to open the third pull-down transistor; a second level upward shift circuit has an output end, and the output terminal is directly coupled to the third pull-up The control terminal of the transistor and the control terminal of the third pull-down transistor are configured to output the second pull-up signal, and the second level-up shift circuit receives a second select signal when the second select signal When the second pull-up signal is enabled, the second pull-up signal is outputted by the first voltage, and when the second select signal is disabled, the second pull-up signal is output by the second voltage; and a second selection a circuit coupled to the second level up shift circuit For outputting the second selection signal, the second selection circuit receives a plurality of second decoding signals, and when the plurality of second decoding signals are enabled, enabling the second selection signal, and when the plurality of When the second decoded signal is not enabled in the second decoded signal, the second selected signal is not enabled. The control driver of claim 8, wherein the first selection circuit is a reverse gate, the second selection circuit is a reverse gate, and the first voltage is lower than the second voltage. The control driver of claim 1, wherein the low power supply voltage is equal to the second control line voltage when the non-volatile memory is in the stylized mode.