JP2016116157A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a push-pull type output circuit capable of driving a load of an output node at a higher speed.SOLUTION: An output circuit 100 comprises: a latch circuit 20; a CMOS inverter P1/N1; and a negative voltage generating circuit 220 for changing a voltage of a pull-up node PU to a negative voltage. The negative voltage generating circuit 220 comprises: a PMOS transistor P2 connected between a supply node NPU of a pull-up control signal and the pull-up node PU; and a delay circuit DL connected to the supply node NPU and delaying the pull-up control signal. An output of the delay circuit DL achieves a high-speed drive by being capacitively coupled to the pull-up node PU.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an output circuit including a pull-up PMOS transistor and a pull-down NMOS transistor, and more particularly to an output circuit formed in a semiconductor integrated circuit or a semiconductor memory device.

  A push-pull type CMOS inverter or a CMOS buffer including a PMOS transistor and an NMOS transistor is used for an output circuit of a semiconductor device or the like. An output circuit (Patent Document 1) that can output a high-voltage signal while configuring transistors constituting such a CMOS inverter with a low breakdown voltage, an output circuit (Patent Document 2) that suppresses switching noise, and the like are disclosed.

JP 2013-90278 A JP 2012-65235 A

  FIG. 1 is a diagram illustrating a configuration example of a conventional output circuit. The output circuit includes a pull-up PMOS transistor P1 and a pull-down NMOS transistor N1 that constitute a push-pull type CMOS inverter. An output node OUT obtained by coupling the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 is electrically coupled to the output pad 10, for example. The latch circuit or pre-buffer circuit 20 includes an inverter IN1 that receives data DATA, an NOR gate, an inverter IN2 that supplies a pull-up control signal to the pull-up node PU, an inverter IN3 that supplies a pull-down control signal to the NAND gate and a pull-down node PD. Including. The latch circuit 20 generates a pull-up control signal and a pull-down control signal obtained by inverting the logic level of the data DATA, and supplies them to the pull-up node PU and the pull-down node PD.

  The pull-up PMOS transistor P1 is required to have a certain driving capability in order to drive the load connected to the output node OUT, that is, the output pad 10. However, when the internal power supply voltage VDD is lowered along with the miniaturization of the semiconductor integrated circuit, the gate / source voltage Vgs of the pull-up transistor P1 becomes small, and the load connected to the output node OUT is increased at high speed. There is a risk that it cannot be driven. For example, when the power supply voltage VDD is changed from 3.3 V to 1.8 V, the gate-source voltage Vgs when the PMOS transistor P1 is turned on decreases, so that the drain current Id of the PMOS transistor P1 decreases and the output pad 10 It takes longer than necessary to drive the connected load.

  An object of the present invention is to solve such a conventional problem and to provide a push-pull type output circuit capable of driving a load connected to an output node at a higher speed.

  An output circuit according to the present invention includes a P-channel type pull-up transistor connected between a first power supply and an output node, a pull-down transistor connected between a second power supply and the output node, and an input A supply circuit for supplying a pull-up control signal to a pull-up node of the pull-up transistor and a pull-down control signal to a pull-down node of the pull-down transistor according to the logic level of the data that has been generated, and the pull-up transistor controlling the pull-up And a circuit that changes the voltage of the pull-up node to a negative voltage when turned on by a signal.

  In a preferred aspect, the circuit for changing to the negative voltage includes a PMOS transistor connected between a supply node of the pull-up control signal of the supply circuit and the pull-up node, connected to the supply node, and the pull-up circuit A delay circuit for delaying the control signal, and an output of the delay circuit is capacitively coupled to the pull-up node. Preferably, when the pull-up control signal transitions from a high level to a low level, the voltage of the pull-up node is changed to a negative voltage. Preferably, the PMOS transistor includes an N well formed in a p-type semiconductor region, and p-type first and second diffusion regions formed in the N well. The first diffusion region is the supply source. Connected to the node, the second diffusion region is connected to the pull-up node, and the N-well is electrically coupled to a positive power supply voltage. Preferably, the output node is electrically coupled to an output pad of the semiconductor chip.

  According to the present invention, by providing a circuit that changes the voltage of the pull-up node to a negative voltage when the pull-up transistor is turned on, the current flowing through the pull-up transistor is increased and the output node is driven at higher speed. can do.

It is a figure which shows an example of the conventional output circuit. It is a figure which shows the structural example of the output circuit based on the Example of this invention. It is a figure explaining the operation | movement waveform of the output circuit which concerns on the Example of this invention. It is a figure which shows the specific structural example of the output circuit which concerns on the Example of this invention. FIG. 5 is a schematic cross-sectional view of a PMOS transistor of the output circuit shown in FIG. 4. FIG. 5 is a diagram showing voltage waveforms at each node of the output circuit shown in FIG. 4. It is a figure which shows a bootstrap type output circuit.

  The output circuit of the present invention is formed in a semiconductor device such as a semiconductor integrated circuit or a semiconductor memory device or a semiconductor chip. The output circuit of the present invention can be used to drive a circuit in a semiconductor device or to drive another semiconductor device or circuit connected to an output terminal of the semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram illustrating a configuration example of the output circuit according to the embodiment of the present invention. The output circuit 100 of this embodiment includes a logic circuit 200 and a push-pull type inverter 240. The logic circuit 200 receives the data DATA at the input unit 210, generates a pull-up control signal and a pull-down control signal having a complementary relationship according to the logic level of the data DATA, and outputs these control signals to the pull-up node PU. And supplied to the pull-down node PD.

  The inverter 240 includes a pull-up PMOS transistor P1 and a pull-down NMOS transistor N1. The source of the PMOS transistor P1 is connected to the power supply voltage VDD, the gate is connected to the pull-up node PU, and the drain is connected to the output node OUT. The source of the NMOS transistor N1 is connected to the reference potential GND, the gate is connected to the pull-down node PD, and the drain is connected to the output node OUT. The PMOS transistor P1 and the NMOS transistor N1 perform a push-pull operation according to the pull-up control signal and the pull-down control signal. That is, when the pull-up control signal is at L level and the pull-down control signal is at L level, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, and the drain current Id flows from the power supply voltage VDD to the output node OUT. On the other hand, when the pull-up control signal is at the H level and the pull-down control signal is at the H level, the PMOS transistor P1 is turned off, the NMOS transistor N1 is turned on, and the drain current Id flows from the output node OUT to GND. The output node OUT is connected to an output pad of the semiconductor device or another integrated circuit.

  Furthermore, the logic circuit 200 of this embodiment is used to change the L-level pull-up control signal supplied to the pull-up node PU in the negative voltage or negative direction when the pull-up PMOS transistor P1 is turned on. A negative voltage generation circuit 220 is included. That is, when the PMOS transistor P1 is turned on, the pull-up node PU is transited to a negative voltage lower than 0V, and the PMOS transistor P1 is strongly turned on. The configuration of the negative voltage generation circuit 220 is not particularly limited as long as it is a circuit that can transition the voltage of the pull-up node PU in the negative direction. For example, the negative voltage generation circuit 2220 changes the pull-up node PU to a negative voltage using capacitive coupling as described later.

  FIG. 3A schematically shows the voltage waveform at each node of a conventional output circuit that does not include the negative voltage generation circuit 220, and FIG. 3B shows the negative voltage generation of this embodiment. The voltage waveform of each node of the output circuit provided with the circuit is shown. When the data DATA changes from the H level to the L level during the period from the time t1 to the time t2, the logic circuit 200 supplies the pull-up node PU with the L-level pull-up control signal and the pull-down node PD with the H-level pull-down. Supply control signals. As a result, the pull-up PMOS transistor P1 is turned on, the pull-down NMOS transistor N1 is turned off, and the output node OUT outputs an H level signal obtained by inverting the logic level of the data DATA. For example, when the power supply voltage VDD is lowered (3.3 V → 1.8 V), the gate-source voltage of the PMOS transistor P1 becomes insufficient, and the drain current Id also decreases accordingly, and the output node OUT It takes time to drive the connected load capacity.

  On the other hand, in the output circuit 100 of the present embodiment, when the data DATA transitions from the H level to the L level, the negative voltage generation circuit 220 applies the L level pull-up control signal to the negative voltage as shown in FIG. Transition to (−V). Therefore, the gate-source voltage of the pull-up PMOS transistor P1 can be increased as compared with an output circuit that does not change to a negative voltage as shown in FIG. 3A. As a result, the PMOS transistor P1 The drain current Id flowing through can be increased. Therefore, the load capacitance of the output node OUT can be driven at high speed.

  Next, a specific configuration example of the output circuit of this embodiment will be described. FIG. 4 shows an output circuit of the present embodiment, and the same reference numerals are assigned to the same components as those of the output circuit of FIG. As shown in the figure, the output circuit 100 of the present embodiment includes a latch circuit 20 and a CMOS inverter P1 / N1, in addition to a negative voltage generating circuit for changing the voltage of the pull-up node PU to a negative voltage. 220 is included. For example, a 1.8V VDD power supply is connected to the source of the pull-up PMOS transistor P1. An output pad or the like is connected to the output node OUT.

  The latch circuit 20 generates a pull-up control signal at the node NPU, and generates a pull-down control signal complementary to the pull-up control signal at the pull-down node PD. Negative voltage generation circuit 220 includes a PMOS transistor P2 connected between node NPU and pull-up node PU of latch circuit 20, and delay circuit DL connected to node NPU and delaying the pull-up control signal. The output of the delay circuit DL is capacitively coupled to the pull-up node PU. When an L-level pull-up control signal is supplied to the pull-up node PU, the voltage of the pull-up node PU is changed to a negative voltage. The delay circuit DL can be composed of a plurality of inverters, for example.

  FIG. 5 shows a schematic cross section of the PMOS transistor P2. As shown in the figure, the PMOS transistor P 2 is formed in an N well 310 formed in a p-type silicon substrate 300. The substrate 300 is supplied with GND (0 V), and the N well 310 is supplied with a power supply Vcc of 3.3 V, for example, via the n-type diffusion region 320. One p-type diffusion region 330 of the PMOS transistor P2 is connected to the node NPU of the latch circuit 20, and the other p-type diffusion region 340 is connected to the pull-up node PU. The gate is supplied with GND, and the PMOS transistor P2 is always in a conductive state.

  Next, the operation of the output circuit of this embodiment will be described. FIG. 6 schematically shows a voltage waveform at each node of the output circuit. At time T1, the data DATA to the latch circuit 20 changes from L level to H level. In response to this, the output of the NAND gate transitions to the H level, so that at time T2, the pull-down node PD transitions from the H level to the L level, and the pull-down NMOS transistor N1 is turned off.

  Since the NOR gate outputs the H level by the L level input from the inverter IN1 and the L level input from the pull-down node PD, the node NPU transitions from the H level (Vcc) to the L level (0 V) at time T3. . At time T3, since the PMOS transistor P2 is in a conductive state, the L-level pull-up control signal generated at the node NPU is supplied to the pull-up node PU. At this time, the voltage of the pull-up node PU drops from Vcc to Vth (Vth is a threshold value of the PMOS transistor P2). In response to the pull-up node being driven to the L level, the pull-up transistor P1 is turned on.

  Further, at time T4, the delay circuit DL outputs a pull-up control signal delayed for a certain time to the node PU_C. That is, the node PU_C transitions from the H level to the L level. Since node PU_C is capacitively coupled to pull-up node PU, when the voltage at node PU_C drops, the voltage at pull-up node PU is pulled in a negative direction accordingly. In the present embodiment, the capacitive coupling ratio and the like are adjusted so that the pull-up node PU has a negative voltage. When the pull-up node PU transitions to a negative voltage, no forward bias is formed between the diffusion region 340 and the N well 310, so that no through current flows between the substrate 300.

  Since the negative voltage of the pull-up node PU continues for a certain period, the gate-source voltage of the PMOS transistor P1 increases during this period, the PMOS transistor P1 is strongly turned on, and a large drain current Id is supplied to the output node OUT. . Therefore, the load connected to the output node OUT can be driven at high speed.

  FIG. 7 shows an output circuit for driving the pull-up transistor by bootstrap. The pull-up transistor TR1 is composed of an NMOS, and an NMOS transistor TR2 connected to VDD is connected to the gate of the transistor TR1. When the H-level pull-up control signal is supplied to the node NPU, the pull-up node PU becomes Vcc-Vth via the transistor TR2, the transistor TR1 is turned on, and the output node OUT changes to H level. Since it is capacitively coupled to the pull-up node PU, the voltage at the output node OUT rises in response to the rise in the voltage at the output node OUT, and the voltage between the gate and source of the pull-up transistor TR1 increases. Therefore, the pull-up transistor TR1 is strongly turned on. However, if the load capacitance connected to the output node OUT is equal to or greater than a certain value, the potential of the output node OUT immediately decreases, and the voltage of the pull-up node PU cannot be maintained at VDD + Vth. On the other hand, since the output circuit of this embodiment is not configured to change the voltage of the pull-up node PU by the voltage of the output node OUT, the negative voltage of the pull-up node PU can be stably maintained for a certain period. Therefore, it is possible to keep the pull-up transistor strongly turned on.

  In the above embodiment, an example in which the logic circuit 200 includes the latch circuit 20 has been described. However, this is an example and the present invention is not limited to this. The logic circuit 200 may include, for example, a level conversion circuit (level shifter) that changes the voltage of the logic level of data input to the input unit 210 to another voltage, or other pre-buffers or the like. A circuit element other than a circuit or a logic circuit may be included. Further, in the above embodiment, the logic circuit 200 is illustrated as including the negative voltage generation circuit 220. However, the negative voltage generation circuit 220 is not included in the logic circuit 200, but is configured separately from the logic circuit 200. There may be. Further, the power supply Vcc supplied to the logic circuit 200 and the power supply Vdd supplied to the pull-up transistor may have the same voltage value or different voltage values. Further, the logic circuit 200 may generate a pull-up control signal and a pull-down control signal having the same logic level as the input data or a logic level obtained by inverting the logic level of the input data. Good.

  Further, in the above embodiment, the negative voltage generation circuit 220 is illustrated as a circuit for changing the voltage of the pull-up node to a negative voltage. However, the present invention is not limited to the name of the negative voltage generation circuit 220, A circuit having a function of changing the voltage in the negative direction can be applied. Further, in this embodiment, an example in which the output node of the output circuit is connected to the output pad has been shown. However, the output node can be applied to one that drives various loads such as other circuits or other devices.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

10: output circuit 20: latch circuit 100: output circuit 200: logic circuit 210: input unit 220: negative voltage generation circuit 240: inverter 300: p-type substrate 310: N well 320: n-type diffusion region 330: p-type diffusion region 340: p-type diffusion regions P1, P2: PMOS transistor N1: NMOS transistor DL: delay circuit PU: pull-up node PD: pull-down node OUT: output node

Claims (5)

A P-channel type pull-up transistor connected between the first power supply and the output node;
A pull-down transistor connected between a second power supply and the output node;
A supply circuit for supplying a pull-up control signal to a pull-up node of the pull-up transistor and supplying a pull-down control signal to a pull-down node of the pull-down transistor according to a logic level of input data;
An output circuit including: a circuit that changes a voltage of the pull-up node to a negative voltage when the pull-up transistor is turned on by the pull-up control signal. The circuit for changing to the negative voltage includes a PMOS transistor connected between a supply node of the pull-up control signal of the supply circuit and the pull-up node;
A delay circuit connected to the supply node and delaying the pull-up control signal;
The output circuit of claim 1, wherein an output of the delay circuit is capacitively coupled to the pull-up node. The output circuit according to claim 1, wherein when the pull-up control signal transitions from a high level to a low level, the voltage of the pull-up node is changed to a negative voltage. The PMOS transistor includes an N well formed in a p-type semiconductor region, and p-type first and second diffusion regions formed in the N well,
The first diffusion region is connected to the supply node, the second diffusion region is connected to the pull-up node, and the N-well is electrically coupled to a positive power supply voltage. Output circuit described in one. The output circuit according to claim 1, wherein the output node is electrically coupled to an output pad of a semiconductor chip.

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