JPH04328858A - Input/output buffer circuit - Google Patents

Input/output buffer circuit

Info

Publication number
JPH04328858A
JPH04328858A JP3098928A JP9892891A JPH04328858A JP H04328858 A JPH04328858 A JP H04328858A JP 3098928 A JP3098928 A JP 3098928A JP 9892891 A JP9892891 A JP 9892891A JP H04328858 A JPH04328858 A JP H04328858A
Authority
JP
Japan
Prior art keywords
circuit
output
input
buffer circuit
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3098928A
Inventor
Takayasu Sakurai
Kazuhiro Sawada
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3098928A priority Critical patent/JPH04328858A/en
Publication of JPH04328858A publication Critical patent/JPH04328858A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make possible a guarantee of TTL and MOS levels by the output of an input/output buffer circuit by a method wherein the buffer circuit is formed into such a constitution that the gate voltage of a first P-MOSFET and the gate voltage of a first N-MOSFET are controlled by a level conversion circuit at a ground level at the time of the high output of the buffer circuit.
CONSTITUTION: An output control circuit 10 includes a level conversion circuit 20 in its interior, an output control signal EN and an integrated circuit internal signal Dout are inputted in the circuit 10 and an output mode N1 is controlled by the circuit 10 so that a signal level of the node N1 becomes a power-supply voltage Vcc1 level or a power-supply voltage Vcc2 level according to the state of these signals. An output node N4 of an input gate is connected to the interior of an integrated circuit via an input control circuit 30 and transmits a signal Din to the integrated circuit. A gate voltage of a P-MOSFET and a gate voltage of an N-MOSFT are controlled by the circuit 20 at a ground level at the time of a high output of the title buffer circuit. Thereby, TTL and MOS levels are guaranteed by the output of the buffer circuit and a system having not an input leakage voltage is obtained by the input of the buffer circuit.
COPYRIGHT: (C)1992,JPO&Japio
JP3098928A 1991-04-30 1991-04-30 Input/output buffer circuit Pending JPH04328858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3098928A JPH04328858A (en) 1991-04-30 1991-04-30 Input/output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3098928A JPH04328858A (en) 1991-04-30 1991-04-30 Input/output buffer circuit

Publications (1)

Publication Number Publication Date
JPH04328858A true JPH04328858A (en) 1992-11-17

Family

ID=14232792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3098928A Pending JPH04328858A (en) 1991-04-30 1991-04-30 Input/output buffer circuit

Country Status (1)

Country Link
JP (1) JPH04328858A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177341A (en) * 1992-12-04 1994-06-24 Nippon Motorola Ltd Mos type integrated circuit device having complementary inverter output stage
US6812766B2 (en) 2001-05-22 2004-11-02 Matsushita Electric Industrial Co., Ltd. Input/output circuit of semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177341A (en) * 1992-12-04 1994-06-24 Nippon Motorola Ltd Mos type integrated circuit device having complementary inverter output stage
US6812766B2 (en) 2001-05-22 2004-11-02 Matsushita Electric Industrial Co., Ltd. Input/output circuit of semiconductor integrated circuit

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