JP4242226B2 - Level conversion circuit and semiconductor device using the same - Google Patents

Description

  The present invention relates to a level conversion circuit and a semiconductor device using the level conversion circuit, and more particularly to a level conversion circuit for converting a logic level of a signal and a semiconductor device using the level conversion circuit.

  Conventionally, in a semiconductor integrated circuit device, the “L” level is the ground potential GND, the “H” level is the first power supply potential VDD1, and the “L” level is the ground potential GND. There is provided a level conversion circuit for converting the “H” level into a second signal having a second power supply potential VDD2 higher than the first power supply potential VDD1. In this level conversion circuit, two sets of P-channel MOS transistors and N-channel MOS transistors connected in series between the second power supply potential VDD2 line and the ground potential GND line are provided, and the gate of each P-channel MOS transistor is already provided. This is connected to the drain of one P-channel MOS transistor.

There is also a method of reducing the through current flowing through the P-channel MOS transistor and the N-channel MOS transistor by lowering the second power supply potential VDD2 at the time of inversion of the logic level of the signal, thereby increasing the level conversion speed (for example, Patent Document 1).
Japanese Patent Laid-Open No. 2001-24499

  However, in the above method, based on the first signal, a control signal whose “L” level is the ground potential GND and whose “H” level is the second power supply potential VDD2 is generated, and the control signal generates the first signal. Since the two power supply potential VDD2 is controlled, it is necessary to perform level conversion also in the control signal generating circuit, and there is a problem that the configuration becomes complicated.

  Therefore, a main object of the present invention is to provide a level conversion circuit having a small through current, a high level conversion speed, and a simple configuration, and a semiconductor device using the same.

Engaging Relais bell converter to the invention this is a level that the reference potential of the one, the first signal its other level is the first power supply potential, while the level of a reference potential, A level conversion circuit for converting to a second signal that is a second power supply potential whose other level is higher than the first power supply potential, both of which the first electrodes receive the second power supply potential. The first and second transistors of one conductivity type and the potential of the gate electrode of the first transistor from the reference potential in response to the first signal being raised from the reference potential to the first power supply potential A first pulse generation circuit that rises to the first power supply potential and sets the reference potential after a predetermined first time has elapsed, and the first signal is lowered from the first power supply potential to the reference potential Depending on the situation, the potential of the gate electrode of the second transistor A second pulse generating circuit that rises from the reference potential to the first power supply potential and sets the reference potential after a predetermined second time has elapsed, and the first electrodes of the second pulse generation circuit are the first and second transistors, respectively. First gates connected to the first and second output nodes, respectively, and their second electrodes connected to the second and first output nodes, respectively. Conductive type third and fourth transistors and their first electrodes are connected to the second and first output nodes, respectively, and their gate electrodes receive the first signal and its inverted signal, respectively. The second electrode of the second conductive type includes the fifth and sixth transistors of the second conductivity type both receiving a reference potential.

Further, engagement Ru another level conversion circuit of the present invention is a level of the reference potential of the one, the first signal its other level is the first power supply potential, while the level of the reference potential And a level conversion circuit for converting the second level into a second signal that is a second power supply potential whose other level is higher than the first power supply potential, both of which have the second power supply potential. And first and second transistors of the first conductivity type whose gate electrodes receive the first signal and its inverted signal, respectively, and whose first electrodes are the first and second transistors of the first and second transistors, respectively. A first conductive type connected to two electrodes, their gate electrodes connected to first and second output nodes, respectively, and their second electrodes connected to second and first output nodes, respectively. 3rd and 3rd Transistors and their first electrodes are respectively connected to the second and first output nodes, their gate electrodes receive the first signal and its inverted signal, respectively, and their second electrodes are both referenced The fifth and sixth transistors of the second conductivity type receiving the potential, and the potential of the back gate of the fifth transistor in response to the first signal rising from the reference potential to the first power supply potential Is raised from the reference potential to the first power supply potential, and the first signal is changed from the first power supply potential to the reference potential. The first pulse generation circuit sets the reference potential after the elapse of a predetermined first time. In response to the fall, the second pulse that raises the back gate potential of the sixth transistor from the reference potential to the first power supply potential and sets the reference potential after the elapse of a predetermined second time. Generator circuit Those were example.

  The semiconductor device according to the present invention includes a first circuit that outputs a first signal, the level conversion circuit, and a second circuit that receives a second signal. The threshold voltage of the sixth transistor is set lower than the threshold voltage of the transistor of the first circuit.

The engagement Relais bell converter to the present invention this, first to a reference potential the potential of the gate electrode Startup the first power supply potential from the reference potential, after a first predetermined time of the first transistor In response to the first pulse generation circuit and the first signal falling from the first power supply potential to the reference potential, the potential of the gate electrode of the second transistor is raised from the reference potential to the first power supply potential. And a second pulse generation circuit that sets the reference potential after a predetermined second time has elapsed, so that the current driving capability of the third transistor is increased in response to the rising edge of the first signal. The current driving capability of the fourth transistor is smaller than the current driving capability of the third transistor in response to the falling edge of the first signal, and the through current is suppressed. As Le conversion speed is fast. In addition, since the first power supply potential or the reference potential is applied to the gate electrodes of the first and second transistors, the second power supply potential or the reference potential is selectively applied to the gate electrodes of the first and second transistors at a predetermined timing. The configuration can be simplified as compared with the conventional example given in (1).

Further, the engagement Ru another level conversion circuit of the present invention, in response to the first signal is raised to the first power supply potential from the reference potential, the potential of the back gate of the fifth transistor from the reference potential A first pulse generation circuit that rises to the first power supply potential and sets the reference potential after a predetermined first time has elapsed, and the first signal is lowered from the first power supply potential to the reference potential In response, a second pulse generation circuit that raises the potential of the back gate of the sixth transistor from the reference potential to the first power supply potential and sets the reference potential after a predetermined second time has elapsed. Since the first transistor is turned off in response to the falling edge of the first signal, the current driving capability of the fifth transistor is increased, and in response to the falling edge of the first signal. Second transistor is non-conductive Okikuri the current driving force of the sixth transistor with made, the level conversion speed a through current is suppressed is increased. In addition, since the first power supply potential or the reference potential is applied to the back gates of the fifth and sixth transistors, the second power supply potential or the reference potential is selectively applied to the gate electrodes of the first and second transistors at a predetermined timing. The configuration can be simplified as compared with the conventional example given in (1).

  In the semiconductor device according to the present invention, a first circuit that outputs a first signal, the level conversion circuit, and a second circuit that receives a second signal are provided. The threshold voltage of the transistor is set lower than the threshold voltage of the transistor of the first circuit. In this case, the switching speed of the fifth and sixth transistors is increased, and the level conversion speed is further increased.

[Embodiment 1]
1 is a block diagram showing a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, the semiconductor integrated circuit device includes an internal circuit 1, a level conversion circuit 2, and an output circuit 3.

  Internal circuit 1 is driven by first power supply potential VDD1 (eg, 1.0 V) and ground potential GND (0 V), performs a predetermined operation according to input signal φ1, and outputs signal φ2. The “L” level of the signal φ2 is the ground potential GND, and the “H” level is the first power supply potential VDD1.

  Level conversion circuit 2 is driven by first power supply potential VDD1, second power supply potential VDD2 (eg, 3.3V) and ground potential GND, converts the logic level of signal φ2 to generate signal φ3, and generates signal φ3. This is given to the output circuit 3. The “L” level of the signal φ3 is the ground potential GND, and the “H” level is the second power supply potential VDD2.

Output circuit 3 is driven by second power supply potential VDD2 and ground potential GND, generates signal φ4 in response to signal φ3, and outputs signal φ4 to the outside. The internal circuit 1 is composed of a MOS transistor having a relatively thin gate oxide film because the drive voltage VDD1 is as low as 1.0V. The output circuit 3 is composed of a MOS transistor having a relatively thick gate oxide film because the drive voltage VDD2 is as high as 3.3V. Since level conversion circuit 2 is driven by second and second power supply voltages VDD1 and VDD2, it is composed of both a MOS transistor having a relatively thin gate oxide film and a MOS transistor having a relatively thick gate oxide film. .

  FIG. 2 is a circuit diagram showing a configuration of level conversion circuit 2 shown in FIG. In FIG. 2, level conversion circuit 2 includes P channel MOS transistors 11 to 14, N channel MOS transistors 15 and 16, and an inverter 17. The sources of P channel MOS transistors 11 and 12 are both connected to a line of second power supply potential VDD2, and their gates are both connected to a line of ground potential GND. Each of P channel MOS transistors 11 and 12 constitutes a resistance element.

  The sources of P channel MOS transistors 13 and 14 are connected to the drains (nodes N11 and N12) of P channel MOS transistors 11 and 12, respectively, and their gates are the drains of P channel MOS transistors 14 and 13 (nodes N14 and N13), respectively. Connected to. The signal appearing at the node N14 becomes the output signal VO (φ3) of the level conversion circuit 2. An inverted signal of the output signal VO appears at the node N13. The drains of N-channel MOS transistors 15 and 16 are connected to nodes N13 and N14, respectively, and their sources are both connected to the ground potential GND line. Input signal VI (φ 2) is directly input to the gate of N channel MOS transistor 15 and is also input to the gate of N channel MOS transistor 16 via inverter 17.

  Inverter 17 includes a P-channel MOS transistor 18 and an N-channel MOS transistor 19 as shown in FIG. P-channel MOS transistor 18 is connected between the line of first power supply potential VDD1 and output node 17b, and its gate is connected to input node 17a. N channel MOS transistor 19 is connected between output node 17b and the ground potential GND line, and has its gate connected to input node 17a.

  When input signal VI is at "L" level (GND), P channel MOS transistor 18 is turned on and N channel MOS transistor 19 is turned off, and output node 17b is at "H" level (VDD1). When input signal VI is at "H" level (VDD1), P channel MOS transistor 18 is turned off and N channel MOS transistor 19 is turned on, and output node 17b is at "L" level (GND). Therefore, inverted signal / VI of input signal VI appears at output node 17b. Since each of the MOS transistors 18 and 19 is driven by the first power supply voltage VDD1, it has a relatively thin gate oxide film like the MOS transistor of the internal circuit 1. Each of the MOS transistors 11 to 16 in FIG. 2 is driven by the second power supply voltage VDD2, and therefore has a relatively thick gate oxide film, similarly to the MOS transistor of the output circuit 3.

  FIG. 4 is a time chart showing the operation of the level conversion circuit 2 shown in FIGS. In the initial state, it is assumed that the input signal VI is at the “L” level (0 V). At this time, N channel MOS transistor 15 is rendered non-conductive, N channel MOS transistor 16 is rendered conductive, and nodes N13 and N14 attain "H" level (3.3V) and "L" level (0V), respectively. Yes. In addition, P channel MOS transistor 13 becomes conductive and P channel MOS transistor 14 becomes nonconductive, and nodes N11 and N12 are both at "H" level (3.3 V).

When input signal VI rises from "L" level (0V) to "H" level (3.3V) at a certain time t1, N channel MOS transistor 15 shifts to a conductive state and N channel MOS transistor 16 is non-conductive. Transition to the conductive state. In response, the potential at node N13 begins to drop, and P channel MOS transistor 14 shifts to a conductive state. Output signal VO is raised from "L" level (0 V) to "H" level (3.3 V), and P channel MOS transistor 13 is turned off.

  Here, at the moment when the input signal VI rises from the “L” level to the “H” level, the MOS transistors 11, 13, and 15 are both turned on, and the MOS transistor 11, 12 is connected from the second power supply potential VDD 2 line. A through current flows through the ground potential GND line via 13 and 15. However, a voltage drop occurs in P channel MOS transistor 11 constituting the resistance element, the potential of node N11 decreases, the current driving capability of P channel MOS transistor 13 decreases, and the through current is suppressed to a small level.

  On the other hand, though a through current also flows through the MOS transistors 12, 14, and 16, the MOS transistors 12, 14, and 16 do not conduct at the same time even when the input signal VI is raised from the “L” level to the “H” level. The through current flowing through the MOS transistors 12, 14 and 16 is smaller than the through current flowing through the MOS transistors 11, 13 and 15. Therefore, the voltage drop caused by P channel MOS transistor 12 is smaller than the voltage drop caused by P channel MOS transistor 11, and the degree of decrease in current driving capability of P channel MOS transistor 14 is the extent of decrease in current driving capability of P channel MOS transistor 13. Smaller than. Therefore, as compared with the case where P channel MOS transistors 11 and 12 are not provided, the levels of nodes N13 and N14 are changed quickly, and the signal level conversion is performed at a high speed.

  Next, when input signal VI falls from "H" level (3.3 V) to "L" level (0 V) at time t2, N channel MOS transistor 15 shifts to a non-conductive state and N channel MOS transistor The transistor 16 is turned on. In response, the potential at node N14 begins to drop, and P channel MOS transistor 13 shifts to a conductive state. Node N13 is raised from "L" level (0V) to "H" level (3.3V), and P channel MOS transistor 14 is turned off.

  Here, at the moment when the input signal VI falls from the “H” level to the “L” level, the MOS transistors 12, 14, and 16 are both in a conductive state, and the MOS transistor 12, A through current flows through the ground potential GND line via 14 and 16. However, a voltage drop is generated by the P channel MOS transistor 12 constituting the resistance element, the potential of the node N12 is lowered, the current driving capability of the P channel MOS transistor 14 is lowered, and the through current is suppressed to be small.

  On the other hand, though a through current also flows through the MOS transistors 11, 13, and 15, the MOS transistors 11, 13, and 15 do not conduct at the same time even when the input signal VI falls from the “H” level to the “L” level. The through current flowing through the MOS transistors 11, 13 and 15 is smaller than the through current flowing through the MOS transistors 12, 14 and 16. Therefore, the voltage drop due to P channel MOS transistor 11 is smaller than the voltage drop due to P channel MOS transistor 12, and the degree of decrease in current driving capability of P channel MOS transistor 13 is the extent of decrease in current driving capability of P channel MOS transistor 14. Smaller than. Therefore, compared with the case where P channel MOS transistors 11 and 12 are not provided, level conversion of nodes N13 and N14 is performed quickly, and signal level conversion is performed at high speed.

  In the first embodiment, two resistance elements including two P-channel MOS transistors 11 and 12 are connected between two P-channel MOS transistors 13 and 14 that are cross-coupled and a line of the second power supply potential VDD2. In addition, the through current is suppressed and the level conversion speed is increased. Therefore, the circuit configuration can be simplified as compared with the conventional case where the second power supply potential VDD2 or the ground potential GND is applied to the gates of the P-channel MOS transistors 11 and 12 at a predetermined timing.

  Further, if the threshold voltage of N channel MOS transistors 15 and 16 is made lower than the threshold voltage of the N channel MOS transistor of internal circuit 1, the switching speed of N channel MOS transistors 15 and 16 is increased and level conversion is performed. Speed is even faster.

[Embodiment 2]
FIG. 5 is a circuit diagram showing a configuration of level conversion circuit 20 according to the second embodiment of the present invention, and is a diagram to be compared with FIG. Referring to FIG. 5, the level conversion circuit 20 is different from the level conversion circuit 2 of FIG. 2 in that pulse generation circuits 21 and 26 are added.

  The pulse generation circuit 21 includes an odd number (three in the figure) of inverters 22 to 24 and a NOR gate 25 connected in series. Inverters 22 to 24 constitute a delay circuit. Each of inverters 22-24 and NOR gate is driven by first power supply potential VDD1 and ground potential GND, and is formed of a MOS transistor having a relatively thin gate oxide film. Output signal / VI of inverter 17 is input to one input node of NOR gate 25 through inverters 22 to 24 and directly input to the other input node of NOR gate 25. An output signal φ 25 of NOR gate 25 is input to the gate of P channel MOS transistor 11.

  When signal / VI is at “H” level (when signal VI is at “L” level), output signal φ24 of inverter 24 is at “L” level, and output signal φ25 of NOR gate 25 is at “L” level (0V). )It has become. When signal / VI falls from "H" level to "L" level, signal φ25 is raised to "H" level (1V). When the delay time of inverters 22 to 24 elapses and signal φ24 is raised to “H” level, signal φ25 is lowered to “L” level (0 V).

  When signal / VI is at “L” level (when signal VI is at “H” level), output signal φ24 of inverter 24 is at “H” level, and output signal φ25 of NOR gate 25 is at “L” level. ing. Even when signal / VI rises from "L" level to "H" level, signal φ25 remains at "L" level. Even if the delay time of inverters 22 to 24 elapses and signal φ24 falls to “L” level, signal φ25 remains at “L” level. Therefore, as shown in FIG. 6, signal φ25 is pulsed to “H” level in response to the rising edge of signal VI, and remains at “L” level in response to the falling edge of signal VI. It does not change.

  The pulse generation circuit 26 includes an odd number (three in the drawing) of inverters 27 to 29 and a NOR gate 30 connected in series. Inverters 27 to 29 constitute a delay circuit. Each of inverters 27 to 29 is driven by first power supply potential VDD1 and ground potential GND, and is formed of a MOS transistor having a relatively thin gate oxide film. Signal VI is input to one input node of NOR gate 30 via inverters 27 to 29 and directly input to the other input node of NOR gate 30. Output signal φ30 of NOR gate 30 is input to the gate of P-channel MOS transistor 12. This pulse generation circuit 26 operates in the same manner as the pulse generation circuit 21.

  As shown in FIG. 6, the signal φ30 does not change to “L” level (0V) in response to the rising edge of the signal VI, but changes in pulse to “H” level in response to the falling edge of the signal VI. It is raised to (1V).

Next, the operation of the level conversion circuit 20 will be described. The basic operation is the same as that of the level conversion circuit 2 in FIG. However, when signal VI is raised from "L" level to "H" level, signal φ25 is raised to "H" level in a pulsed manner, and the conduction resistance value of P channel MOS transistor 11 is pulsed. As a result, the through current flowing through the MOS transistors 11, 13, and 15 is reduced. On the other hand, signal φ30 remains at the “L” level, and the conduction resistance value of P channel MOS transistor 12 is smaller than the conduction resistance value of P channel MOS transistor 11. Therefore, the level change of the nodes N13 and N14 is performed quickly.

  When signal VI is lowered from "H" level to "L" level, signal φ30 is raised to "H" level in a pulsed manner, and the conduction resistance value of P channel MOS transistor 12 is pulsed. As a result, the through current flowing in the MOS transistors 12, 14, and 16 is suppressed to a small value. On the other hand, signal φ25 remains at “L” level, and the conduction resistance value of P channel MOS transistor 11 is smaller than the conduction resistance value of P channel MOS transistor 12. Therefore, the level change of the nodes N13 and N14 is performed quickly.

  In the second embodiment, P-channel MOS transistors 11 and 12 are connected between cross-coupled P-channel MOS transistors 13 and 14 and the second power supply potential VDD2 line. The gate is set to the first power supply potential VDD1 or the ground potential GND at a predetermined timing. Therefore, the circuit configuration can be simplified as compared with the conventional case where the second power supply potential VDD2 or the ground potential GND is applied to the gates of the P-channel MOS transistors 11 and 12 at a predetermined timing.

  FIG. 7 is a circuit diagram showing a modification of the second embodiment. Referring to FIG. 7, level conversion circuit 31 is different from level conversion circuit 20 in FIG. 5 in that output signals φ25 and φ30 of pulse generation circuits 21 and 26 are applied to the back gates of N channel MOS transistors 15 and 16, respectively. Is also input. When the back gate potentials of N channel MOS transistors 15 and 16 are raised from "L" level (0V) to "H" level (1V), the threshold voltage of N channel MOS transistors 15 and 16 decreases, and current flows. Driving force increases.

  When signal VI is raised from "L" level to "H" level, current driving capability of N channel MOS transistor 15 is increased in a pulse manner, and node N13 is quickly pulled down to "L" level. When signal VI is lowered from "H" level to "L" level, current driving capability of N channel MOS transistor 16 is increased in a pulse manner, and node N14 is rapidly lowered to "L" level. Accordingly, the level conversion speed is increased. Further, the margin of the operation lower limit current is increased, and malfunction due to a decrease in the first power supply potential VDD1 is prevented.

[Embodiment 3]
FIG. 8 is a circuit diagram showing a configuration of level conversion circuit 35 according to the third embodiment of the present invention, and is a diagram to be compared with FIG. Referring to FIG. 8, the level conversion circuit 35 is different from the level conversion circuit 2 of FIG. 2 in that pulse generation circuits 36 and 41 are added.

  The pulse generation circuit 36 includes an odd number (three in the figure) of inverters 37 to 39 and an AND gate 40 connected in series. Inverters 37 to 39 constitute a delay circuit. Each of inverters 37 to 39 and AND gate 40 is driven by first power supply potential VDD1 and ground potential GND, and is formed of a MOS transistor having a relatively thin gate oxide film. Signal VI is input to one input node of AND gate 40 through inverters 37 to 39 and directly input to the other input node of AND gate 40. An output signal φ 40 of AND gate 40 is input to the gate of P channel MOS transistor 11.

When signal VI is at “L” level, output signal φ39 of inverter 39 is at “H” level, and output signal φ40 of AND gate 40 is at “L” level (0 V). When signal VI is raised from “L” level to “H” level, signal φ 40 is raised to “H” level (1 V). When the delay time of inverters 37 to 39 elapses and signal φ39 is lowered to “L” level, signal φ40 is lowered to “L” level (0 V).

  When signal VI is at “H” level, output signal φ39 of inverter 39 is at “L” level, and output signal φ40 of AND gate 40 is at “L” level. Even if the signal VI falls to the “L” level, the signal φ40 remains at the “L” level. Even if the delay time of inverters 37 to 39 elapses and signal φ39 is raised to “H” level, signal φ40 remains at “L” level. Therefore, similarly to signal φ25 in FIG. 6, signal φ40 is pulsed to “H” level in response to the rising edge of signal VI, and “L” level in response to the falling edge of signal VI. It remains unchanged.

  The pulse generation circuit 41 includes an odd number (three in the drawing) of inverters 42 to 44 and an AND gate 45 connected in series. Inverters 42 to 44 constitute a delay circuit. Each of inverters 42 to 44 and AND gate 45 is driven by first power supply potential VDD1 and ground potential GND, and is formed of a MOS transistor having a relatively thin gate oxide film. Output signal / VI of inverter 17 is input to one input node of AND gate 45 through inverters 42 to 44 and directly input to the other input node of AND gate 45. An output signal φ 45 of AND gate 45 is input to the gate of P channel MOS transistor 12.

  Similarly to the signal φ30 in FIG. 6, the signal φ45 does not change to “L” level (0 V) in response to the rising edge of the signal VI, and pulse-wise “H” in response to the falling edge of the signal VI. To the level (1V). Since other configurations and operations are the same as those in the second embodiment, description thereof will not be repeated.

  In the third embodiment, the same effect as in the second embodiment can be obtained.

  FIG. 9 is a circuit diagram showing a modification of the third embodiment. Referring to FIG. 9, level conversion circuit 46 is different from level conversion circuit 35 of FIG. 8 in that output signals φ40 and φ45 of pulse generation circuits 36 and 41 are applied to the back gates of N channel MOS transistors 15 and 16, respectively. Is also input. When the back gate potentials of N channel MOS transistors 15 and 16 are raised from "L" level (0V) to "H" level (1V), the threshold voltage of N channel MOS transistors 15 and 16 decreases, and current flows. Driving force increases.

  When signal VI is raised from "L" level to "H" level, current driving capability of N channel MOS transistor 15 is increased in a pulse manner, and node N13 is quickly pulled down to "L" level. When signal VI is lowered from "H" level to "L" level, current driving capability of N channel MOS transistor 16 is increased in a pulse manner, and node N14 is rapidly lowered to "L" level. Accordingly, the level conversion speed is further increased. Further, the margin of the operation lower limit voltage is increased, and malfunction due to the decrease in the first power supply potential VDD1 is prevented.

[Embodiment 4]
FIG. 10 is a circuit diagram showing a configuration of level conversion circuit 51 according to the fourth embodiment of the present invention, which is compared with FIG. Referring to FIG. 10, level conversion circuit 51 is different from level conversion circuit 31 in FIG. 7 in that the gate of P channel MOS transistor 11 receives input signal VI instead of output signal φ25 of pulse generation circuit 21, and The gate of P channel MOS transistor 12 receives output signal / VI of inverter 17 instead of output signal φ30 of pulse generation circuit 26.

  In level converting circuit 51, when input signal VI is raised from "L" level (0V) to "H" level (1V), the conduction resistance value of P channel MOS transistor 11 is increased and P channel MOS is increased. The conduction resistance value of the transistor 12 is lowered. In response to the rising edge of input signal VI, signal .phi.25 is raised to "H" level (1.0 V) in a pulse manner, and the current driving capability of N channel MOS transistor 15 is increased. Therefore, the through current of MOS transistors 11, 13, and 15 is suppressed, node N13 is quickly pulled down to "L" level, and node N14 is quickly pulled up to "H" level.

  When input signal VI falls from "H" level (1V) to "L" level (0V), the conduction resistance value of P channel MOS transistor 11 is lowered and the conduction resistance of P channel MOS transistor 12 is reduced. The value becomes higher. In response to the falling edge of input signal VI, signal φ30 is raised to the “H” level (1.0 V) in a pulsed manner, and the current driving capability of N channel MOS transistor 16 is increased. Therefore, the through current of MOS transistors 12, 14, and 16 is suppressed, node N13 is quickly pulled up to "H" level, and node N14 is quickly pulled down to "L" level.

  In the fourth embodiment, P-channel MOS transistors 11 and 12 are connected between cross-coupled P-channel MOS transistors 13 and 14 and the second power supply potential VDD2 line. Each gate is set to the first power supply potential VDD1 or the ground potential GND at a predetermined timing to suppress the through current and increase the level conversion speed. Therefore, the circuit configuration can be simplified as compared with the conventional case where the second power supply potential VDD2 or the ground potential GND is applied to the gates of the P-channel MOS transistors 11 and 12 at a predetermined timing.

[Embodiment 5]
FIG. 11 is a circuit diagram showing a configuration of level converting circuit 52 according to the fifth embodiment of the present invention, and is a diagram to be compared with FIG. Referring to FIG. 11, level conversion circuit 52 is different from level conversion circuit 46 of FIG. 9 in that the gate of P channel MOS transistor 11 receives input signal VI instead of output signal φ40 of pulse generation circuit 36, The gate of P-channel MOS transistor 12 receives output signal / VI of inverter 17 instead of output signal φ45 of pulse generation circuit 41.

  In level converting circuit 52, when input signal VI is raised from "L" level (0V) to "H" level (1V), the conduction resistance value of P channel MOS transistor 11 is increased and P channel MOS is increased. The conduction resistance value of the transistor 12 is lowered. Further, in response to the rising edge of input signal VI, signal φ40 is raised to the “H” level (1.0 V) in a pulse manner, and the current driving capability of N channel MOS transistor 15 increases. Therefore, the through current of MOS transistors 11, 13, and 15 is suppressed, node N13 is quickly pulled down to "L" level, and node N14 is quickly pulled up to "H" level.

  When input signal VI falls from "H" level (1V) to "L" level (0V), the conduction resistance value of P channel MOS transistor 11 is lowered and the conduction resistance of P channel MOS transistor 12 is reduced. The value becomes higher. In response to the falling edge of input signal VI, signal .phi.45 is raised to "H" level (1.0 V) in a pulse manner, and the current driving capability of N channel MOS transistor 16 is increased. Therefore, the through current of MOS transistors 12, 14, and 16 is suppressed, node N13 is quickly pulled up to "H" level, and node N14 is quickly pulled down to "L" level.

  In the fifth embodiment, the same effect as in the fourth embodiment can be obtained.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a level conversion circuit shown in FIG. 1. FIG. 3 is a circuit diagram illustrating a configuration of an inverter illustrated in FIG. 2. FIG. 4 is a time chart showing the operation of the level conversion circuit shown in FIGS. 2 and 3. FIG. It is a circuit diagram which shows the structure of the level conversion circuit by Embodiment 2 of this invention. 6 is a time chart showing the operation of the level conversion circuit shown in FIG. 5. FIG. 10 is a circuit diagram showing a modification of the second embodiment. It is a circuit diagram which shows the structure of the level conversion circuit by Embodiment 3 of this invention. FIG. 10 is a circuit diagram showing a modification of the third embodiment. It is a circuit diagram which shows the structure of the level conversion circuit by Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the level conversion circuit by Embodiment 5 of this invention.

Explanation of symbols

  1 internal circuit, 2, 20, 31, 35, 46, 51, 52 level conversion circuit, 3 output circuit, 11-14, 18 P channel MOS transistor, 15, 16, 19 N channel MOS transistor, 17, 22-24 27-29, 37-39, 42-44 Inverter, 21, 26, 36, 41 Pulse generation circuit, 25, 30 NOR gate, 40, 45 AND gate.

Claims (8)

The first signal whose one level is the reference potential and the other level is the first power supply potential, the one level is the reference potential, and the other level is the first power supply potential. A level conversion circuit for converting to a second signal having a higher second power supply potential,
First and second transistors of a first conductivity type, whose first electrodes both receive the second power supply potential;
In response to the first signal being raised from the reference potential to the first power supply potential, the potential of the gate electrode of the first transistor is raised from the reference potential to the first power supply potential. A first pulse generation circuit that sets the reference potential after the elapse of a predetermined first time;
In response to the first signal falling from the first power supply potential to the reference potential, the potential of the gate electrode of the second transistor is raised from the reference potential to the first power supply potential. , A second pulse generation circuit that sets the reference potential after a predetermined second time,
The first electrodes are respectively connected to the second electrodes of the first and second transistors, the gate electrodes are respectively connected to the first and second output nodes, and the second electrodes are Third and fourth transistors of a first conductivity type connected to the second and first output nodes, respectively, and their first electrodes connected to the second and first output nodes, respectively; A level conversion circuit comprising fifth and sixth transistors of the second conductivity type, each of which has a gate electrode receiving the first signal and its inverted signal, and whose second electrodes both receive the reference potential. . 2. The level conversion circuit according to claim 1 , wherein gate electrodes of the first and second transistors are connected to back gates of the fifth and sixth transistors, respectively. The first pulse generation circuit includes:
A first delay circuit including an odd number of first inverters connected in series and delaying an inverted signal of the first signal by the predetermined first time; Including a first NOR gate circuit in which the other input node receives the inverted signal of the first signal, the output node of which is connected to the gate electrode of the first transistor,
The second pulse generation circuit includes:
A second delay circuit including an odd number of second inverters connected in series and delaying the first signal by the predetermined second time, and one input node of which is the second delay circuit; receiving the output signal, and the other input node receives the first signal, including a second NOR gate circuit whose output node is connected to a gate electrode of the second transistor, according to claim 1 or claim 3. The level conversion circuit according to 2. The first pulse generation circuit includes:
A first delay circuit including an odd number of first inverters connected in series and delaying the first signal by the predetermined first time; and one input node of the first delay circuit is the first delay circuit A first AND gate circuit in which the other input node receives the first signal and the output node is connected to the gate electrode of the first transistor;
The second pulse generation circuit includes:
A second delay circuit including an odd number of second inverters connected in series and delaying the inverted signal of the first signal by the predetermined second time; Including a second AND gate circuit in which the other input node receives the inverted signal of the first signal and the output node is connected to the gate electrode of the second transistor. The level conversion circuit according to claim 1 or 2 . The first signal whose one level is the reference potential and the other level is the first power supply potential, the one level is the reference potential, and the other level is the first power supply potential. A level conversion circuit for converting to a second signal having a higher second power supply potential,
First and second transistors of a first conductivity type, both having their first electrodes receiving the second power supply potential and their gate electrodes receiving the first signal and its inverted signal, respectively;
The first electrodes are respectively connected to the second electrodes of the first and second transistors, the gate electrodes are respectively connected to the first and second output nodes, and the second electrodes are Third and fourth transistors of a first conductivity type respectively connected to the second and first output nodes;
The first electrodes are connected to the second and first output nodes, respectively, the gate electrodes receive the first signal and its inverted signal, respectively, and both of the second electrodes are the reference potential. Fifth and sixth transistors of the second conductivity type receiving
The back gate potential of the fifth transistor is raised from the reference potential to the first power supply potential in response to the first signal being raised from the reference potential to the first power supply potential. A first pulse generation circuit for setting the reference potential after elapse of a predetermined first time, and in response to the first signal being lowered from the first power supply potential to the reference potential And a second pulse generation circuit that raises the potential of the back gate of the sixth transistor from the reference potential to the first power supply potential, and sets the reference potential after the elapse of a predetermined second time. Level conversion circuit. The first pulse generation circuit includes:
A first delay circuit including an odd number of first inverters connected in series and delaying an inverted signal of the first signal by the predetermined first time; Including a first NOR gate circuit whose other input node receives an inverted signal of the first signal, and whose output node is connected to the back gate of the fifth transistor,
The second pulse generation circuit includes:
A second delay circuit including an odd number of second inverters connected in series and delaying the first signal by the predetermined second time, and one input node of which is the second delay circuit; receiving an output signal, and the other input node receives the first signal, including a second NOR gate circuit whose output node is connected to the back gate of said sixth transistor, according to claim 5 Level conversion circuit. The first pulse generation circuit includes:
A first delay circuit including an odd number of first inverters connected in series and delaying the first signal by the predetermined first time; and one input node of the first delay circuit is the first delay circuit And the other input node receives the first signal, and the output node includes a first AND gate circuit connected to the gate electrode of the fifth transistor,
The second pulse generation circuit includes:
A second delay circuit including an odd number of second inverters connected in series and delaying the inverted signal of the first signal by the predetermined second time; Including a second AND gate circuit in which the other input node receives the inverted signal of the first signal and the output node is connected to the back gate of the sixth transistor. The level conversion circuit according to claim 5 . A first circuit that outputs the first signal, a level conversion circuit according to any one of claims 1 to 7 , and a second circuit that receives the second signal,
The semiconductor device, wherein threshold voltages of the fifth and sixth transistors are set lower than a threshold voltage of the transistors of the first circuit.

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